MT4HTF12864HZ-800XX - Micron Technology, Inc.

DDR2 SDRAM SODIMM

MT4HTF3264HZ – 256MB

MT4HTF6464HZ – 512MB

MT4HTF12864HZ – 1GB

Features

•200-pin, small-outline dual in-line memory module

(SODIMM)

•Fast data transfer rates: PC2-3200, PC2-4200,

PC2-5300, or PC2-6400

•256MB (32 Meg x 64), 512MB (64 Meg x 64), 1GB

(128 Meg x 64)

•VDD = VDDQ = 1.8V

•VDDSPD = 1.7–3.6V

•JEDEC-standard 1.8V I/O (SSTL_18-compatible)

•Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

•Multiple internal device banks for concurrent opera-

tion

•Programmable CAS latency (CL)

•Posted CAS additive latency (AL)

•WRITE latency = READ latency - 1 tCK

•Programmable burst lengths (BL): 4 or 8

•Adjustable data-output drive strength

•64ms, 8192-cycle refresh

•On-die termination (ODT)

•Halogen-free

•Serial presence detect (SPD) with EEPROM

•Gold edge contacts

•Single rank

Figure 1: 200-Pin SODIMM (MO-224 R/C C)

Module height: 30mm (1.181in)

Options Marking

•Operating temperature

–Commercial (0°C ≤ TA ≤ +70°C) None

–Industrial (–40°C ≤ TA ≤ +85°C)1I

•Package

–200-pin DIMM (halogen-free) Z

•Frequency/CL2

–2.5ns @ CL = 5 (DDR2-800) -80E

–2.5ns @ CL = 6 (DDR2-800) -800

–3.0ns @ CL = 5 (DDR2-667) -667

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. CL = CAS (READ) latency.

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns)

tRP

(ns)

tRC

(ns)CL = 6 CL = 5 CL = 4 CL = 3

-80E PC2-6400 800 800 533 400 12.5 12.5 55

-800 PC2-6400 800 667 533 400 15 15 55

-667 PC2-5300 –667 553 400 15 15 55

-53E PC2-4200 – – 553 400 15 15 55

-40E PC2-3200 – – 400 400 15 15 55

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 256MB 512MB 1GB

Refresh count 8K 8K 8K

Row address 8K A[12:0] 8K A[12:0] 16K A[13:0]

Device bank address 4 BA[1:0] 8 BA[2:0] 8 BA[2:0]

Device configuration 512Mb (32 Meg x 16) 1Gb (64 Meg x 16) 2Gb (128 Meg x16)

Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]

Module rank address 1 S0# 1 S0# 1 S0#

Table 3: Part Numbers and Timing Parameters – 256MB

Base device: MT47H32M16,1 512Mb DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT4HTF3264H(I)Z-80E__ 256MB 32 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5

MT4HTF3264H(I)Z-800__ 256MB 32 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6

MT4HTF3264H(I)Z-667__ 256MB 32 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Table 4: Part Numbers and Timing Parameters – 512MB

Base device: MT47H64M16,1 1Gb DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT4HTF6464H(I)Z-80E__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5

MT4HTF6464H(I)Z-800__ 512MB 64 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6

MT4HTF6464H(I)Z-667__ 512MB 64 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Table 5: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT47H128M16,1 2Gb DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT4HTF12864H(I)Z-80E__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 5-5-5

MT4HTF12864H(I)Z-800__ 1GB 128 Meg x 64 6.4 GB/s 2.5ns/800 MT/s 6-6-6

MT4HTF12864H(I)Z-667__ 1GB 128 Meg x 64 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Notes: 1. The data sheet for the base device can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT4HTF6464HZ-667H1.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Features

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Pin Assignments

Table 6: Pin Assignments

200-Pin DDR2 SODIMM Front 200-Pin DDR2 SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VREF 51 DQS2 101 A1 151 DQ42 2 VSS 52 DM2 102 A0 152 DQ46

3 VSS 53 VSS 103 VDD 153 DQ43 4 DQ4 54 VSS 104 VDD 154 DQ47

5 DQ0 55 DQ18 105 A10 155 VSS 6 DQ5 56 DQ22 106 BA1 156 VSS

7 DQ1 57 DQ19 107 BA0 157 DQ48 8 VSS 58 DQ23 108 RAS# 158 DQ52

9 VSS 59 VSS 109 WE# 159 DQ49 10 DM0 60 VSS 110 S0# 160 DQ53

11 DQS0# 61 DQ24 111 VDD 161 VSS 12 VSS 62 DQ28 112 VDD 162 VSS

13 DQS0 63 DQ25 113 CAS# 163 NC 14 DQ6 64 DQ29 114 ODT0 164 CK1

15 VSS 65 VSS 115 NC 165 VSS 16 DQ7 66 VSS 116 NC/A132166 CK1#

17 DQ2 67 DM3 117 VDD 167 DQS6# 18 VSS 68 DQS3# 118 VDD 168 VSS

19 DQ3 69 NC 119 NC 169 DQS6 20 DQ12 70 DQS3 120 NC 170 DM6

21 VSS 71 VSS 121 VSS 171 VSS 22 DQ13 72 VSS 122 VSS 172 VSS

23 DQ8 73 DQ26 123 DQ32 173 DQ50 24 VSS 74 DQ30 124 DQ36 174 DQ54

25 DQ9 75 DQ27 125 DQ33 175 DQ51 26 DM1 76 DQ31 126 DQ37 176 DQ55

27 VSS 77 VSS 127 VSS 177 VSS 28 VSS 78 VSS 128 VSS 178 VSS

29 DQS1# 79 CKE0 129 DQS4# 179 DQ56 30 CK0 80 NC 130 DM4 180 DQ60

31 DQS1 81 VDD 131 DQS4 181 DQ57 32 CK0# 82 VDD 132 VSS 182 DQ61

33 VSS 83 NC 133 VSS 183 VSS 34 VSS 84 NC 134 DQ38 184 VSS

35 DQ10 85 NC/BA21135 DQ34 185 DM7 36 DQ14 86 NC 136 DQ39 186 DQS7#

37 DQ11 87 VDD 137 DQ35 187 VSS 38 DQ15 88 VDD 138 VSS 188 DQS7

39 VSS 89 A12 139 VSS 189 DQ58 40 VSS 90 A11 140 DQ44 190 VSS

41 VSS 91 A9 141 DQ40 191 DQ59 42 VSS 92 A7 142 DQ45 192 DQ62

43 DQ16 93 A8 143 DQ41 193 VSS 44 DQ20 94 A6 144 VSS 194 DQ63

45 DQ17 95 VDD 145 VSS 195 SDA 46 DQ21 96 VDD 146 DQS5# 196 VSS

47 VSS 97 A5 147 DM5 197 SCL 48 VSS 98 A4 148 DQS5 198 SA0

49 DQS2# 99 A3 149 VSS 199 VDDSPD 50 NC 100 A2 150 VSS 200 SA1

Notes: 1. Pin 85 is NC for 256MB, BA2 for 512MB and 1GB.

2. Pin 116 is NC for 256MB and 512MB, A13 for 1GB.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Pin Assignments

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Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR2

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 7: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments Table for density-specific

addressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, and MR3) is loaded during the LOAD MODE command.

CKx,

CK#x

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DDR2 SDRAM.

DMx, Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This

signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.

S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C

bus.

SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the

SPD EEPROM on the I2C bus.

CBx I/O Check bits. Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQS#x

I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-

troller. Output with read data; input with write data for source synchronous opera-

tion. DQS# is only used when differential data strobe mode is enabled via the LOAD

MODE command.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Pin Descriptions

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Table 7: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on

the I2C bus.

RDQSx,

RDQS#x

Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS

is output with read data only and is ignored during write data. When RDQS is disa-

bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled

and differential data strobe mode is enabled.

Err_Out# Output

(open drain)

Parity error output: Parity error found on the command and address bus.

VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-

ule VDD.

VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.

VREF Supply Reference voltage: VDD/2.

VSS Supply Ground.

NC –No connect: These pins are not connected on the module.

NF –No function: These pins are connected within the module, but provide no functionality.

NU –Not used: These pins are not used in specific module configurations/operations.

RFU –Reserved for future use.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Pin Descriptions

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Functional Block Diagram

Figure 2: Functional Block Diagram

BA[2/1:0]

A[13/12:0]

RAS#

CAS#

WE#

CKE0

ODT0

BA[2/1:0]: DDR2 SDRAM

A[13/12:0]: DDR2 SDRAM

RAS#: DDR2 SDRAM

CAS#: DDR2 SDRAM

WE#: DDR2 SDRAM

CKE0: DDR2 SDRAM

ODT0: DDR2 SDRAM

DDR SDRAM

U1, U2

CK0

CK0#

DDR SDRAM

U3, U4

CK1

CK1#

Serial PD

A1 A2

SA0 SA1

SDASCL

VREF

VSS

DDR2 SDRAM

VDD

VDDSPD Serial PD

DDR2 SDRAM

DQS

DQS#

DQS

DQS#

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS0

DQS0#

DM0

DQS1

DQS1#

DM1

CS#

DQS

DQS#

DQS

DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS2

DQS2#

DM2

DQS3

DQS3#

DM3

CS#

DQS

DQS#

DQS

DQS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS4

DQS4#

DM4

DQS5

DQS5#

DM5

CS#

DQS

DQS#

DQS

DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS7

DQS7#

DM7

DQS6

DQS6#

DM6

CS#

S0#

VSS

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Functional Block Diagram

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General Description

DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM

modules use DDR architecture to achieve high-speed operation. DDR2 architecture is

essentially a 4n-prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM

module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the

internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-

fers at the I/O pins.

DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-

mitted externally, along with data, for use in data capture at the receiver. DQS is a

strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-

troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned

with data for WRITEs.

DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands (address and control signals) are registered at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-

ule type and various SDRAM organizations and timing parameters. The remaining 128

bytes of storage are available for use by the customer. System READ/WRITE operations

between the master (system logic) and the slave EEPROM device occur via a standard

I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect

(WP) is connected to VSS, permanently disabling hardware write protection.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

General Description

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in the device data sheet are not implied. Exposure to

absolute maximum rating conditions for extended periods may adversely affect reliability.

Table 8: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V

IIInput leakage current; Any input 0V ≤ VIN ≤

VDD; VREF input 0V ≤ VIN ≤ 0.95V; (All other

pins not under test = 0V)

Address inputs, RAS#, CAS#,

WE#, S#, CKE, ODT, BA

–20 20 µA

CK, CK# –10 10

DM –5 5

IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ;

DQ and ODT are disabled

DQ, DQS, DQS# –5 5 µA

IVREF VREF leakage current; VREF = valid VREF level –8 8 µA

TAModule ambient operating temperature Commercial 0 +70 °C

Industrial –40 +85 °C

TC1DDR2 SDRAM component operating tem-

perature2

Commercial 0 +85 °C

Industrial –40 +95 °C

Notes: 1. The refresh rate is required to double when TC exceeds 85°C.

2. For further information, refer to technical note TN-00-08: "Thermal Applications," avail-

able on Micron’s Web site.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron's Web site. Module speed grades cor-

relate with component speed grades.

Table 9: Module and Component Speed Grades

DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-1GA -187E

-80E -25E

-800 -25

-667 -3

-53E -37E

-40E -5E

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level. Mi-

cron encourages designers to simulate the signal characteristics of the system's memo-

ry bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

DRAM Operating Conditions

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IDD Specifications

Table 10: DDR2 IDD Specifications and Conditions – 256MB

Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)

component data sheet

Parameter Symbol

-80E/

-800 -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD0 540 480 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL

(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data pattern is same as IDD4W

IDD1 660 600 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW;

Other control and address bus inputs are stable; Data bus inputs are floating

IDD2P 28 28 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs

are floating

IDD2Q 260 220 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is

HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-

ing

IDD2N 280 240 mA

Active power-down current: All device banks open; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

IDD3P 160 140 mA

Slow PDN exit

MR[12] = 1

48 48

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control

and address bus inputs are switching; Data bus inputs are switching

IDD3N 300 280 mA

Operating burst write current: All device banks open; Continuous burst writes; BL

= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data

bus inputs are switching

IDD4W 1180 1000 mA

Operating burst read current: All device banks open; Continuous burst read, IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-

ing; Data bus inputs are switching

IDD4R 1100 940 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus

inputs are switching; Data bus inputs are switching

IDD5 920 740 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

IDD6 28 28 mA

Operating bank interleave read current: All device banks interleaving reads; IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC

(IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are switch-

ing

IDD7 1480 1400 mA

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

IDD Specifications

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Table 11: DDR2 IDD Specifications and Conditions – 512MB (Die Revision E and G)

Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-

ponent data sheet

Parameter Symbol

-80E/

-800 -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD0 600 540 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL

(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data pattern is same as IDD4W

IDD1 700 520 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW;

Other control and address bus inputs are stable; Data bus inputs are floating

IDD2P 28 28 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs

are floating

IDD2Q 300 260 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is

HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-

ing

IDD2N 320 280 mA

Active power-down current: All device banks open; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

IDD3P 160 120 mA

Slow PDN exit

MR[12] = 1

40 40

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control

and address bus inputs are switching; Data bus inputs are switching

IDD3N 340 300 mA

Operating burst write current: All device banks open; Continuous burst writes; BL

= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data

bus inputs are switching

IDD4W 1260 800 mA

Operating burst read current: All device banks open; Continuous burst read, IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-

ing; Data bus inputs are switching

IDD4R 1280 880 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus

inputs are switching; Data bus inputs are switching

IDD5 1200 1080 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

IDD6 28 28 mA

Operating bank interleave read current: All device banks interleaving reads; IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC

(IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are switch-

ing

IDD7 1760 1400 mA

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

IDD Specifications

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Table 12: DDR2 IDD Specifications and Conditions – 512MB (Die Revision H)

Values shown for MT47H64M16 DDR2 SDRAM only and are computed from values specified in the 1Gb (64 Meg x 16) com-

ponent data sheet

Parameter Symbol

-80E/

-800 -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD0 320 300 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL

(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data pattern is same as IDD4W

IDD1 380 360 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW;

Other control and address bus inputs are stable; Data bus inputs are floating

IDD2P 28 28 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs

are floating

IDD2Q 104 104 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is

HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-

ing

IDD2N 120 104 mA

Active power-down current: All device banks open; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

IDD3P 80 60 mA

Slow PDN exit

MR[12] = 1

40 40

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control

and address bus inputs are switching; Data bus inputs are switching

IDD3N 140 128 mA

Operating burst write current: All device banks open; Continuous burst writes; BL

= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data

bus inputs are switching

IDD4W 640 540 mA

Operating burst read current: All device banks open; Continuous burst read, IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-

ing; Data bus inputs are switching

IDD4R 600 500 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus

inputs are switching; Data bus inputs are switching

IDD5 600 580 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

IDD6 28 28 mA

Operating bank interleave read current: All device banks interleaving reads; IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC

(IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are switch-

ing

IDD7 1040 920 mA

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

IDD Specifications

PDF: 09005aef83c05a5d

htf4c32_64_128x64hz.pdf - Rev. C 9/10 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 13: DDR2 IDD Specifications and Conditions – 1GB

Values shown for MT47H128M16 DDR2 SDRAM only and are computed from values specified in the 2Gb (128 Meg x 16)

component data sheet

Parameter Symbol

-80E/

-800 -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

IDD0 600 540 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL

(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data pattern is same as IDD4W

IDD1 720 640 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW;

Other control and address bus inputs are stable; Data bus inputs are floating

IDD2P 48 48 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs

are floating

IDD2Q 300 260 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is

HIGH; Other control and address bus inputs are switching; Data bus inputs are switch-

ing

IDD2N 320 280 mA

Active power-down current: All device banks open; tCK = tCK

(IDD); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

IDD3P 180 160 mA

Slow PDN exit

MR[12] = 1

56 56

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX

(IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control

and address bus inputs are switching; Data bus inputs are switching

IDD3N 340 300 mA

Operating burst write current: All device banks open; Continuous burst writes; BL

= 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is

HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data

bus inputs are switching

IDD4W 1080 1000 mA

Operating burst read current: All device banks open; Continuous burst read, IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switch-

ing; Data bus inputs are switching

IDD4R 1180 1100 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus

inputs are switching; Data bus inputs are switching

IDD5 1200 1120 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

IDD6 48 48 mA

Operating bank interleave read current: All device banks interleaving reads; IOUT

= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC

(IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are switch-

ing

IDD7 1780 1580 mA

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

IDD Specifications

PDF: 09005aef83c05a5d

htf4c32_64_128x64hz.pdf - Rev. C 9/10 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Serial Presence-Detect

For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 14: SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 1.7 3.6 V

Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V

Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V

Output low voltage: IOUT = 3mA VOL –0.4 V

Input leakage current: VIN = GND to VDD ILI 0.1 3 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA

Standby current ISB 1.6 4 µA

Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA

Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA

Table 15: SPD EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time bus must be free before a new transition can start tBUF 1.3 –µs

Data-out hold time tDH 200 –ns

SDA and SCL fall time tF–300 ns 2

SDA and SCL rise time tR–300 ns 2

Data-in hold time tHD:DAT 0 –µs

Start condition hold time tHD:STA 0.6 –µs

Clock HIGH period tHIGH 0.6 –µs

Noise suppression time constant at SCL, SDA inputs tI–50 ns

Clock LOW period tLOW 1.3 –µs

SCL clock frequency tSCL –400 kHz

Data-in setup time tSU:DAT 100 –ns

Start condition setup time tSU:STA 0.6 –µs 3

Stop condition setup time tSU:STO 0.6 –µs

WRITE cycle time tWRC –10 ms 4

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1

and the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a

write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the

WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-

up resistance, and the EEPROM does not respond to its slave address.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Serial Presence-Detect

PDF: 09005aef83c05a5d

htf4c32_64_128x64hz.pdf - Rev. C 9/10 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Module Dimensions

Figure 3: 200-Pin DDR2 SODIMM

2.45 (0.096)

MAX

PIN 1

67.75 (2.67)

67.45 (2.65)

20.0 (0.787)

TYP

1.80 (0.071)

(2X)

0.6 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

PIN 199

PIN 200 PIN 2

Front view

2.0 (0.079)

TYP

6.0 (0.236)

TYP

63.6 (2.504)

TYP

0.5 (0.0197) R

29.85 (1.175)

30.15 (1.187)

Back view

1.1 (0.043)

0.9 (0.035)

47.4 (1.87)

TYP 11.4 (0.45)

TYP

4.2 (0.165)

TYP

16.25 (0.64)

TYP

3.5 (0.138)

TYP

45° 4X

U1 U2

U3 U4

No components this side of module

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for

additional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

256MB, 512MB, 1GB (x64, SR) 200-Pin DDR2 SODIMM

Module Dimensions

PDF: 09005aef83c05a5d

htf4c32_64_128x64hz.pdf - Rev. C 9/10 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice.