Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-95
310D—04/12/05
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/ProTM
Pin Configuration
• Up to 124MHz frequency support.
• Spread Spectrum for EMI control ±0.5% center
spread and ±0.25% center spread
• Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.
• Provides the following system clocks
- 4-CPUs @ 3.3V, up to 124MHz.
- 13-SDRAMs @3.3V , up to 124MHz
(including SDRAM_F)
- 6-PCI @3.3V , CPU/2 or CPU/3
(including PCICLK_F)
(including 1 free running).
- 1-24MHz @3.3V fixed.
- 1-48MHz @3.3V fixed.
- 2-REF @3.3V , 14.318MHz.
• Efficient Power management scheme through PCI
and STOP CLOCKS.
• Spread Spectrum ±.25%, & ±.5% center spread
48-Pin SSOP
Power Groups
VDDCPU, GNDCPU = CPUCLK [2:0], CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS [11:0], SDRAM_F
VDDPCI, GNDPCI = PCICLKS [4:0], PCICLK_F
VDD48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2
* Internal Pull-up Resistor of 240K to VDD
The ICS9248-95 is the single chip clock solution for Desktop
designs using the VIA MVP4 style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-95
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
2
ICS9248-95
310D—04/12/05
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS9248-95
310D—04/12/05
Functionality
VDD1,2,3 = 3.3V±5%, VDDL1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
Mode Pin - Power Management Input Control
3SF2SF1SF0SF UPC )zHM( ICP )zHM(
0000 00.42133.14
0001 00.02100.04
0010 99.41133.83
0011 99.90166.63
0100 00.50100.53
0101 13.3856.14
0110 00.0800.04
0111 00.5705.7
3
1000 00.00133.33
1001 91.5937.13
1010 13.3877.72
1011 00.0876.62
1100 00.0900.03
1101 00.0700.53
1110 28.6614.33
1111 00.0600.03
EDOM )tupnIdehctaL(
0#POTS_ICP )tupnI(
10FER )tuptuO(
4
ICS9248-95
310D—04/12/05
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller . The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time .
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Recei ver)
Start Bit
Address
D3(H) ACK
Byte Count
ACK Byte 0
ACK Byte 1
ACK Byte 2
ACK Byte 3
ACK Byte 4
ACK Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2(H) ACK
Dummy Command Code ACK
Dummy Byte Count ACK
Byte 0 ACK
Byte 1 ACK
Byte 2 ACK
Byte 3 ACK
Byte 4 ACK
Byte 5 ACK
Stop Bit
How to Write:
5
ICS9248-95
310D—04/12/05
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note 1. Default at Power-up will be for latched logic inputs to define frequency.
Bit [2, 6:4] are default to 0000.
I2C is a trademark of Philips Corporation
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000000.42133.14
100000.02100.04
010099.41133.83
110099.90166.63
001000.50100.53
101013.3
856.14
011000.0800.04
111000.5705.73
000100.00133.33
100191.5937.13
010113.3877.72
110100.0833.23
001100.0900.03
101100.0700.5
3
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111100.0600.03
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6
ICS9248-95
310D—04/12/05
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-X #0SFdehctaL
6tiB71 )tcanI/tcA(F_KLCICP
5tiB-1 )devreseR(
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/t
cA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-X #2SFdehctaL
6tiB641 )tcanI/tcA(F_KLCUPC
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB931 )tcanI/tcA(F_MAR
DS
2tiB241 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB541 )tcanI/tcA(0KLCUPC
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB711 )evitcanI/evitcA(11MARDS
6tiB811 )evitcanI/evitcA(01MARDS
5tiB021 )evitcanI/evitcA(9MARDS
4tiB121 )evitcanI/evitcA(8MARDS
3tiB821 )evitcanI/evitcA(7MARDS
2tiB921 )evitcanI/evitcA(6MARDS
1tiB131 )evitcanI/evitcA
(5MARDS
0tiB231 )evitcanI/evitcA(4MARDS
7
ICS9248-95
310D—04/12/05
Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #
3SFdehctaL
0tiB-1 )devreseR(
tiB#niPDWPnoitpircseD
7tiB431 )tcanI/tcA(3MARDS
6tiB531 )tcanI/tcA(2MARDS
5tiB731 )tcanI/tcA(1MARDS
4tiB831 )tcanI/tcA(0MARD
S
3tiB621 )tcanI/tcA(zHM84
2tiB521 )tcanI/tcA(zHM42
1tiB841 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER
8
ICS9248-95
310D—04/12/05
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS9248-95. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-95.
3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-95
CLK_STOP# signal. SDRAM (0:11) are controlled as shown.
5. All other clocks continue to run undisturbed.
9
ICS9248-95
310D—04/12/05
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-95. It is used to turn off the PCICLK [4:0] clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-95 internally. The minimum that the PCICLK [4:0] clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK [4:0] clocks. PCICLK [4:0] clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK [4:0] clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
10
ICS9248-95
310D—04/12/05
Shared Pin Operation -
Input/Output Pins
Fig. 1
The I/O pins designated by (input/output) on the ICS9248-
95 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 4-bit internal data latch. At the end of Power -On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
T o program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figs. 1 and 2 show the recommended means of implementing
this function. In Fig. 1 either one of the resistors is loaded
onto the board (selective stuffing) to configure the device’s
internal logic. Figs. 2a and b provide a single resistor loading
option where either solder spot tabs or a physical jumper
header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance clock
signals. The layouts have been optimized to provide as little
impedance transition to the clock signal as possible, as it
passes through the programming resistor pad(s).
11
ICS9248-95
310D—04/12/05
Fig. 2a
Fig. 2b
12
ICS9248-95
310D—04/12/05
Electrical Cha ra cteristics - In put/Supply/Common Output Para meters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD+0.3 V
Input Low Voltage VIL VSS-0.3 0.8 V
Supply Current IDD CL = 0 pF; Select @ 66M 77 180 mA
IDDL 6.030mA
Input frequency FiVDD = 3.3 V; 14.318 MHz
Input Capacitance1CIN Logic Inputs 5 pF
CINX X1 & X2 pins 27 36 45 pS
Transition Time1Ttrans To 1st crossing of target Freq. 1.5 3 mS
Clk Stabilization1TSTAB From VDD = 3.3 V to 1% target Freq. 3 mS
Skew1TCPU-BUS VT = 1.5 V; 1.0 2.2 4.0 nS
1Guarenteed by design, not 100% tested in production.
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
13
ICS9248-95
310D—04/12/05
Electrical Characteristics - 24M, 48M, REF 1
T
A
= 0 - 70C; V
DD
= V
DDL
= 3.3 V +/-5%; C
L
= 20
p
F (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP51
V
O
= V
DD
*(0.5) 20 60 Ω
Output Impedance R
DSN51
V
O
= V
DD
*(0.5) 20 60 Ω
Output High Voltage V
OH5
I
OH
= -14 mA 2.4 2.9 V
Output Low Voltage V
OL5
I
OL
= 6.0 mA 0.25 0.4 V
Output High Current I
OH5
V
OH
= 2.0 V -42 -20 mA
Output Low Current I
OL5
V
OL
= 0.8 V 10 18 mA
Rise Time t
r51
V
OL
= 0.4 V, V
OH
= 2.4 V 4.0 nS
Fall Time t
f51
V
OH
= 2.4 V, V
OL
= 0.4 V 4.0 nS
Duty Cycle d
t51
V
T
= 1.5 V 45.0 50.0 55.0 %
Jitter t
j
1s51
V
T
= 1.5 V 100 250 pS
t
jabs51
V
T
= 1.5 V 250 800 pS
1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - CPU
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 20
p
F (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2A
1
V
O
= V
DD
*(0.5) Output P 10 20 Ω
Output Impedance R
DSN2A
1
V
O
= V
DD
*(0.5) Output N 10 20 Ω
Output High Voltage V
OH2B
I
OH
= -12.0 mA 2 2.3 V
Output Low Voltage V
OL2B
I
OL
= 12 mA 0.2 0.4 V
Output High Current I
OH2B
V
OH
= 1.7 V -41 -19 mA
Output Low Current I
OL2B
V
OL
= 0.7 V 19 37 mA
Rise Time t
r2A
1
V
OL
= 0.4 V, V
OH
= 2.4 V 0.4 2.0 nS
Fall Time t
f2A
1
V
OH
= 2.4 V, V
OL
= 0.4 V 0.4 1.0 2.0 nS
Duty Cycle d
t2A
1
V
T
= 1.25 V 45.0 51.0 55.0 %
Skew
(Window)
t
sk2A
1
V
T
= 1.25 V 120 250 pS
t
c-c
1
V
T
= 1.25 V 250 300 pS
t
j
1s
1
V
T
= 1.25 V 150 pS
Jitter t
jabs
1
V
T
= 1.25 V 208 250 pS
1
Guarenteed by design, not 100% tested in production.
14
ICS9248-95
310D—04/12/05
Electrical Characteristics - PCI
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 30
p
F (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1
1
V
O
= V
DD
*(0.5) 12 23 55 Ω
Output Impedance R
DSN1
1
V
O
= V
DD
*(0.5) 12 20 55 Ω
Output High Voltage V
OH1
I
OH
= -18 mA 2.4 2.9 V
Output Low Voltage V
OL1
I
OL
= 9.4 mA 0.2 0.4 V
Output High Current I
OH1
V
OH
= 2.0 V -58 -22 mA
Output Low Current I
OL1
V
OL
= 0.8 V 25 52 mA
Rise Time t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V 1.5 2.0 nS
Fall Time t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V 1.4 2.0 nS
Duty Cycle d
t1
1
V
T
= 1.5 V 45.0 50.0 55.0 %
Skew Window t
sk1
1
V
T
= 1.5 V 80 500 pS
Jitter t
j
1s1
1
V
T
= 1.5 V 50 150 pS
t
jabs1
1
V
T
= 1.5 V 200 500 pS
1
Guarenteed by design, not 100% tested in production.
Electrical Charact erist ics - SDRAM
T
A
= 0 - 70C; V
DD
=V
DDL
3.3 V +/-5%; C
L
= 30
p
F (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2A
1
V
O
= V
DD
*(0.5) 10 20 Ω
Output Impedance R
DSN2A
1
V
O
= V
DD
*(0.5) 10 20 Ω
Output High Voltage V
OH2A
I
OH
= -28 mA 2.4 2.8 V
Output Low Voltage V
OL2A
I
OL
= 19 mA 0.3 0.4 V
Output High Current I
OH2A
V
OH
= 2.0 V -72 -42 mA
Output Low Current I
OL2A
V
OL
= 0.8 V 33 50 mA
Rise Time t
r2A
1
V
OL
= 0.4 V, V
OH
= 2.4 V 0.5 2.0 nS
Fall Time t
f2A
1
V
OH
= 2.4 V, V
OL
= 0.4 V 0.5 2 nS
Duty Cycle d
t2A
1
V
T
= 1.5 V 45 50 55 %
Skew Window ( output to output ) t
sk2A
1
V
T
= 1.5 V 200 250 pS
Skew ( Bufferin to output ) t
sk2A
1
V
T
= 1.5 V 5nS
1
Guarenteed by design, not 100% tested in production.
15
ICS9248-95
310D—04/12/05
SSOP Package
LOBMYS SNOISNEMIDNOMMOC SNOITAIRAV D N
.NIM.MON.XAM.NIM.MON.XAM
A590.101.011.CA026.526.036.84
1A800.210.610.
2A880.090.290.
B800.010.5310.
C500.- 010.
DsnoitairaVeeS
E292.692.9
92.
eCSB520.0
H004.604.014.
h010.310.610.
L420.230.040.
NsnoitairaVeeS
∝
°0°5°8
X580.390.001.
Ordering Information
ICS9248yF-95LF
Annealed Lead Free (optional)
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP LF
16
ICS9248-95
310D—04/12/05
Revision History
Rev. Issue Date Description Page #
C 4/4/2005 1. Updated CPU,PCI, and SDRAM Electrical Characteristics. 13-14
D 4/12/2005
1. Updated Electrical Characteristics for Input/Output Parameters, CPU and SDRAM.
2. Added Lead Free option.
3. Datasheet Release. 12-15
