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CY7C1061G/CY7C1061GE
16-Mbit (1M words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-81540 Rev. *T Revised July 13, 2018
16-Mbit (1M words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
■High speed
❐tAA = 10 ns/15 ns
■Embedded error-correcting code (ECC) for single-bit error
correction[1, 2]
■Low active and standby currents
❐ICC = 90 mA typical at 100 MHz
❐ISB2 = 20 mA typical
■Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■1.0 V data retention
■Transistor-transistor logic (TTL) compatible inputs and outputs
■Error indication (ERR) pin to indicate 1-bit error detection and
correction
■Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball
VFBGA packages
Functional Description
CY7C1061G and CY7C1061GE are high-performance CMOS
fast static RAM devices with embedded ECC[1]. Both devices are
offered in single and dual chip enable options and in multiple pin
configurations. The CY7C1061GE device includes an ERR pin
that signals a single-bit error-detection and correction event
during a read cycle.
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O0 through I/O15). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE1 HIGH / CE2 LOW for a dual chip enable device),
or control signals are de-asserted (OE, BLE, BHE).
On the CY7C1061GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
on page 16 for a complete description of read and write modes.
The logic block diagrams are on page 2.
The CY7C1061G and CY7C1061GE devices are available in
48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.
For a complete list of related documentation, click here.
Product Portfolio
Product
Features and Options
(see Pin Configurations on
page 4)
Range VCC Range
(V)
Speed
(ns)
10/15
Current Consumption
Operating ICC, (mA) Standby, ISB2 (mA)
f = fmax
Typ[3] Max Typ[3] Max
CY7C1061G18 Single or dual chip enables
Optional ERR pins
Address MSB A19 pin
placement options
compatible with Cypress and
other vendors
Industrial 1.65 V–2.2 V 15 70 80 20 30
CY7C1061G(E)30 2.2 V–3.6 V 10 90 110
CY7C1061G 4.5 V–5.5 V 10 90 110
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate <0.1 FIT/Mb. Refer AN88889 for details.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC =3V (for a V
CC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 001-81540 Rev. *T Page 2 of 25
CY7C1061G/CY7C1061GE
Logic Block Diagram – CY7C1061G
Logic Block Diagram – CY7C1061GE
Document Number: 001-81540 Rev. *T Page 3 of 25
CY7C1061G/CY7C1061GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Loads and Waveforms ....................................... 8
Data Retention Characteristics ....................................... 9
Data Retention Waveform ................................................ 9
AC Switching Characteristics ....................................... 10
Switching Waveforms .................................................... 11
Truth Table ...................................................................... 16
ERR Output – CY7C1061GE .......................................... 16
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 001-81540 Rev. *T Page 4 of 25
CY7C1061G/CY7C1061GE
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout,
Dual Chip Enable without ERR, Address MSB A19 at Ball G2,
CY7C1061G[4] Package/Grade ID: BVJXI
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout,
Dual Chip Enable without ERR, Address MSB A19 at Ball H6,
CY7C1061G[4] Package/Grade ID: BVXI
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout, Single Chip Enable without ERR, Address MSB A19 at Ball G2, CY7C1061G[4]
Package/Grade ID: BV1XI
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
A
19
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
Note
4. NC pins are not connected internally to the die.
Document Number: 001-81540 Rev. *T Page 5 of 25
CY7C1061G/CY7C1061GE
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout,
Single Chip Enable with ERR, Address MSB A19 at Ball G2,
CY7C1061GE[5, 6] Package/Grade ID: BV1XI
Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout,
Dual Chip Enable with ERR, Address MSB A19 at Ball G2,
CY7C1061GE[5, 6] Package/Grade ID: BVJXI
Figure 6. 48-ball VFBGA (6 × 8 × 1.0 mm) Pinout, Dual Chip Enable with ERR, Address MSB A19 at Ball H6,
CY7C1061GE[5, 6] Package/Grade ID: BVXI
Pin Configurations (continued)
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
A
19
326
5
41
D
E
B
A
C
F
G
H
A
16
ERR
V
CC
V
CC
V
SS
Notes
5. NC pins are not connected internally to the die.
6. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81540 Rev. *T Page 6 of 25
CY7C1061G/CY7C1061GE
Figure 7. 48-pin TSOP I (12 × 18.4 × 1 mm) Pinout,
Single Chip Enable with ERR, CY7C1061GE[7, 8]
Package/Grade ID: ZXI
Figure 8. 48-pin TSOP I (12 × 18.4 × 1 mm) Pinout,
Single Chip Enable without ERR, CY7C1061G[7]
Package/Grade ID: ZXI
Figure 9. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout,
Dual Chip Enable without ERR, CY7C1061G[7]
Package/Grade ID: ZSXI
Figure 10. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout,
Dual Chip Enable with ERR, CY7C1061GE[7, 8]
Package/Grade ID: ZSXI
Pin Configurations (continued)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
4
A
3
A
2
A
1
A
0
ERR
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
DD
GND
I/O
4
I/O
5
I/O
6
I/O
7
WE
NC
A
19
A
18
A
17
A
16
A
15
A
5
A
6
A
7
A
8
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
GND
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
9
A
10
A
11
A
12
A
13
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
4
A
3
A
2
A
1
A
0
NC
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
DD
GND
I/O
4
I/O
5
I/O
6
I/O
7
WE
NC
A
19
A
18
A
17
A
16
A
15
A
5
A
6
A
7
A
8
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
GND
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
9
A
10
A
11
A
12
A
13
A
14
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
I/O
11
18
17
20
19
23
28
25
24
22
21
27
26
V
SS
I/O
10
I/O
12
V
CC
I/O
13
I/O
14
V
SS
A
16
A
17
A
11
A
12
A
13
A
14
I/O
0
A
15
I/O
7
I/O
9
V
CC
I/O
8
I/O
15
A
19
A
4
A
3
A
2
A
1
CE
1
V
CC
WE
CE
2
BLE
NC
V
SS
OE
A
8
A
7
A
6
A
5
A
0
NC
A
9
BHE
A
10
10
A
18
46
45
47
50
49
48
51
54
53
52
I/O
2
I/O
1
I/O
3
V
SS
V
CC
V
SS
I/O
6
I/O
5
V
CC
I/O
4
1
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
I/O
11
18
17
20
19
23
28
25
24
22
21
27
26
V
SS
I/O
10
I/O
12
V
CC
I/O
13
I/O
14
V
SS
A
16
A
17
A
11
A
12
A
13
A
14
I/O
0
A
15
I/O
7
I/O
9
V
CC
I/O
8
I/O
15
A
19
A
4
A
3
A
2
A
1
CE
1
V
CC
WE
CE
2
BLE
NC
V
SS
OE
A
8
A
7
A
6
A
5
A
0
ERR
A
9
BHE
A
10
10
A
18
46
45
47
50
49
48
51
54
53
52
I/O
2
I/O
1
I/O
3
V
SS
V
CC
V
SS
I/O
6
I/O
5
V
CC
I/O
4
Notes
7. NC pins are not connected internally to the die.
8. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81540 Rev. *T Page 7 of 25
CY7C1061G/CY7C1061GE
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND ......................–0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z State [9] ................................ –0.5 V to VCC + 0.5 V
DC input voltage[9] .............................. –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Grade Ambient Temperature VCC
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Test Conditions 10 ns / 15 ns Unit
Min Typ [10] Max
VOH Output
HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2.0 – –
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – –
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.4 [11] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4
VIH[9] Input HIGH
voltage
1.65 V to 2.2 V 1.4 – VCC + 0.2 V
2.2 V to 2.7 V 2.0 – VCC + 0.3
2.7 V to 3.6 V 2.0 – VCC + 0.3
4.5 V to 5.5 V 2.0 – VCC + 0.5
VIL[9] Input LOW
voltage
1.65 V to 2.2 V –0.2 – 0.4 V
2.2 V to 2.7 V –0.3 – 0.6
2.7 V to 3.6 V –0.3 – 0.8
4.5 V to 5.5 V –0.5 – 0.8
IIX Input leakage current GND < VIN < VCC –1.0 – +1.0 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1.0 – +1.0 A
ICC Operating supply current VCC = Max, IOUT = 0 mA,
CMOS levels
f = 100 MHz – 90.0 110.0 mA
f = 66.7 MHz – 70.0 80.0
ISB1 Automatic CE power down
current – TTL inputs
Max VCC, CE > VIH [12],
VIN > VIH or VIN < VIL, f = fMAX
– – 40.0 mA
ISB2 Automatic CE power down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V[12],
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
– 20.0 30.0 mA
Notes
9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
10. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
11. This parameter is guaranteed by design and is not tested.
12. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
Document Number: 001-81540 Rev. *T Page 8 of 25
CY7C1061G/CY7C1061GE
Capacitance
Parameter [13] Description Test Conditions 54-pin TSOP II 48-ball VFBGA 48-pin TSOP I Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = VCC(typ) 10 10 10 pF
COUT I/O capacitance 10 10 10 pF
Thermal Resistance
Parameter [13] Description Test Conditions 54-pin TSOP II 48-ball VFBGA 48-pin TSOP I Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
93.63 31.50 57.99 C/W
JC Thermal resistance
(junction to case)
21.58 15.75 13.42 C/W
AC Test Loads and Waveforms
Figure 11. AC Test Loads and Waveforms[14]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
JIG and
Scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
VTH 0.9 1.5 1.5 V
VHIGH 1.8 3 3 V
Notes
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value.
Document Number: 001-81540 Rev. *T Page 9 of 25
CY7C1061G/CY7C1061GE
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter Description Conditions Min Max Unit
VDR VCC for data retention 1.0 – V
ICCDR Data retention current VCC = VDR, CE > VCC – 0.2 V[15],
VIN > VCC – 0.2 V or VIN < 0.2 V
–30.0mA
tCDR[16] Chip deselect to data retention
time
0–ns
tR[16, 17] Operation recovery time VCC > 2.2 V 10.0 – ns
VCC < 2.2 V 15.0 – ns
Data Retention Waveform
Figure 12. Data Retention Waveform [15]
tCDR tR
VDR = 1.0 V
DATA RETENTION MODE
VCC(min) VCC(min)
VCC
CE
Notes
15. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
16. This parameter is guaranteed by design and is not tested
17. Full-device operation requires linear VCC ramp from VDR to VCC (min) > 100 s or stable at VCC (min) > 100 s.
Document Number: 001-81540 Rev. *T Page 10 of 25
CY7C1061G/CY7C1061GE
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [18] Description 10 ns 15 ns Unit
Min Max Min Max
Read Cycle
tPOWER VCC (stable) to the first access [19, 20] 100.0 – 100.0 – µs
tRC Read cycle time 10.0 – 15.0 – ns
tAA Address to data / ERR valid – 10.0 – 15.0 ns
tOHA Data / ERR hold from address change 3.0 – 3.0 – ns
tACE CE LOW to data / ERR valid [21] – 10.0 – 15.0 ns
tDOE OE LOW to data / ERR valid – 5.0 – 8.0 ns
tLZOE OE LOW to low Z [22, 23, 24] 0–1.0–ns
tHZOE OE HIGH to high Z [22, 23, 24] – 5.0 – 8.0 ns
tLZCE CE LOW to low Z [21, 22, 23, 24] 3.0–3.0–ns
tHZCE CE HIGH to high Z [21, 22, 23, 24] – 5.0 – 8.0 ns
tPU CE LOW to power-up [20, 21] 0–0–ns
tPD CE HIGH to power-down [20, 21] – 10.0 – 15.0 ns
tDBE Byte enable to data valid – 5.0 – 8.0 ns
tLZBE Byte enable to low Z [22, 23] 0–1.0–ns
tHZBE Byte disable to high Z [22, 23] – 6.0 – 8.0 ns
Write Cycle [25, 26]
tWC Write cycle time 10.0 – 15.0 – ns
tSCE CE LOW to write end [21] 7.0 – 12.0 – ns
tAW Address setup to write end 7.0 – 12.0 – ns
tHA Address hold from write end 0–0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7.0 – 12.0 – ns
tSD Data setup to write end 5.0 – 8.0 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to low Z [22, 23, 24] 3.0–3.0–ns
tHZWE WE LOW to high Z [22, 23, 24] – 5.0 – 8.0 ns
tBW Byte Enable to write end 7.0 – 12.0 –ns
Notes
18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 11 on page 8, unless specified
otherwise.
19. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed.
20. These parameters are guaranteed by design and are not tested.
21. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
22. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 11 on page 8. Hi-Z, Lo-Z transition is measured 200 mV from steady state
voltage.
23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
24. Tested initially and after any design or process changes that may affect these parameters.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-81540 Rev. *T Page 11 of 25
CY7C1061G/CY7C1061GE
Switching Waveforms
Figure 13. Read Cycle No. 1 of CY7C1061G (Address Transition Controlled) [27, 28]
Figure 14. Read Cycle No. 2 of CY7C1061GE (Address Transition Controlled) [27, 28]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ERR PREVIOUS ERR VALID ERR VALID
tOHA
tAA
Notes
27. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
28. WE is HIGH for read cycle.
Document Number: 001-81540 Rev. *T Page 12 of 25
CY7C1061G/CY7C1061GE
Figure 15. Read Cycle No. 3 (OE Controlled) [29, 30, 31]
Switching Waveforms (continued)
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IMPEDANCE DATAOUT VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
DATA I/O
VCC
SUPPLY
CURRENT
tHZOE
tHZBE
ISB
ICC
Notes
29. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
30. WE is HIGH for read cycle.
31. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-81540 Rev. *T Page 13 of 25
CY7C1061G/CY7C1061GE
Figure 16. Write Cycle No. 1 (CE Controlled) [32, 33, 34]
Figure 17. Write Cycle No. 2 (WE Controlled, OE LOW) [32, 33, 34, 35]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN VALID
Note 36
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE/
BLE
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Note 36
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
34. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
35. The minimum write cycle pulse width should be equal to sum of tHZWE and tSD.
36. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-81540 Rev. *T Page 14 of 25
CY7C1061G/CY7C1061GE
Figure 18. Write Cycle No. 3 (WE Controlled) [37, 38, 39]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/BLE
D A TA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN V A LID
Note40
Notes
37. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
39. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-81540 Rev. *T Page 15 of 25
CY7C1061G/CY7C1061GE
Figure 19. Write Cycle No. 4 (BLE or BHE Controlled) [41, 42, 43]
Switching Waveforms (continued)
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
tWC
tSCE
tAW
tSA
tBW
tHA
tHD
tHZWE tSD
BHE/
BLE
tPWE
tLZWE
Note 44
Notes
41. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
42. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
43. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
44. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-81540 Rev. *T Page 16 of 25
CY7C1061G/CY7C1061GE
Truth Table
CE [45] OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
HX
[46] X[46] X[46] X[46] High-Z High-Z Power down Standby (ISB)
L L H L L Data out Data out Read all bits Active (ICC)
L L H L H Data out High-Z Read lower bits only Active (ICC)
L L H H L High-Z Data out Read upper bits only Active (ICC)
L X L L L Data in Data in Write all bits Active (ICC)
L X L L H Data in High-Z Write lower bits only Active (ICC)
L X L H L High-Z Data in Write upper bits only Active (ICC)
L H H X X High-Z High-Z Selected, outputs disabled Active (ICC)
L X X H H High-Z High-Z Selected, outputs disabled Active (ICC)
ERR Output – CY7C1061GE
Output [47] Mode
0 Read operation, no single-bit error in the stored data.
1 Read operation, single-bit error detected and corrected.
High-Z Device deselected or outputs disabled or Write operation
Notes
45. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
46. The input voltage levels on these pins should be either at VIH or VIL.
47. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81540 Rev. *T Page 17 of 25
CY7C1061G/CY7C1061GE
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram
Package Type
(all Pb-free)
Key Features /
Differentiators
ERR Pin /
Ball
Operating
Range
10 4.5 V–5.5 V CY7C1061G-10BV1XI 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball G2
No Industrial
CY7C1061GE-10BV1XI Yes
CY7C1061G-10BVJXI Dual Chip Enable,
Address MSB A19 at ball G2
No
CY7C1061GE-10BVJXI Yes
CY7C1061G-10BVXI Dual Chip Enable,
Address MSB A19 at ball H6
No
CY7C1061GE-10BVXI Yes
CY7C1061G-10ZSXI 51-85160 54-pin TSOP II Dual Chip Enable No
CY7C1061GE-10ZSXI Yes
CY7C1061G-10ZXI 51-85183 48-pin TSOP I Single Chip Enable No
CY7C1061GE-10ZXI Yes
2.2 V–3.6 V CY7C1061G30-10BV1XI 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball G2
No
CY7C1061GE30-10BV1XI Yes
CY7C1061G30-10BVJXI Dual Chip Enable,
Address MSB A19 at ball G2
No
CY7C1061GE30-10BVJXI Yes
CY7C1061G30-10BVXI Dual Chip Enable,
Address MSB A19 at ball H6
No
CY7C1061GE30-10BVXI Yes
CY7C1061G30-10ZSXI 51-85160 54-pin TSOP II Dual Chip Enable No
CY7C1061GE30-10ZSXI Yes
CY7C1061G30-10ZXI 51-85183 48-pin TSOP I Single Chip Enable No
CY7C1061GE30-10ZXI Yes
15 1.65 V–2.2 V CY7C1061GE18-15BV1XI 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball G2
Yes
CY7C1061G18-15BV1XI No
CY7C1061GE18-15BVJXI Dual Chip Enable,
Address MSB A19 at ball G2
Yes
CY7C1061G18-15BVJXI No
CY7C1061GE18-15BVXI Dual Chip Enable,
Address MSB A19 at ball H6
Yes
CY7C1061G18-15BVXI No
CY7C1061GE18-15ZSXI 51-85160 54-pin TSOP II Dual Chip Enable Yes
CY7C1061G18-15ZSXI No
CY7C1061GE18-15ZXI 51-85183 48-pin TSOP I Single Chip Enable Yes
CY7C1061G18-15ZXI No
Document Number: 001-81540 Rev. *T Page 18 of 25
CY7C1061G/CY7C1061GE
10 4.5 V–5.5 V CY7C1061G-10BV1XIT 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
No Industrial
CY7C1061GE-10BV1XIT Yes
CY7C1061G-10BVJXIT Dual Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
No
CY7C1061GE-10BVJXIT Yes
CY7C1061G-10BVXIT Dual Chip Enable,
Address MSB A19 at ball
H6, Tape and Reel
No
CY7C1061GE-10BVXIT Yes
CY7C1061G-10ZSXIT 51-85160 54-pin TSOP II Dual Chip Enable,
Tape and Reel
No
CY7C1061GE-10ZSXIT Yes
CY7C1061G-10ZXIT 51-85183 48-pin TSOP I Single Chip Enable,
Tape and Reel
No
CY7C1061GE-10ZXIT Yes
2.2 V–3.6 V CY7C1061G30-10BV1XIT 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
No
CY7C1061GE30-10BV1XIT Yes
CY7C1061G30-10BVJXIT Dual Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
No
CY7C1061GE30-10BVJXIT Yes
CY7C1061G30-10BVXIT Dual Chip Enable,
Address MSB A19 at ball
H6, Tape and Reel
No
CY7C1061GE30-10BVXIT Yes
CY7C1061G30-10ZSXIT 51-85160 54-pin TSOP II Dual Chip Enable,
Tape and Reel
No
CY7C1061GE30-10ZSXIT Yes
CY7C1061G30-10ZXIT 51-85183 48-pin TSOP I Single Chip Enable,
Tape and Reel
No
CY7C1061GE30-10ZXIT Yes
15 1.65 V–2.2 V CY7C1061GE18-15BV1XIT 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
Yes
CY7C1061G18-15BV1XIT No
CY7C1061GE18-15BVJXIT Dual Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
Yes
CY7C1061G18-15BVJXIT No
CY7C1061GE18-15BVXIT Dual Chip Enable,
Address MSB A19 at ball
H6, Tape and Reel
Yes
CY7C1061G18-15BVXIT No
CY7C1061GE18-15ZSXIT 51-85160 54-pin TSOP II Dual Chip Enable,
Tape and Reel
Yes
CY7C1061G18-15ZSXIT No
CY7C1061GE18-15ZXIT 51-85183 48-pin TSOP I Single Chip Enable,
Tape and Reel
Yes
CY7C1061G18-15ZXIT No
Ordering Information (continued)
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram
Package Type
(all Pb-free)
Key Features /
Differentiators
ERR Pin /
Ball
Operating
Range
Document Number: 001-81540 Rev. *T Page 19 of 25
CY7C1061G/CY7C1061GE
Ordering Code Definitions
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = BV or ZS or Z
BV = 48-ball VFBGA; ZS = 54-pin TSOP II; Z = 48-pin TSOP I
Speed: XX = 10 ns or 15 ns
Voltage Range: XX = no character or 30 or 18
no character = 4.5 V–5.5 V; 30 = 2.2 V–3.6 V; 18 = 1.65 V–2.2 V
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: Revision Code “G” = 65 nm
Data Width: 1 = × 16-bits
Density: 06 = 16-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 -XX I706 G1 XX XE XX X
Document Number: 001-81540 Rev. *T Page 20 of 25
CY7C1061G/CY7C1061GE
Package Diagrams
Figure 20. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183
4
5
SEE DETAIL A
SEE DETAIL B
STANDARD PIN OUT (TOP VIEW)
REVERSE PIN OUT (TOP VIEW)
3
2X (N/2 TIPS)
B
B
N/2
0.20
D
D1
A
1
2
5
E
A
N/2 +1
2X
2X
B
N
0.10
0.10
SEATING PLANE
C
A1
e9
2X (N/2 TIPS)
0.10 C
A2
DETAIL A
0.08MM M C A-B
SECTION B-B
7c
b1
SEATING PLANE
PARALLEL TO
b6
0°
DETAIL B
BASE METAL
e/2
X = A OR B
X
GAUGE PLAN
E
0.25 BASIC
WITH PLATING
7
L
C
R
(c)
8
c1
1N
N/2 N/2 +1
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS (mm).
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
1.051.000.95
A2
N
R
0
L
e
c
D1
E
D
b
c1
b1
0.50 BASIC
0.60
0°
0.08
0.50
48
0.20
8
0.70
0.22
0.20
20.00 BASIC
18.40 BASIC
12.00 BASIC
0.10
0.17
0.10
0.17
0.21
0.27
0.16
0.23
A1
A
0.05 0.15
1.20
SYMBOL
MIN. MAX.
DIMENSIONS
NOM.
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
0.10mm AND 0.25mm FROM THE LEAD TIP.
SEATING PLANE.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-81540 Rev. *T Page 21 of 25
CY7C1061G/CY7C1061GE
Figure 21. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
Package Diagrams (continued)
51-85160 *E
Document Number: 001-81540 Rev. *T Page 22 of 25
CY7C1061G/CY7C1061GE
Figure 22. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Package Diagrams (continued)
51-85150 *H
Document Number: 001-81540 Rev. *T Page 23 of 25
CY7C1061G/CY7C1061GE
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
Document Number: 001-81540 Rev. *T Page 24 of 25
CY7C1061G/CY7C1061GE
Document History Page
Document Title: CY7C1061G/CY7C1061GE, 16-Mbit (1M words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-81540
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*P 4791835 NILE 06/09/2015 Changed status from Preliminary to Final.
*Q 5436639 NILE 09/14/2016 Updated Maximum Ratings:
Updated Note 9 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values
corresponding to VOH parameter.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding to
Operating Range “4.5 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*R 5580947 NILE 01/10/2017 Updated Logic Block Diagram – CY7C1061G.
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
*S 5775815 AESATMP9 06/16/2017 Updated logo and copyright.
*T 6245720 NILE 07/13/2018 Updated Features:
Added Note 2 and referred the same note in “Embedded error-correcting code
(ECC) for single-bit error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-81540 Rev. *T Revised July 13, 2018 Page 25 of 25
© Cypress Semiconductor Corporation, 2012–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
CY7C1061G/CY7C1061GE
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