Am2130/Am2140 1024x8 Dual-Port Static Random-Access Memories DISTINCTIVE CHARACTERISTICS True dual port operation Access time as fast as 55 ns Master device (Am2130) has on-chip arbitration Expandable data bus width in multiples of 8 bits using one master (Am2130) and required number of slave devices (Am2140) Automatic power-down feature All inputs and outputs are TTL-compatible @ 48-pin DIP or 52-pin PLCC @ Single +5-volt power supply @ Advanced N-MOS technology GENERAL DESCRIPTION The Am2130 and the Am2140 are members of the 1K x8 dual-port static RAM family. The Am2130 is designated as the master and the Am2140 as the slave device. The master provides the necessary control signal to the slave devices to facilitate implementing a wider data bus in a system. The master/slave concept allows expansion with minimal external logic. Both devices have two independent ports called Left and Right port. Each port consists of an 8-bit bidirectional data bus and a 10-bit address input bus and necessary control signals. The Am2130 has an on-board arbiter to resolve contention between the left and right ports. When contention between ports occurs, one port is given priority while the other port receives a busy indication. The Am2130 also contains on-chip facilities for supporting semaphores. Addresses (3FE)y and (3FF)y serve as interrupt generators. If any data is written at the address (3FF)H from the left port, an interrupt signal becomes active for the right port. The interrupt signal is deactivated by reading from the right port at the same address. The address (3FE)y is used in a similar fashion by the right port to activate the interrupt signal for the left port. The Am2130/Am2140 also have two chip enable signals corresponding to the left and right ports. Before any transaction on a port takes place, the corresponding chip enable input must be activated. If a chip enable signal is not active, the circuitry corresponding to its side automatically powers down and enters standby mode. The Am2130/Am2140 are packaged in 48-pin DiPs or 52- pin plastic leaded chip carrier. All inputs and outputs are TTL-compatible and the devices operate from a single + 5- volt power supply. BLOCK DIAGRAM ByWa Ash . COLUMN COLUMN . vo . . yo . e LEFT : : RIGHT . An r) rt Arn aay" a Busy, el I sid e tert |e | RIGHT e e Row | |] MEMORY a] AoW . DECODER annay | * : DRIVER | ORI Aow I Ris fey onver 1 Aon CONTENTION INTERRUPT Losic INT, = Int, . cE (ame130 Gp Wray oe, _}_ ony) Ep ai, R/Wa BDoo5085 Notes: 1. Am2130 (Master): BUSY is open-drain output and requires pull-up resistor. Am2140 (Slave): BUSY is an input.CONNECTION DIAGRAMS DIP ew 48 I Voc RAW, C2 47 [-) CE, BUSY, Cj 3 46 [J A, Int, C4 45 (7) BUSY, dE. CIs 44 (7) INT, Ag, [6 43 [7] OE, A, C7 42 [7] Aw Aw C8 41] Aw A, C49 40 17 Aw A, [10 30 [7] Asa Ay C4 38 [7 Ass 4 (7) 12 37 77) Asay A, (1) 13 36 [7 Aen Ag (14 35 7) Ana Ay (15 34 [7 Asa VO, (] 16 33 [7] Awe 1/0, ([] 17 32 (7) 1/0, VO, C18 St IE) Onn 04, (7) 19 30 [7] O69 VO. (J 20 29 [> V0.9 VOg (21 28 1} 1/059 VO, (7) 22 27 TI) /Onm vO, Cj 23 26 [J 0.8 Vas 24 25 1/Qce D005813 Top View PLCC > p> poe 528 oe f8EbsN S283 ee8 7,6 5 4 3 2 1 52 $1 50 49 48 47 Arf] 8 OQ 46D] Aga Az] 3 46D Aw Ax 10 441 An AcQ 431) Aan As 1] 12 42D Ag Aw G13 410 Asa An 14 40 TT Asn Aa (J 15 39 Arg Ay (916 381) Aan nc 17 371) Aon 1/09, Oh 18 3611) No VO. ts 351 1/07, vod 20 34D \/Os, 21 22 23 24 25 26 27 28 29 30 31 32 33 UYU oor s3 ese RHEE REE S ecodcdossrogdedcoad =at>tsah ssa 3252 CD00g600 Note: Pin 1 is marked for orientation. LOGIC SYMBOL AW, 10 OD oe 10 LD ee Ce, cE, R/W, OE, OE, Op, ~ 1/0, 1Op9 = 1/ Orn INT, BUSY, INT, | LS002232 Voc = +5-V Power Supply Vss = Groundere AMD products are available in formed by a combination of: a. b. ORDERING INFORMATION Standard Products several packages and operating ranges. The order number (Valid Combination) is Device Number Speed Option (if applicable) c. Package Type d. e. Optional Processing Temperature Range B & e. OPTIONAL PROCESSING Blank = Standard processing B = Burn-in d. TEMPERATURE RANGE = Commercial (0 to + 70C) c. PACKAGE TYPE P = 48-Pin Plastic DIP (PD 048) D = 48-Pin Sidebrazed Ceramic DIP (SD 048) J =52-Pin Plastic Leaded Chip Carrier (PL 052) b. SPEED OPTION -85 = 55 ns -70 = 70 ns ~10 = 100 ns -12= 120 ns a. DEVICE NUMBER/DESCRIPTION Am2130/Am2140 1K x8 Dual-Port Static RAM Valid Combinations Valid Combinations AM2130-55 Valid Combinations list configurations planned to be supported in volume AM2130-70 for this device. Consult MSIS sales department to confirm availability of AM2130-10 specific valid combinations, and to obtain additional data on MSIS's AM2130-12 PC, PCB, DC, standard military grade products. AM2140-55 OCB, JC, JCB AM2140-70 AM2140-10 AM2140-12MILITARY ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and Operating ranges. APL {Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number b. Speed Option (if applicable) . Device Class d. Package Type e. Lead Finish AM2130 -10 1B x cS | LEAD FINISH C = Gold d. PACKAGE TYPE X= 48-Pin Sidebrazed Ceramic DIP (SD 048) c. DEVICE CLASS /B=Class B b. SPEED OPTION ~70 = 70 ns -10 = 100 ns ~12 = 120 ns a. DEVICE NUMBER/DESCRIPTION Am2130/Am2140 1Kx8 DualPort Static RAM Valid Combinations Valid Combinations list configurations planned to be supported in volume Valid Combinations for this device. Consult MSIS sales department to confirm availability of AM2130-70 specific valid combinations, and to obtain additional data on MSIS's AM2130-10 standard military grade products. AM2130-12 IBXC - AM2140-70 Group A Tests AM2140-10 Group A Tests consist of subgroups 1, 2, 3, 7, 8, 9, 10, 11. AM2140-12 Fe ba ee ooPIN DESCRIPTION Am2130 Ao.-Agt Left Port Address (Inputs) These 10 inputs constitute the memory address for the left port. Ag is the least significant bit position and Ag is the most significant position. A HIGH level on any of these inputs represents a logic 1 at that position and LOW represents a logic 0. The sequence of events and related timing for the address inputs during read and write operations will be discussed in later sections of this data sheet. If a write operation is performed using (8FF)y, an interrupt signal is activated for the right port (see INTR pin description). if a read operation is performed using (3FE)H, the INTL signal will be deactivated (see INT_ description). Aorn-AgR Right Port Address (Inputs) These 10 inputs constitute the memory address for the right port. Ap is the least significant bit position and Ag is the most significant position. A HIGH level on any of these inputs represents a logic 1 at that position and LOW represents a logic 0. The sequence of events and related timing for the address inputs during read and write operations will be discussed in later sections of this data sheet. if a write operation is performed using ) (SFE), an interrupt signal is activated for the left port (see INT,_ pin description). If a read operation is performed using (FF), the INTR signal will be deactivated (see INTR description). BUSY, Left Port Busy Flag (Output; Open Drain) This open-drain output requires a pull-up resistor for proper operation. A LOW on this output indicates that the on-chip arbitration logic detected a contention between the left and right ports and the right port is given priority. All left port signals must be held stable until a HIGH on this output is indicated. The BUSY signa! generation is a logical function of the left and right port address inputs and the GE; and CER inputs. The transient behavior of the BUSY, output is not assured while the inputs are changing. BUSYR Right Port Busy Flag (Output; Open Drain) This open-drain output requires a pull-up resistor for proper operation. A LOW on this output indicates that the on-chip arbitration logic detected a contention between the left and right ports and the left port is given priority. All right port signals must be held stable until a HIGH on this output is indicated. The BUSY pR signal generation is a logical function of the left and right port address inputs and the CEL and CER inputs. The transient behavior of the BUSYR output is not assured while the inputs are changing. CE. eft Port Chip Enabie (Input) This input must be LOW before any transaction from the left port and remain LOW for the duration of the transaction. When this input goes HIGH, left port logic circuits enter standby power mode and remain in this mode as long as this input remains HIGH. It should be noted that powering down the left port to standby mode does not affect the INTL or INTR outputs. This input going HIGH also initializes the internal arbitration latch. It is recommended that CE, go HIGH after compieting a transaction (see discussion on arbitration). CER Right Port Chip Enable (Input) Operation of this input is identical to CEL except that the CER input contiols the right port. GND (Vss) 1/OoL - 1/O7L Ground Left Port Input/Output Bus (Input/Output; Three State) These eight lines constitute the data bus for the left port. Ifa read operation is performed using the left port, data from the location addressed by the left port address will be available on these lines. Similarly, to perform a write operation using the left port, data to be written into the memory must be presented on these lines. The drivers on the chip to drive these lines are enabled only when the CE, is LOW, OE, is LOW and R/WL is HIGH. 1/OgR-1/07R ~~ Right Port Input/Output Bus (Input/Output; Three State) These eight lines constitute the data bus for the right port. If a read operation is performed using the right port, data from the location addressed by the right port address will be available on these lines. Similarly, to perform a write operation using the right port, data to be written into the memory must be presented on these lines. The drivers on the chip to drive these lines are enabled only when the CEA is LOW, OER is LOW and R/Wp is HIGH. INTL Left Port interrupt Flag (Output; Open Drain) This open-drain output requires a pull-up resistor for proper operation. If the right port performs any write operation using address (3FE)y, then this output goes LOW. It will remain LOW until the left port successfully completes any read operation using the address (3FE)y. It should be noted that powering down the ports has no effect on this output. INTa Right Port Interrupt Flag (Output; Open Drain) This open-drain output requires a pull-up resistor for proper operation. If the left port performs any write operation using address (3FF)y, then this output goes LOW. It will remain LOW until the right port successfully completes any read operation using the address (3FF)y. It should be noted that powering down the ports has no effect on this output. OE_ Output Enable Left 1/0 Port (Input) When this input is HIGH, the left port |/O bus lines are in high impedance state. Hf this input is LOW and CE, is LOW and R/W_ is HIGH, the teft port drivers are enabled and data from the location addressed by the Ao, Agi inputs will be available on the |/O bus lines of the left port. It may be of interest to note that the OE, input has no effect on the BUSY or BUSYa or INT_ or INTR signals. Even though the left port |/O port drivers are disabled when the R/WL input goes LOW (write operation), it is recommended that the OEL signal be kept HIGH during write operations to the left port. OER Output Enable Right 1/0 Port (Input) When this input is HIGH, the right port I/O bus lines are in high impedance state. If this input is LOW and TER is LOW and R/Wrp is HIGH, the right port drivers are enabled and data from the location addressed by the Agr - Agr inputs will be available on the !/O bus lines of the right port. It may be of interest to note that the OER ir input has no effect on the BUSY, or BUSYp or INT, or INTR signals. Even though the left port |/O port drivers are disabled when the R/Wrp input goes LOW (write operation), it is recommended that the GER signal be kept HIGH during write operations to the right port.R/W_ Left Port Read/Write Enable (input) This input is used to specify the left port function to be performed. HIGH indicates a read and LOW indicates a write function, When the CE, is LOW and the OE, is LOW and the R/W is HIGH, data from the location addressed by the Aoi ~ Agi will be available on the I/Og. ~ 1/O7,, lines. As mentioned earlier, reading from the left port at the location (BFE)H disables the INTL output. When the CE, is LOW and the R/W. goes LOW, data present on the I/O, -|/O7, lines will be written into the location addressed by the Ao_- Agi inputs. it should be noted that the write operation is not affected by the OE, input. However, it is recommended that the OEL input be held HIGH during a write operation. As mentioned earlier, performing a write operation from the left port at the address (3FF)H causes the INTR output to go LOW. It should be noted that even though R/W_ is LOW, writing is internally inhibited if the right port is given priority by the arbiter. Discussion on arbitration can be found in a later section. R/Wp_ Right Port Read/Write Enable (Input) oe Am2140 The Am2140 is functionally very similar to the Am2130 The Am2140 differs from the Am2130 in two signals only BUSY, and BUSYp. In the case of the Am2140 they are used as inputs and play a significant role in expanding the word width. BUSY, Left Port Busy Flag (Input) If this input is LOW, a write enable signal to the left side of the memory array is internally disabled. In expanded systems where an Am2130 is used as the master, this input '$ connected to the BUSY, output of the Am2130. EB 46077984 o000087 605 oe This input is used to specify the right port function to be performed. HIGH indicates a read and LOW indicates a write function. When the CER is LOW and the OER is LOW and the R/Wr is HIGH, data from the location addressed by the Agog ~ Agr will be available on the !/Oor ~ |/O7R Hines. As mentioned earlier, reading from the fight port at the location (SFF}Y disables the INTg output. When the CER is LOW and the R/Wr goes LOW, data Present on the !/Ogp - I/O7p lines will be written into the location addressed by the Aor ~ Agr inputs. It should be noted that the write operation is not affected by the OER input. However, it is recommended that the OER input be held HIGH during a write operation. As mentioned earlier, performing a write operation from the tett port at the address (3FE)} causes the INT, output to go LOW. It should be noted that even though R/Wp is LOW, writing is internally inhibited if the left port is given priority by the arbiter. Discussion on arbitration can be found in a later section. Voc +5-Voit Power Supply BUSYR Right Port Busy Flag (Output; Open Drain) If this input is LOW, a write enable signal to the right side of the memory array is internally disabled. In expanded systems where an Am2130 is used as the master, this input is connected to the BUSYpR output of the Am2130. Am2130/Am2140 4-95FUNCTIONAL DESCRIPTION As shown in the block diagram, the Am2130/Am2140 is a true 1K x8 dual-port RAM. It consists of a memory array with two sets of address decoders and associated logic. This arrange- ment allows the accessing of every word in the memory array from two independent sources. We call these sources left side and right side for convenience. Data accessed by the left-side address inputs appears on the left-side data lines of the array and is connected to the left-side VO pins through the associated three-state buffers. The enable control signal for these buffers is generated using the R/WL, GE, and GEL inputs. If the 1/O buffers are disabled on the chip, the |/O pins can be used as inputs. Data to be written from the left port is presented on these inputs. Writing into the memory array from the left side is controlled by the left write enable signal generated on the chip using the A/W,, and CE; inputs. An identical arrangement exists for the right side also. In addition, there is on-chip arbitration logic to give priority to one port over the other in case of a contention, and interrupt flag logic. Contention Arbitration Two independent access facilities are provided in a dual-port memory to eliminate physical interference between signals. However, there are two significant possibilities of logical interference which are not tolerable: when one port is reading from a location while the other port is writing into the same location at the same time. In this case, data received by the reading port may not be predictable. Similarly, consider the situation when both ports write information into the same iocation simultaneously. The resultant data that finally ends up in the memory location may not be valid. These two situations are commonly called contention. The Am2130 has on-chip logic to detect contention and give priority to one port over the other. Ina true dual-port RAM, simultaneous reading from both ports at the same address does nat corrupt the data. Hence, it can be construed that no contention occurs. However, for the sake of simplicity and compatibility with the industry standard practices, the Am21 30 arbitration is based purely on ad- dresses. Hence, in the case of a simultaneous read from both ports at the same address, the arbitration logic will sense contention and give priority to one ot the ports. The other port will receive a busy indication. Figure 1 is a conceptual logic diagram of contention arbitration logic. It consists of two equality comparators. The left compar- ator compares the left port address inputs to the delayed version of the right port address. Similarly, the fight compara- tor compares the right-port address to the delayed version of the left port address. The output of the comparators is connected to a latch formed by two cross-coupled NAND gates as shown in Figure 1. The chip enable signals, CEL and CEpR, are also inputs to this latch as shown. The BUSY, and BUSY R outputs are generated by gating the latch output with the proper chip enable signal as shown. Also note that the latch outputs are used internally for left and right write inhibit signals. For example, if the right side write inhibit signal in Figure 1 is LOW, writing into the memory does not occur even if the R/Wr input of the Am2130 is LOW. The operation of the arbitration circuit can now be explained. Assume that the left port address had been stable and CE, is LOW. Both Q and Q' outputs of the latch will be HIGH because the output of both comparators is LOW (addresses are different). So the BUSY output on both sides is HIGH. Now assume that the right address changes and becomes equal to the left address. The right address comparator output goes HIGH and the Q' output of the latch goes LOW. Eventually the output of the left comparator also goes HIGH, but because of the crass coupling of the Q' into the gate generating the Q output, Q output remains HIGH. As soon as the CER input goes LOW, BUSY_ becomes LOW. Thus, the arbitrator gave priority to the left port by indicating a busy signal to the right port. Thus in this example, the left port is the winner and the right port is the loser in the contention for the memory. Sooner or ater the left port will finish its transaction at the contended location and change the address or its chip enable will go HIGH. Thus when the contention is over the Q output of the latch will become HIGH and BUSYR will go HIGH. A similar reasoning can be used to understand the operation of the left side. It should be clear then, in cases of contention, the arbiter will decide one port as the winner and the losing port must wait for the winner to complete the use af the memory. The winning port must indicate to the arbiter that it has completed its operation either by changing the address or making its chip enable input HIGH. Without such an indication, the arbiter will not remove the busy indication to the losing port. ovo: | o 1 Aon Aon x, % % 10 a a Tio LEFT RIGHT COMPARATOR COMPARATOR: ce, [po ; 4 Ea BUSY, BUSY py a a! LEFT WRITE FIGHT WRITE INHIBIT NHIBIT BD007422 Figure 1. Conceptual Arbitration Logic 4-96 Am2130/Am2140 ms 6077984 cooodss 745 =Read/Write Operations Pertorming read/write operations when there is no contention is relatively straightforward. The sequence of events for a read is listed below. The timing relationships between various signals can be found in later sections of this data sheet. . Establish HIGH on the R/W and LOW on the CE input of the desired port. = pS Establish the desired address on the desired port address tines. Make the GE input of the desired port LOW. & & The I/O lines of the selected port will contain the data after the access time has elapsed. mn Make the output enable and chip enable inputs HIGH to complete the read operation. Performing write operations when there is no contention is equally straightforward. The sequence of events for a write is listed below. The timing relationships between various signals can be found in later sections of this data sheet. 1. Establish LOW on the CE input of the desired port. 2. Establish the desired address on the desired port address lines. 3. Establisn the desired data on the I/O lines of the port. 4, Make the R/W input of the port LOW and bring it HIGH after the specified amount of time. 5, Make the CE input HIGH to complete the operation. When a read or write operation is initiated by a port and contention from the other port occurs, the implications are very simple. The losing port will see its BUSY line go LOW. The port must wait untit a HIGH is indicated on the BUSY line. Thus in this case of contention, the operation did not really start when the port initiated it. Instead, the operation actually started when the BUSY line went HIGH. See the timing diagram for details. interrupts Each port has an associated output called interrupt. The interrupt outputs are activated and deactivated by the on-chip logic when read and write operations occur with a particular address location. For dxample, if a write operation is per- formed by the left port with address (3FF)H, an on-chip iatch is set. This latch drives the INTq output LOW. The latch is cleared only when a read operation from the right port using the address (3FF)y takes place. Similarly, if a write operation from the right port using the address (3FE)y occurs, a latch is set to drive the INT, output LOW. The INT, will go HIGH (latch is cleared) only after a read operation from the jeft port using the address (3FE)y occurs. As mentioned before, powering down a port to standby mode does not affect these outputs. Depth Expansion Using Multiple Am2130s The Am2130 has an intrinsic storage capacity of 1K bytes. However, it is simple to expand the storage capacity by using multiple devices. Figure 2 is a conceptual diagram of a 2K byte dual port memory system using two Am2130 devices. The principle behind such expansion is obvious: all that needs to be done is to decode the most significant system address to generate the individual CE inputs for the Am2130s. For 8077984 0000089 b41 = example in Figure 2, Aig is the most significant address bit. When this signal is LOW and CE input is LOW, the chip enable input of the upper Am2130 goes LOW. Thus, the first 1K locations are selected for transactions. On the other hand, if A409 is HIGH and CE is LOW, the chip enable input of the lower Am2130 goes LOW selecting the second 1K locations. As depicted in the figure, the address inputs of both Am2130 devices are bussed together. Similarly, the !/O signals are also bussed to create the overall data bus. Also note that the other control signals are connected between the two devices. In this example, we have not used the interrupt outputs. However, it should be noted that depth expansion using multiple devices does not change the operation of the interrupt outputs. The interrupt output of each device behaves as described before. Hence, the user must decide which interrupt output from which device will be used in his system. Width Expansion The intrinsic width of the data word of the Am2130 is eight bits. However, it is possible to realize wider data words (multiples of 8) by using multiple devices. The instinctive solution of taking the required number of the devices and assigning the data bits to individual devices is potentially unreliable. As we know, the Am2130 has arbitration logic on the chip, and hence is calted the master. When several of these masters are present, device-to-device variations and other factors may cause one device to give priority to one port, while another device gives priority to the other port. In essence both ports are busy! This is an undesirable situation and should not be allowed in operation. The most elegant way to avoid the situation is to allow only one device to arbitrate the contention. it is recommended that when expanding the width of the data words, the Am2130 be used as the master and a number of Am2140s be used as slave devices. The Am2140 does not have the arbitration capability, instead it accepts the BUSY outputs generated by the Am2130 as inputs. Figure 3 is a conceptual diagram of a 16-bit system using one Am2130 and one Am2140. As can be seen, using master/ slave devices avoids external logic for expansion. For the sake of completeness of this discussion, it may be noted that it is indeed possible to expand the width using Am2130s only. However, external logic must be provided to prevent every device of the system from arbitrating. We want only one device to be the arbitrator. As explained in Figure 1, arbitration can be defeated by suitable contro! of the CE input of the Am2130. Figure 4 shows a conceptual diagram of a 16-bit system using two Am2130s. Device 1 in this figure behaves as the master. The external logic shown in the figure ensures that the CE input of Device 2 is HIGH if the corresponding BUSY output of Device 1 is LOW. Thus the arbitration logic of Device 2 is prevented from taking part in resolving contention. Simultaneous Width and Depth Expansion By combining the depth and width expansion schemes dis- cussed, it is possible to build systems with greater depth (multiples of 1K) and wider words (multiples of 8). Figure 5 shows a conceptual diagram of a 2Kx16 system. The operation of this scheme is understood by suitably combining the explanation of Figure 2 and Figure 3 and hence is not repeated here. Am2130/Am2140 4-97Aaa, Apa-ABR POG H07, WorO7R WE, Wea Aro A cE, a ay SER BD007380 Figure 2. Conceptual Depth Expansion Aa aL Aon-AaR POgplo7, WOor- 7A A WEn ee, Ey e, Gp BUSY, BUSY, Wg y5, LEFT 0 RIGHT LO Won 158 RW RW R ar L CER BUSY, BUSY, BDG07400 Figure 3. Width Expansion with Master/Slave M8 46077984 oO00050 373 4-98 Am2130/Am2140A Aor Aa LEFT ADDRESS RIGHT Aor-Agr Wy 7, vo RIGHT Wor-O7R we, CER Am2130 rote Ep We, WEa BUSY, BUSY g LEFT ADDRESS RIGHT ADORESS Wg, 10; 5 LEFT YO RIGHT vO Wen 15R cE Am2130 OE, SER WE, WE, +5V +5V BD007410 Figure 4. Width Expansion with Master Aon Ave AoA st yn ise Rotor, Mrs We AtoL , a, may, Wi, BDOO7390 Figure 5. Conceptual Diagram of a 2K x 16 System Using Master/Slave Be 8077984 0000091 23T Am2130/Am2140 4-99TABLE 1. NON-CONTENTION READ/WRITE CONTROL Left Port Inputs Right Port Inputs Left Flags | Right Flags R/W. CEL GOEL! AoL-Ag. | R/WR CER GER] Aor-Agr |BUSY|| INT, | BUSY, INT, Function x H x x x x xX x H x H X {Left port in power- down mode x x x x x H x x H x H xX Right port in power- down mode L L xX x x Xx x x H x x X {Data on left port written to memory location Ao. - Ao. H L L xX x x Xx x H x x X |Data in memory location Ag. ~ Agi output on left port xX x x x L L x x x x H X |Data on right port writtan to memory location Aor ~ Aor x x xX x H L L x x x H X |Data in memory location Agr - Asn output on right port L L x 3FF x x x Xx H x H L Left port flags right port to read memory location 3FF x x . x x L L x 3FE H Ll H x Right port fiags left Port to read memory location 3FE TABLE 2. BUSY ARBITRATION OF ADDRESS CONTENTION Flags Left Port Right Port (Note 1) A/W CEL OEL | Ao.-Ao.|R/Wa} CER OER |Aon-Aon| BUSYL | BUSYR Function x L (LIV) x Match x L x Match L H Right-Port operation only x L x Match X L x Match L H [IS Permitted. (Note 3) (uly) x L x Match x L (LIV) x Match H L Left-port operation only x L x Match Xx L x Match H L___{/8 Permitted. (Note 4) (LIV) TABLE 3. INTERRUPT FLAG Left Port Right Port R/WL CEL OE, Ao._-AgoL INTL R/WrR CER OER Aor-Asr INTR Function L L x 3FF x x x x Xy L Set INTR x x X x; x H L L 3FF H Reset INTR x x x xy L L L x 3FE x Set INT. H L L 3FE H x x x Xt x Reset INTL Key: H=HIGH L= LOW LIV = Last Input Valid; meets taps spec (Note 2) X= Don't Care X4 = No Match, or Same port deselected, or Opposite port has priority Nates: 1. INT Fiags = X 2. if LIV violates taps spec then one of the two ports receives priority, and the remaining port's BUSY Flag goes LOW. However, there is an extramely rare metastabla event which can occur when the arbitration circuitry cannot determine which part was "first" at the matching address. On this rare occurrence, both ports may momentarily receive BUSY = LOW signals until the metastabie state is resolved (usually within a few nanoseconds). Thereafter, one port's BUSY remains LOW while the other campietes its operation and resumes normal operation. 3. A Left-Port Read operation is also permitted if the Right-Port is also reading. 4. A Right-Port Read operation is also permitted if the Left-Port is also reading. We 6077984 OOOO0S2 17b 4-100 Am2130/Am2140ABSOLUTE MAXIMUM RATINGS (Note 15) Storage Temperature .......0. ee -65 to + 150C Ambient Temperature with Power Applied ..........0.........0004 -55 to + 125C Supply Voltage with Respect to Ground -0.5 to +7.0 V All Signal Volitages........... -3.5 to +7.0 V Power Dissipation ........... cece sce c crete eee en nen ees 1.2W Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES (Note 8) Commercial (C) Devices Temperature (TA)... cccccccce cee ete ree en ee nen ee 0 to + 70C Supply Voltage (VCC) .....---.cceeeece ee eeee +45 to +6.5 V Military (M) Devices Temperature (TA) ........cccceee cee ee renee ee -55 to + 125C Supply Voltage (Voc) .........-..ceeeeeeees +45 to +55 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating range unless otherwise specified (for APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Ain2130/Am2140 Parameter Parameter Symbol Description Test Conditions Min. Max. Units Input Load Current = = tu (All input Pins) Voc = Max., Vin = GND to Vcc 10 pA tto Output Leakage Current Geant Ge we 10 HA Revi 170 \ Power Supply Currant Voc = Max. CE = Viv Devices mA ce (Both Ports Active) Outputs Open M Devicas 185 Bevi 30 spi Standby Current Voc = Min. to Max., Devices mA {Both Ports Standby) mV M CEL and CER = Vin Devices 40 c Voc = Max., Devices 410 Standby Current TE =v d GE =v, vl spa One Port Standb tek an Am IW oF M mA ( ) CEL = Vin and CER = Vit Devices 125 Vit input LOW Voltage -05 08 Vv Vin input HIGH Voltage 22 6.0 v Output LOW Voltage - Vout (Op - 1/07) log = 3.2 MA 0.4 v Open-Drain Output LOW Voitage lo. = 4 mA Vou2 (BUSY (Note 14), INT) (Note 7) 05. Vv Vou Output HIGH Voltage Rte ne mA 24 Vv CAPACITANCE (Note 9) Parameter Parameter Symbol Description Test Conditions Min. Max. Units Cour Output Capacitance 10 F Cin Input Capacitance 10 P Notes: See notes following Switching Waveforms. ms 8077984 0000093 00 Am2130/Am2140 4-101SWITCHING CHARACTERISTICS over o Group A, Subgroups 7, 8 9, 10, 11 are tested perating range unless otherwise specified (for APL Products, unless otherwise noted) Am2130/Am2140 -70 -10 ~12 Parameter Parameter Test T No. Symbol Description Conditions | Min. | Max. Min. | Max. | Min. | Max.) Min. | Max. | Units READ CYCLE (Note 10) 1 tac Read Cycle Time 65 70 100 120 ns 2 tAA Address Access Time 55 70 100 120 ns 3 tACE Chip Enable Access Time 55 70 100 120 ns 4 tAOE Output Enable Access Time 30 35 40 60 ns toH Output Hold from Address Change 5 5 5 5 ns 6 tLz Output Low Z Time {Notes 5 & 9) 5 5 5 ns | 7 tHz Output High Z Time (Notes 5 & 9) Q 25 Q 30 0 40 0 40 ns 8 tpu Chip Enabie to Power Up Time (Note 9) 0 0 0 0 ns 9 tpp Chip Disable to Power Down Time (Note 9} 35 35 50 60 ns WRITE CYCLE (Note 10) Pood two Write Cycle Time 55 70 100 120 ns PT te Chip Enable to End of Write 55 65 90 100 ns [2 thw Address Valid to End of Write 50 65 90 100 ns 3 tas Address Setup Time 0 0 9 0 ns 14 twp Write Pulse Width 45 50 60 70 ns 15 twrR Write Recovery Time 0 0 0 0 ns 16 tow Data Valid to End of Write 30 36 40 40 ns 17 tDH Data Hold Time 0 0 0 0 ns 18 twz Write Enabled to Output in High Z (Notes 5 & 9) 0 25 0 30 0 40 0 50 ns ig tow Output Active from End of Write {Notes 5 & 9) Q 0 0 0 ns BUSY FLAG TIMING (Notes 7 & 14) 20 tac Read Cycle Time 55 70 100 120 ns 21 two Write Cycie Time 85 70 100 120 ns 22 tgsw BUSY to Write (Note 13) -5 -5 -5 -5 ns 23 tWH Write Hold After BUSY (Note 13) 20 20 20 20 ns 24 TBAA BUSY Access Time to Address {Note 9) 46 45 50 60 ns 25 tBDA BUSY Disable Time to Address (Note 9) 40 45 50 60 ns 26 tac Chi, Soe Time to Chip Enable or (Note 9) 40 45 50 60 ns 27 | teoc BUSY Disable Time to Chip E nable or Chip (Note 9} 40 45 50 60 ns 28 taps Arbitration Priority Setup Time 10 10 10 10 ns INTERRUPT TIMING (Note 7) 29 twins WE to Interrupt Set Time 30 30 35 45 ns 30 teINs CE to Interrupt Set Time 50 55 60 70 ns hl tiNS Address to Interrupt Set Time 50 55 60 70 ns 32 toINR Output Enable to Interrupt Reset Time 30 30 36 45 ns 33 tINR Address to Interrupt Reset Time 50 55 60 70 ns 34 tEINR Chip Enable to interrupt Reset Time 50 55 60 70 ns Notes: See notes following Switching Waveforms. Me 8077984 0000094 T44 Ml 4.102 Am2130/Am2140SWITCHING TEST CIRCUITS +5V +5V 12800 1180.0 Pour BUSY @ NT TTB CAP | CAP TC002201 TC002222 Test Loads A and B Test Loads C and D TEST OUTPUT LOADS Test Load CAP A & pF (Note 1) B 100 pF Cc 50 pF D 5 pF (Note 1) Notes: 1. Includes Scope and Jig Capacitance. SWITCHING TEST WAVEFORM AC Test Conditions Input Lavels GND to 3.0 V Input Rise and Fall Times 5 ns Input Timing Reference Leveis 1S Output Reference Levels 15 V Test Output Load See Test Output Loads Table SWITCHING WAVEFORMS KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE WILL BE STEADY STEADY May CHANGE WILL BE FROMH TOL CHANGING FROM K TOL MAY CHANGE ILL BE FROML TOH FROML TOK DON'T CARE, CRANGING, ANY CHANGE STATE PERMITTED UNKNOWN CENTER DOES NOT LINE IS HIGH APPLY IMPEDANCE "OFF" STATE KS000010 6077984 0000095 485 = Am2130/Am2140 4-103SWITCHING WAVEFORMS (Cont'd.) READ CYCLE (Either Side) <1) ay x 7 | ce | rX YX X oava vat DATA OUT PREVIOUS DATA VALID eT Address Access (Notes 1 & 2) DATA OUT VALID DATA ee CURRENT sp CE and O-Controlled Access (Notes 1 & 3) we 8077984 OOOO05b 611 4-104 Am2130/Am2140 X WF009391 WFO009401SWITCHING WAVEFORMS (Cont'd.) WRITE CYCLE (Either Side Note 4) @ L = e o RW x \ { |. @ @~ Lt YAAN -D HIGH IMPEDANCE CATA Out E-Controlled Data Out WFO09411 on @ a ww yi -@--+ @ OATA IN lan yanto bo. (78) = fener DATA OUT DATA UNCEFINED ) RIGH UAPEOANCE WFO009421 WE-Controlled Data Out (OE = Vit) mm 8077984 ooooon? 755 Am2130/Am2140 4-105SWITCHING WAVEFORMS (Cont'd.) BUSY FLAG TIMING (1 of 2) (Note 12) (Chip Enable Arbitration) AODRR YOOXKRX ADDRESSES MATCH x ADDRESSES DONT CARE x ADDR, X AODRESSES MATCH xX ADDRESSES DONT CARE xX e, x # 777/77 Sn \ 7 KR -__ @ _ BUSY, _ @ WF009433 ER Valid Last ADDR, XXX ADDRESSES MATCH x ADORESSES DONT CARE xX ADDR, K AODRESSES MATCH x AGORESSES DONT CARE X CER x #/ / / / / / -e- ze, \ ai __-@ -_~. @ __- a, [_ _ WF009434 E_ Valid Last ma 8077964 g000096 494 4-106 Am2130/Am2140SWITCHING WAVEFORMS (Cont'd) BUSY FLAG TIMING (2 of 2) (Address Arbitration) rr cr |. Oo } ADDR, ADORESSES MATCH YORK ARDRESSES 00 NOT MATCH x @ DA ADDR, x ADORESSES MATCH x ADDRESSES 00 NOT MATCH X | 33) LL 3 I as, ee { | j WF009443 ADDR Valid Last SQ /- KE /~ | one | 4 ADDR ADORESSES MATCH XXX ADDRESSES 00 NOT MATCH xX. a @a AOR, x ADDRESSES MATCH x AODRESSES 00 NOT MATCH x BUSY, WF009444 ADDR, Valid Last WF024680 For Am2140 Only 48077964 0000099 5Se0 Am2130/Am2140 4-107SWITCHING WAVEFORMS (Cont'd.) INTERRUPT TIMING (1 of 2) (Set INT Flag Note 11) ADDR, x WRITE 3FF XXX ADDRESSES DON'T CARE X + ~((3) >| @ RM, 1 SNE LITTTTTTATLELELLELELLELALTL 2 WF009486 Sh Left Side Flags Right Side (54) Se ADDR x WRITE 3FE XX ADDRESSES DON'T CARE xX | (3) +--+ ya -+| k- R/Wa N 5) hs INT, TN {7+ ey rN eS CE, N LLLLLLLLLLLLLLLLLLLLLLL LLL. WFQ09487 ht N Right Side Flags Left Side M8 4077984 0000100 O72 4-108 Am2130/Am2140SWITCHING WAVEFORMS (Cont'd.) INTERRUPT TIMING (2 of 2) (Clear INT Flag) Bs c = (TTL Wi LL > COMMA, LTT INTC, : f Left Side Clears INT|, Ho nity LLLLLLLLLLLLLLLLL | i AAAS LLL me AAA LLLT11 Na . t Right Side Clears INTR mm 80779484 0000101 TOS Am2130/Am2140 4-109Notes* 1. R/W is HIGH for Read Cycles. 2. Device is continuously enabled, CE = Vi,, OE = Vi. 3. Addresses valid prior to or coincident with CE transition LOW. 4.\f CE and R/W go HIGH simultaneously, the outputs remain in the high-impedance state. 5. Transition is measured at 1.5 Vv on the input to VOH - 500 mV and VOL + 500 mV on the outputs using the Load shown in Load A. 6. CE, = CER = Vit. 7 . The BUSY and INT outputs are open drain. A pull-up resistor is required for systern operation. For measurement purposes, Load C is used for HIGH-to-LOW transitions; output reference level is 1.5 V. Load D is used for LOW-to-HIGH transitions; output reference level is +500 mV from the output LOW voltage level. @ For test and correlation purposes, ambient temperature is defined as the instant-on case temperature. . This parameter is guaranteed by design but is not 100% tested. 10. Except where indicated, I/O pins use Load B. wo 11. For a given port to Set or Clear an interrupt Flag, 1) that port must have priority if addresses match and both CE, = CER = LOW; or 2) Addresses do not match. 12. If the last input valid transition, which would ordinarily cause a match, occurs at the same time that the opposite port address or CE changes to a no-match condition, then BUSY will remain HIGH ({.e., if there is never a match, then BUSY remains HIGH). 13. For Slave Am2140 only. 14. For Master Am2130 only. 15. Absolute Maximum Ratings are intended for user guidelines and are not tested. * Notes listed correspond to reference made in the following sections: - Operating Ranges - DC Characteristics table - Switching Characteristics table - Switching Waveforms Mm 8077984 O0O0010e 5945 4-110 Am2130/Am2140