TPS2110A/TPS2111A
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4RL
RILIM
CL
C2
0.1 Fm
C1
0.1 Fm
EN1
IN2:2.8Vto5.5V
IN1:2.8Vto5.5V
TPS2110A
TPS2111A
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SBVS043A –MARCH 2004–REVISED MARCH 2010
AUTOSWITCHING POWER MUX
Check for Samples: TPS2110A,TPS2111A
1FEATURES APPLICATIONS
• PCs
2• Two-Input, One-Output Power Multiplexer with
Low rDS(on) Switches: • PDAs
• Digital Cameras
– 84 mΩTyp (TPS2111A) • Modems
– 120 mΩTyp (TPS2110A) • Cell Phones
• Reverse and Cross-Conduction Blocking • Digital Radios
• Wide Operating Voltage Range: 2.8 V to 5.5 V • MP3 Players
• Low Standby Current: 0.5 mA Typ
• Low Operating Current: 55 mA Typ DESCRIPTION
• Adjustable Current Limit The TPS211xA family of power multiplexers enables
• Controlled Output Voltage Transition Time: seamless transition between two power supplies,
Limits Inrush Current such as a battery and a wall adapter, each operating
Minimizes Output Voltage Hold-Up at 2.8 V to 5.5 V and delivering up to 1 A. The
Capacitance TPS211xA family includes extensive protection
circuitry, including user-programmable current
• CMOS- and TTL-Compatible Control Inputs limiting, thermal protection, inrush current control,
• Manual and Auto-Switching Operating Modes seamless supply transition, cross-conduction
• Thermal Shutdown blocking, and reverse-conduction blocking. These
features greatly simplify designing power multiplexer
• Available in a TSSOP-8 Package applications.
space space
space
space
TYPICAL APPLICATION
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS
FEATURE TPS2110A TPS2111A TPS2112A TPS2113A TPS2114A TPS2115A
0.31 A to 0.63 A to 0.31 A to 0.63 A to 0.31 A to 0.63 A to
Current Limit Adjustment Range 0.75 A 1.25 A 0.75 A 1.25 A 0.75 A 1.25 A
Manual Yes Yes No No Yes Yes
Switching Modes Automatic Yes Yes Yes Yes Yes Yes
Switch Status Output No No Yes Yes Yes Yes
ORDERING INFORMATION(1)
TAPACKAGE ORDERING NUMBER PACKAGE MARKING
TPS2110APW 2110A
−40°C to 85°C TSSOP-8 (PW) TPS2111APW 2111A
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over recommended operating junction temperature range, unless otherwise noted. TPS2110A, TPS2111A UNIT
Input voltage range at pins IN1, IN2, D0, D1, VSNS, ILIM(2) −0.3 to 6 V
Output voltage range, VO(OUT)(2) −0.3 to 6 V
TPS2110A 0.9
Continuous output current, IOA
TPS2111A 1.5
Continuous total power dissipation See Dissipation Ratings table
Operating virtual junction temperature range, TJInternally Limited
Human body model (HBM) 2 kV
ESD Charged device model (CDM) 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
DISSIPATION RATINGS
DERATING FACTOR TA≤25°C POWER TA= 70°C POWER TA= 85°C POWER
PACKAGE ABOVE TA= 25°C RATING RATING RATING
TSSOP-8 (PW) 3.9 mW/°C 387 mW 213 mW 155 mW
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SBVS043A –MARCH 2004–REVISED MARCH 2010
RECOMMENDED OPERATING CONDITIONS TPS2110A, TPS2111A
MIN NOM MAX UNIT
VI(IN2) ≥2.8 V 1.5 5.5
Input voltage at IN1, VI(IN1) V
VI(IN2) < 2.8 V 2.8 5.5
VI(IN1) ≥2.8 V 1.5 5.5
Input voltage at IN2, VI(IN2) V
VI(IN1) < 2.8 V 2.8 5.5
Input voltage: VI(DO), VI(D1), VI(VSNS) 0 5.5 V
TPS2110A 0.31 0.75
Current limit adjustment range, IO(OUT) A
TPS2111A 0.63 1.25
Operating virtual junction temperature, TJ–40 125 °C
ELECTRICAL CHARACTERISTICS: Power Switch
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2110A TPS2111A
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
VI(IN1) = VI(IN2) = 5.0 V 120 140 84 110
TJ= 25°C, VI(IN1) = VI(IN2) = 3.3 V 120 140 84 110 mΩ
IL= 500 mA
Drain-source VI(IN1) = VI(IN2) = 2.8 V 120 140 84 110
on-state rDS(on)(1)
resistance VI(IN1) = VI(IN2) = 5.0 V 220 150
(INx−OUT) TJ= 125°C, VI(IN1) = VI(IN2) = 3.3 V 220 150 mΩ
IL= 500 mA VI(IN1) = VI(IN2) = 2.8 V 220 150
(1) The TPS211xA can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this
specific case, the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
ELECTRICAL CHARACTERISTICS
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise
noted. TPS2110A, TPS2111A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC INPUTS (D0 AND D1)
High-level input voltage VIH 2 V
Low-level input voltage VIL 0.7 V
D0 or D1 = High, sink current 1
Input current at D0 or D1 mA
D0 or D1 = Low, source current 0.5 1.4 5
SUPPLY AND LEAKAGE CURRENTS
D1 = High, D0 = Low (IN1 active), 55 90
VI(IN2) = 3.3 V
D1 = High, D0 = Low (IN1 active), 1 12
Supply current from IN1 (operating) mA
VI(IN1) = 3.3 V
D0 = D1 = Low (IN2 active), VI(IN2) = 3.3 V 75
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V 1
D1 = High, D0 = Low (IN1 active), 1
VI(IN2) = 3.3 V
D1 = High, D0 = Low (IN1 active), 75
Supply current from IN2 (operating) mA
VI(IN1) = 3.3 V
D0 = D1 = Low (IN2 active), VI(IN2) = 3.3 V 1 12
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V 55 90
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
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SBVS043A –MARCH 2004–REVISED MARCH 2010
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ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise
noted. TPS2110A, TPS2111A
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY AND LEAKAGE CURRENTS, continued
D0 = D1 = High (inactive), VI(IN2) = 3.3 V 0.5 2
Quiescent current from IN1 (standby) mA
D0 = D1 = High (inactive), VI(IN1) = 3.3 V 1
D0 = D1 = High (inactive), VI(IN2) = 3.3 V 1
Quiescent current from IN2 (standby) mA
D0 = D1 = High (inactive), VI(IN1) = 3.3 V 0.5 2
Forward leakage current from IN1 D0 = D1 = High (inactive), IN2 open, VO(OUT) 0.1 5 mA
(measured from OUT to GND) = 0 V (shorted), TJ= 25°C
Forward leakage current from IN2 D0 = D1 = High (inactive), IN1 open, VO(OUT) 0.1 5 mA
(measured from OUT to GND) = 0 V (shorted), TJ= 25°C
Reverse leakage current to INx (measured D0 = D1 = High (inactive), VI(INx) = 0 V, 0.3 5 mA
from INx to GND) VO(OUT) = 5.5 V, TJ= 25°C
CURRENT LIMIT CIRCUIT
RILIM = 400 Ω0.51 0.63 0.80
TPS2110A A
RILIM = 700 Ω0.30 0.36 0.50
Current limit accuracy RILIM = 400 Ω0.95 1.25 1.56
TPS2111A A
RILIM = 700 Ω0.47 0.71 0.99
Time for short-circuit output current to settle
Current limit settling time td1 ms
within 10% of its steady state value.
Input current at ILIM VI(ILIM) = 0 V, IO(OUT) = 0 A –15 0 mA
VSNS COMPARATOR
VI(VSNS) ↑0.78 0.80 0.82
VSNS threshold voltage V
VI(VSNS) ↓0.735 0.755 0.775
VSNS comparator hysteresis 30 60 mV
Deglitch of VSNS comparator (both ↑↓) 90 150 220 ms
Input current 0 V ≤VI(VSNS) ≤5.5 V –1 1 mA
UVLO
Falling edge 1.15 1.25
IN1 and IN2 UVLO V
Rising edge 1.30 1.35
IN1 and IN2 UVLO hysteresis 30 57 65 mV
Falling edge 2.4 2.53
Internal VDD UVLO V
(the higher of IN1 and IN2) Rising edge 2.58 2.8
Internal VDD UVLO hysteresis 30 50 75 mV
UVLO deglitch for IN1, IN2 Falling edge 110 ms
REVERSE CONDUCTION BLOCKING
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT
Minimum output-to-input to a 5-V supply through a series 1-kΩresistor.
voltage difference to block ΔVO(I_block) 80 100 120 mV
Let D0 = low. Slowly decrease the supply
switching voltage until OUT connects to IN1.
THERMAL SHUTDOWN
Thermal shutdown threshold TPS211xA is in current limit. 135 °C
Recovery from thermal shutdown TPS211xA is in current limit. 125 °C
Hysteresis 10 °C
IN2−IN1 COMPARATORS
Hysteresis of IN2−IN1 comparator 0.1 0.2 V
Deglitch of IN2−IN1 comparator (both ↑ ↓) 10 20 50 ms
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SBVS043A –MARCH 2004–REVISED MARCH 2010
SWITCHING CHARACTERISTICS
Over recommended operating junction temperature, VI(IN1) = VI(IN2) = 5.5 V, and RILIM = 400 Ω, unless otherwise noted.
TPS2110A TPS2111A
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
TJ= 25°C,
Output rise CL= 1 mF,
tRtime from an VI(IN1) = VI(IN2) = 5 V 0.5 1.0 1.5 1 1.8 3 ms
IL= 500 mA; see
enable Figure 1(a).
TJ= 25°C,
Output fall time CL= 1 mF,
tFVI(IN1) = VI(IN2) = 5 V 0.35 0.5 0.7 0.5 1 2 ms
from a disable IL= 500 mA; see
Figure 1(a).
IN1 to IN2 transition, TJ= 125°C,
VI(IN1) = 3.3 V, CL= 10 mF, 40 60 40 60
VI(IN2) = 5 V IL= 500 mA;
measure transition
tTTransition time time as 10% to 90% ms
IN2 to IN1 transition, rise time or from 3.4
VI(IN1) = 5 V, 40 60 40 60
V to 4.8 V on
VI(IN2) = 3.3 V VO(OUT). See
Figure 1(b).
Turn-on VI(IN1) = VI(IN2) = 5 V TJ= 25°C,
propagation Measured from CL= 10 mF,
tPLH1 0.5 1 ms
delay from an enable to 10% of IL= 500 mA; see
enable VO(OUT) Figure 1(a).
Turn-off VI(IN1) = VI(IN2) = 5 V TJ= 25°C,
propagation Measured from CL= 10 mF,
tPHL1 3 5 ms
delay from a disable to 90% of IL= 500 mA; see
disable VO(OUT) Figure 1(a).
Logic 1 to Logic 0
transition on D1,
Switch-over TJ= 25°C,
VI(IN1) = 1.5 V,
rising CL= 10 mF,
tPLH2 VI(IN2) = 5 V, 40 100 40 100 ms
propagation IL= 500 mA; see
VI(D0) = 0 V,
delay Figure 1(c).
Measured from D1 to
10% of VO(OUT)
Logic 0 to Logic 1
transition on D1,
Switch-over TJ= 25°C,
VI(IN1) = 1.5 V,
falling CL= 10 mF,
tPHL2 VI(IN2) = 5 V, 2 3 10 2 5 10 ms
propagation IL= 500 mA; see
VI(D0) = 0 V,
delay Figure 1(c).
Measured from D1 to
90% of VO(OUT)
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(c)
1.5V 1.85V
4.65V
5V
VO(OUT)
tPLH2 tPHL2
Switch#1Enabled Switch#1EnabledSwitch#2Enabled
(b)
3.3V
5V
4.8V
3.4V
VO(OUT)
tT
D D
O, 1
D D
O, 1
D D
O, 1
Switch#1Enabled Switch#2Enabled
10%
90% 90%
10%
tR
VO(OUT)
tPLH1 tPHL1
tF
0V
SwitchOff
SwitchOff SwitchEnabled
(a)
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
TIMING WAVEFORMS
Figure 1. Propagation Delays and Transition Timing Waveforms
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Product Folder Link(s): TPS2110A TPS2111A
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
1
2
3
4
8
7
6
5
TPS2110A
TPS2111A
www.ti.com
SBVS043A –MARCH 2004–REVISED MARCH 2010
DEVICE INFORMATION
TRUTH TABLE
D1 D0 VI(VSNS) > 0.8 V(1) VI(IN2) > VI(IN1) OUT(2)
0 0 X X IN2
0 1 Yes X IN1
0 1 No No IN1
0 1 No Yes IN2
1 0 X X IN1
1 1 X X Hi-Z
(1) X = Don’t care.
(2) The undervoltage lockout circuit causes the output to go Hi-Z if the selected power supply does not exceed the IN1/IN2 UVLO, or if
neither of the supplies exceeds the internal VDD UVLO.
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-8
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME NO. I/O DESCRIPTION
D0 1 I TTL- and CMOS-compatible input pins. Each pin has a 1-mA pull-up. The Truth Table
illustrates the functionality of D0 and D1.
D1 2 I
GND 5 Power Ground
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above
IN1 8 I the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is
IN2 6 I above the UVLO threshold and at least one supply exceeds the internal VDD UVLO.
A resistor (RILIM) from ILIM to GND sets the current limit ILto 250/RILIM and 500/RILIM for the
ILIM 4 I TPS2110A and TPS2111A, respectively.
OUT 7 O Power switch output
In the auto-switching mode (D0 = 1, D1 = 0), an internal power FET connects OUT to IN1 if
VSNS 3 I the VSNS voltage is greater than 0.8 V. Otherwise, the FET connects OUT to the higher of
IN1 and IN2. The Truth Table illustrates the functionality of VSNS.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2110A TPS2111A
Thermal
Sense
Charge
Pump
Q ison
2Q ison
1
UVLO(V )
DD
UVLO(IN2)
UVLO(IN1)
D0
D1
VI(SNS) >0.8V
VO(OUT) >VI(INx)
EN2 EN1
Control
Logic
+
+
100mV
0.8V
0.6V
Cross-Conduction
Detector
0.5V
k IO(OUT)
´
IO(OUT)
TPS2110A:k=0.2%
TPS2111A:k=0.1%
IN2
UVLO
VDD
UVLO
IN1
UVLO
V =0V
fV =0V
f
1 Am
1 Am
Internal VDD
IN1 8
IN2 6
D0
D1
1
2
VSNS 3
GND 5
IN1
IN2
EN1
Q1
Q2
4
7OUT
ILIM
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
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FUNCTIONAL BLOCK DIAGRAM
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Product Folder Link(s): TPS2110A TPS2111A
V
2V/div
I(D0)
V
2V/div
I(D1)
V
2V/div
O(OUT)
OUTPUTSWITCHOVERRESPONSE
OutputSwitchoverResponseTestCircuit
t Time 1ms/div--
TPS2111APW
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
0.1 Fm
0.1 Fm
3.3V
5V
400 W
f=28Hz
78%DutyCycle
1 Fm
V
2V/div
I(D0)
V
2V/div
I(D1)
V
2V/div
O(OUT)
OUTPUTTURN-ONRESPONSE
t Time 2ms/div-- OutputTurn-OnResponseTestCircuit
TPS2111APW
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
1 Fm
0.1 Fm
0.1 Fm
3.3V
5V
400 W
f=28Hz
78%DutyCycle
TPS2110A
TPS2111A
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SBVS043A –MARCH 2004–REVISED MARCH 2010
TYPICAL CHARACTERISTICS
Figure 2.
Figure 3.
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Product Folder Link(s): TPS2110A TPS2111A
V
2V/div
I(D0)
V
2V/div
I(D1)
V
2V/div
O(OUT)
OutputSwitchoverVoltageDroopTestCircuit
t Time 40 s/div- m-
TPS2111APW
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
0.1 Fm
0.1 Fm
5V
400 W
f=580Hz
90%DutyCycle
CL
OUTPUTSWITCHOVERVOLTAGEDROOP
CL=0 Fm
CL=1 Fm
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
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TYPICAL CHARACTERISTICS (continued)
Figure 4.
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Product Folder Link(s): TPS2110A TPS2111A
OutputSwitchoverVoltageDroopTestCircuit
OUTPUTSWITCHOVERVOLTAGEDROOP
vs
LOADCAPACITANCE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
D -VO(OUT) OutputVoltageDroop V-
0.1 1 10 100
C LoadCapacitance F- - m
L
VI=5V
RL=10 W
RL=50 W
TPS2111APW
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4
50 W10 W
0.1 Fm
0.1 Fm
VI
400 W
f=28Hz
50%DutyCycle
0.1 Fm1 Fm10 Fm47 Fm100 Fm
TPS2110A
TPS2111A
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SBVS043A –MARCH 2004–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
Figure 5.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
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TYPICAL CHARACTERISTICS (continued)
Figure 6.
12 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2110A TPS2111A
INRUSHCURRENT
vs
LOADCAPACITANCE
300
250
200
150
100
50
0
0 40 80 100
C LoadCapacitance F- - m
L
VI=5V
VI=3.3V
20 60
I InrushCurrent mA- -
I
OutputCapacitorInrushCurrentTestCircuit
TPS2111APW
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
450 W
0.1 Fm
0.1 Fm
VI
400 W
f=28Hz
90%DutyCycle
0.1 Fm1 Fm10 Fm47 Fm100 Fm
NC
ToOscilloscope
TPS2110A
TPS2111A
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SBVS043A –MARCH 2004–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
Figure 7.
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Product Folder Link(s): TPS2110A TPS2111A
180
160
140
120
100
80
60
r Switch-OnResistance m- W
DS(on) -
-50 0 50 100 150
T JunctionTemperature C- -
J°
TPS2110A
TPS2111A
120
115
110
105
100
95
90
85
80
r Switch-OnResistance m- W
DS(on) -
2 3 4 5 6
V SupplyVoltage V- -
I(INx)
TPS2111A
TPS2110A
0.96
0.94
0.92
0.90
0.88
0.86
0.84
0.82
I IN1SupplyCurrent A- - m
I(IN1)
2 3 4 5 6
V IN1SupplyVoltage V
I(IN1) - -
DeviceDisabled
V =0V
I =0A
I(IN2)
O(OUT)
60
58
56
54
52
50
48
46
44
42
40
I IN1SupplyCurrent A- - m
I(IN1)
2 3 4 5 6
V SupplyVoltage V
I(IN1) - -
IN1SwitchisOn
V =0V
I =0A
I(IN2)
O(OUT)
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
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TYPICAL CHARACTERISTICS (continued)
SWITCH ON-RESISTANCE SWITCH ON-RESISTANCE
vs vs
JUNCTION TEMPERATURE SUPPLY VOLTAGE
Figure 8. Figure 9.
IN1 SUPPLY CURRENT IN1 SUPPLY CURRENT
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 10. Figure 11.
14 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2110A TPS2111A
-50 0 50 100 150
T JunctionTemperature C- -
J°
1.2
1.0
0.8
0.6
0.4
0.2
0
I SupplyCurrent A- - m
I(INx)
DeviceDisabled
V =5.5V
V =3.3V
I =0A
I(IN1)
I(IN2)
O(OUT)
I =3.3V
I(IN2)
I =5.5V
I(IN1)
-50 0 50 100 150
T JunctionTemperature C- -
J°
I SupplyCurrent A- - m
I(INx)
IN1SwitchisOn
V =5.5V
V =3.3V
I =0A
I(IN1)
I(IN2)
O(OUT)
II(IN2)
II(IN1)
80
70
60
50
40
30
20
10
0
TPS2110A
TPS2111A
www.ti.com
SBVS043A –MARCH 2004–REVISED MARCH 2010
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT SUPPLY CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 12. Figure 13.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2110A TPS2111A
TPS2110A/TPS2111A
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4RL
RILIM
CL
C2
0.1 Fm
C1
0.1 Fm
IN2:2.8Vto5.5V
IN1:2.8Vto5.5V
NC
R2
R1
TPS2110A/TPS2111A
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
7
6
5
1
2
3
4RL
RILIM
CL
C2
0.1 Fm
C1
0.1 Fm
EN1
IN2:2.8Vto5.5V
IN1:2.8Vto5.5V
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
www.ti.com
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 14
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified value. Once the
voltage on IN1 falls below this value, the TPS211xA will select the higher of the two supplies. This usually means
that the TPS211xA will swap to IN2.
Figure 14. Auto-Selecting for a Dual Power-Supply Application
In Figure 15, the multiplexer selects between two power supplies based upon the EN1 logic signal. OUT
connects to IN1 if EN1 is logic '1'; otherwise, OUT connects to IN2. The logic thresholds for the D1 terminal are
compatible with both TTL and CMOS logic.
Figure 15. Manually Switching Power Sources
16 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2110A TPS2111A
TPS2110A
TPS2111A
www.ti.com
SBVS043A –MARCH 2004–REVISED MARCH 2010
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic '1' and D1 equal to logic '0' selects the auto-switching mode. In this mode, OUT connects to
IN1 if VI(VSNS) is greater than 0.8 V; otherwise, OUT connects to the higher of IN1 and IN2.
The VSNS terminal includes hysteresis equal to 3.75% to 7.5% of the threshold selected for transition from the
primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply
to the other due to resistive drops.
MANUAL SWITCHING MODE
D0 equal to logic '0' selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
'1'; otherwise, OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211xA switches from a higher-voltage supply to a lower-voltage supply, current can potentially
flow back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the
TPS211xA will not connect a supply to the output until the output voltage has fallen to within 100 mV of the
supply voltage. Once a supply has been connected to the output, it will remain connected regardless of output
voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/RILIM and 500/RILIM for the TPS2110A and
TPS2111A, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS211xA slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state (see
the Truth Table). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can glitch
the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot-plugging a load such as a PCI card. The TPS211xA slews the output
voltage at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output
voltage droop and reduces the output voltage hold-up capacitance requirement.
Copyright © 2004–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2110A TPS2111A
TPS2110A
TPS2111A
SBVS043A –MARCH 2004–REVISED MARCH 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March, 2004) to Revision A Page
• Updated document to current format .................................................................................................................................... 1
• Deleted package information from Available Options table .................................................................................................. 2
• Revised Ordering Information table ...................................................................................................................................... 2
• Deleted lead temperature and storage temperature specifications from, added electrostatic discharge specifications
to Absolute Maximum Ratings table; changed operating virtual junction temperature specification; deleted ESD
Protection table ..................................................................................................................................................................... 2
• Updated conditions for Electrical Characteristics ................................................................................................................. 3
• Deleted footnote 1 for Electrical Characteristics table .......................................................................................................... 3
• Deleted footnote 1 for Switching Characteristics table ......................................................................................................... 5
18 Submit Documentation Feedback Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS2110A TPS2111A
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2110APW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2110APWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2110APWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2110APWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111APW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111APWG4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111APWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2111APWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Feb-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2110APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TPS2111APWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2110APWR TSSOP PW 8 2000 367.0 367.0 35.0
TPS2111APWR TSSOP PW 8 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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