4 ADC/8 DAC with PLL,
192 kHz, 24-Bit Codec
AD1939
Rev. D
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FEATURES
PLL generated or direct master clock
Low EMI design
112 dB DAC/107 dB ADC dynamic range and SNR
−94 dB THD + N
Single 3.3 V supply
Tolerance for 5 V logic inputs
Supports 24-bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Differential DAC output
Log volume control with autoramp function
SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes up to 16-channel input/output
64-lead LQFP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Home Theater Systems
Set-top boxes
Digital audio effects processors
GENERAL DESCRIPTION
The AD1939 is a high performance, single-chip codec that
provides four analog-to-digital converters (ADCs) with
differential input, and eight digital-to-analog converters (DACs)
with differential output using the Analog Devices, Inc. patented
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
allowing a microcontroller to adjust volume and many other
parameters. The AD1939 operates from 3.3 V digital and analog
supplies. The AD1939 is available in a 64-lead (differential
output) LQFP package.
The AD1939 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the AD1939 eliminates
the need for a separate high frequency master clock and can
also be used with a suppressed bit clock. The DACs and ADCs
are designed using the latest Analog Devices continuous time
architectures to further minimize EMI. By using 3.3 V supplies,
power consumption is minimized, further reducing emissions.
FUNCTIONAL BLOCK DIAGRAM
DIGITAL
FILTER
SERIAL DAT A P ORT
DIG IT AL AUDIO
INPUT/OUTPUT
PRECISION
VOLTAGE
REFERENCE
TI M ING M ANAGEME NT
AND CONT ROL
(CLOCK AND PL L)
SPI
CONTROL PORT
CONTROL DATA
INPUT/OUTPUT
AD1939
ADC
ADC
ADC
ADC
A
NALOG
AUDIO
INPUTS
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
SDATA
OUT SDATA
IN
CLOCKS
06071-001
Figure 1.
AD1939
Rev. D | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Test Conditions............................................................................. 3
Analog Performance Specifications........................................... 3
Crystal Oscillator Specifications................................................. 4
Digital Input/Output Specifications........................................... 5
Power Supply Specifications........................................................ 5
Digital Filters................................................................................. 6
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 13
Analog-to-Digital Converters (ADCs).................................... 13
Digital-to-Analog Converters (DACs).................................... 13
Clock Signals............................................................................... 13
Reset and Power-Down ............................................................. 14
Serial Control Port ..................................................................... 14
Power Supply and Voltage Reference....................................... 15
Serial Data Ports—Data Format............................................... 15
Time-Division Multiplexed (TDM) Modes............................ 15
Daisy-Chain Mode..................................................................... 19
Control Registers ............................................................................ 24
Definitions................................................................................... 24
PLL and Clock Control Registers............................................. 24
DAC Control Registers .............................................................. 25
ADC Control Registers.............................................................. 27
Additional Modes....................................................................... 29
Application Circuits ....................................................................... 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
Automotive Products ................................................................. 31
REVISION HISTORY
7/11—Rev. C to Rev. D
Changes to Pin 15, Pin 18, Pin 19, and Pin 20 Descriptions ...... 9
Changes to Pin 26 and Pin 27 Descriptions................................ 10
9/10—Rev. B to Rev. C
Added Qualified for Automotive Applications to the Features
Section................................................................................................ 1
Changed Case Temperature from 130°C to 125°C ...................... 4
Changed TA from −40°C to +130°C to −40°C to +105°C ........... 5
Changed TA from −40°C to +130°C to −40°C to +105°C ........... 7
Changes to Ordering Guide .......................................................... 31
Added Automotive Products Section .......................................... 31
3/10—Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 31
6/07—Rev. 0 to Rev. A
Deleted I2C References.......................................................Universal
Change to Figure 1 ............................................................................1
Changes to Figure 2...........................................................................9
Changes to Table 10 ..........................................................................9
Changes to Table 11 ....................................................................... 14
Changes to Table 12 ....................................................................... 16
Changes to Figure 24 and Figure 25............................................. 22
Changes to Table 13 ....................................................................... 23
Change to Figure 26 ....................................................................... 23
Changes to Table 15 and Table 16 ................................................ 24
Changes to Figure 27 and Figure 28............................................. 29
Change to Figure 30 ....................................................................... 30
Updated Outline Dimensions....................................................... 31
Changes to Ordering Guide.......................................................... 31
7/06—Revision 0: Initial Version
AD1939
Rev. D | Page 3 of 32
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Supply voltages (AVDD, DVDD) 3.3 V
Temperature range1 As specified in Table 1 and Table 2
Master clock 12.288 MHz (48 kHz fS, 256 × fS mode)
Input sample rate 48 kHz
Measurement bandwidth 20 Hz to 20 kHz
Word width 24 bits
Load capacitance (digital output) 20 pF
Load current (digital output) ±1 mA or 1.5 kΩ to ½ DVDD supply
Input voltage high 2.0 V
Input voltage low 0.8 V
1 Functionally guaranteed at −40°C to +125°C case temperature.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at an ambient temperature of 25°C.
Table 1.
Parameter Conditions/Comments Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution All ADCs 24 Bits
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 96 102 dB
With A-Weighted Filter (RMS) 98 105 dB
Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB
Full-Scale Input Voltage (Differential) 1.9 V rms
Gain Error −10 +10 %
Interchannel Gain Mismatch −0.25 +0.25 dB
Offset Error −10 0 +10 mV
Gain Drift 100 ppm/°C
Interchannel Isolation −110 dB
CMRR 100 mV rms, 1 kHz 55 dB
100 mV rms, 20 kHz 55 dB
Input Resistance 14 kΩ
Input Capacitance 10 pF
Input Common-Mode Bias Voltage 1.5 V
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 102 107 dB
With A-Weighted Filter (RMS) 105 110 dB
With A-Weighted Filter (Average) 112 dB
Total Harmonic Distortion + Noise 0 dBFS
Two channels running −94 dB
Eight channels running −86 −76 dB
Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p)
Gain Error −10 +10 %
Interchannel Gain Mismatch −0.2 +0.2 dB
Offset Error −25 −6 +25 mV
Gain Drift −30 +30 ppm/°C
Interchannel Isolation 100 dB
AD1939
Rev. D | Page 4 of 32
Parameter Conditions/Comments Min Typ Max Unit
Interchannel Phase Deviation 0 Degrees
Volume Control Step 0.375 dB
Volume Control Range 95 dB
De-emphasis Gain Error ±0.6 dB
Output Resistance at Each Pin 100 Ω
REFERENCE
Internal Reference Voltage FILTR pin 1.50 V
External Reference Voltage FILTR pin 1.32 1.50 1.68 V
Common-Mode Reference Output CM pin 1.50 V
REGULATOR
Input Supply Voltage VSUPPLY pin 4.5 5 5.5 V
Regulated Output Voltage VSENSE pin 3.19 3.37 3.55 V
Specifications measured at a case temperature of 125°C.
Table 2.
Parameter Conditions/Comments Min Typ Max Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution All ADCs 24 Bits
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 93 102 dB
With A-Weighted Filter (RMS) 96 104 dB
Total Harmonic Distortion + Noise −1 dBFS −96 −87 dB
Full-Scale Input Voltage (Differential) 1.9 V rms
Gain Error −10 +10 %
Interchannel Gain Mismatch −0.25 +0.25 dB
Offset Error −10 0 +10 mV
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range 20 Hz to 20 kHz, −60 dB input
No Filter (RMS) 101 107 dB
With A-Weighted Filter (RMS) 104 110 dB
With A-Weighted Filter (Average) 112 dB
Total Harmonic Distortion + Noise 0 dBFS
Two channels running −94 dB
Eight channels running −86 −70 dB
Full-Scale Output Voltage 1.76 (4.96) V rms (V p-p)
Gain Error −10 +10 %
Interchannel Gain Mismatch −0.2 +0.2 dB
Offset Error −25 −6 +25 mV
Gain Drift −30 +30 ppm/°C
REFERENCE
Internal Reference Voltage FILTR pin 1.50 V
External Reference Voltage FILTR pin 1.32 1.50 1.68 V
Common-Mode Reference Output CM pin 1.50 V
REGULATOR
Input Supply Voltage VSUPPLY pin 4.5 5 5.5 V
Regulated Output Voltage VSENSE pin 3.2 3.43 3.65 V
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter Min Typ Max Unit
Transconductance 3.5 mmhos
AD1939
Rev. D | Page 5 of 32
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 4.
Parameter Conditions/Comments Min Typ Max Unit
High Level Input Voltage (VIH) 2.0 V
MCLKI/XI pin 2.2 V
Low Level Input Voltage (VIL) 0.8 V
Input Leakage IIH @ VIH = 2.4 V 10 μA
I
IL @ VIL = 0.8 V 10 μA
High Level Output Voltage (VOH) IOH = 1 mA DVDD − 0.60 V
Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V
Input Capacitance 5 pF
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter Conditions/Comments Min Typ Max Unit
SUPPLIES
Voltage DVDD 3.0 3.3 3.6 V
AVDD 3.0 3.3 3.6 V
VSUPPLY 4.5 5.0 5.5 V
Digital Current Master clock = 256 fS
Normal Operation fS = 48 kHz 56 mA
f
S = 96 kHz 65 mA
f
S = 192 kHz 95 mA
Power-Down fS = 48 kHz to 192 kHz 2.0 mA
Analog Current
Normal Operation 74 mA
Power-Down 23 mA
DISSIPATION
Operation Master clock = 256 fS, 48 kHz
All Supplies 429 mW
Digital Supply 185 mW
Analog Supply 244 mW
Power-Down, All Supplies 83 mW
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins 1 kHz, 200 mV p-p 50 dB
20 kHz, 200 mV p-p 50 dB
AD1939
Rev. D | Page 6 of 32
DIGITAL FILTERS
Table 6.
Parameter Mode Factor Min Typ Max Unit
ADC DECIMATION FILTER All modes, typical @ 48 kHz
Pass Band 0.4375 fS 21 kHz
Pass-Band Ripple ±0.015 dB
Transition Band 0.5 fS 24 kHz
Stop Band 0.5625 fS 27 kHz
Stop-Band Attenuation 79 dB
Group Delay 22.9844/fS 479 μs
DAC INTERPOLATION FILTER
Pass Band 48 kHz mode, typical @ 48 kHz 0.4535 fS 22 kHz
96 kHz mode, typical @ 96 kHz 0.3646 fS 35 kHz
192 kHz mode, typical @ 192 kHz 0.3646 fS 70 kHz
Pass-Band Ripple 48 kHz mode, typical @ 48 kHz ±0.01 dB
96 kHz mode, typical @ 96 kHz ±0.05 dB
192 kHz mode, typical @ 192 kHz ±0.1 dB
Transition Band 48 kHz mode, typical @ 48 kHz 0.5 fS 24 kHz
96 kHz mode, typical @ 96 kHz 0.5 fS 48 kHz
192 kHz mode, typical @ 192 kHz 0.5 fS 96 kHz
Stop Band 48 kHz mode, typical @ 48 kHz 0.5465 fS 26 kHz
96 kHz mode, typical @ 96 kHz 0.6354 fS 61 kHz
192 kHz mode, typical @ 192 kHz 0.6354 fS 122 kHz
Stop-Band Attenuation 48 kHz mode, typical @ 48 kHz 70 dB
96 kHz mode, typical @ 96 kHz 70 dB
192 kHz mode, typical @ 192 kHz 70 dB
Group Delay 48 kHz mode, typical @ 48 kHz 25/fS 521 μs
96 kHz mode, typical @ 96 kHz 11/fS 115 μs
192 kHz mode, typical @ 192 kHz 8/fS 42 μs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter Condition Comments Min Max Unit
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH MCLK duty cycle DAC/ADC clock source = PLL clock @ 256 fS, 384
fS, 512 fS, and 768 fS
40 60 %
tMH DAC/ADC clock source = direct MCLK @ 512 fS
(bypass on-chip PLL)
40 60 %
fMCLK MCLK frequency PLL mode, 256 fS reference 6.9 13.8 MHz
fMCLK Direct 512 fS mode 27.6 MHz
tPDR Low 15 ns
tPDRR Recovery Reset to active output 4096 tMCLK
PLL
Lock Time MCLK and LRCLK input 10 ms
256 fS VCO Clock, Output Duty Cycle,
MCLKO/XO Pin
40 60 %
AD1939
Rev. D | Page 7 of 32
Parameter Condition Comments Min Max Unit
SPI PORT See Figure 11
tCCH CCLK high 35 ns
tCCL CCLK low 35 ns
fCCLK CCLK frequency fCCLK = 1/tCCP; only tCCP shown in Figure 11 10 MHz
tCDS CIN setup To CCLK rising 10 ns
tCDH CIN hold From CCLK rising 10 ns
tCLS CLATCH setup To CCLK rising 10 ns
tCLH CLATCH hold From CCLK falling 10 ns
tCLHIGH CLATCH high Not shown in Figure 11 10 ns
tCOE COUT enable From CCLK falling 30 ns
tCOD COUT delay From CCLK falling 30 ns
tCOH COUT hold From CCLK falling, not shown in Figure 11 30 ns
tCOTS COUT tristate From CCLK falling 30 ns
DAC SERIAL PORT See Figure 24
tDBH DBCLK high Slave mode 10 ns
tDBL DBCLK low Slave mode 10 ns
tDLS DLRCLK setup To DBCLK rising, slave mode 10 ns
tDLH DLRCLK hold From DBCLK rising, slave mode 5 ns
tDLS DLRCLK skew From DBCLK falling, master mode −8 +8 ns
tDDS DSDATA setup To DBCLK rising 10 ns
tDDH DSDATA hold From DBCLK rising 5 ns
ADC SERIAL PORT See Figure 25
tABH ABCLK high Slave mode 10 ns
tABL ABCLK low Slave mode 10 ns
tALS ALRCLK setup To ABCLK rising, slave mode 10 ns
tALH ALRCLK hold From ABCLK rising, slave mode 5 ns
tALS ALRCLK skew From ABCLK falling, master mode −8 +8 ns
tABDD ASDATA delay From ABCLK falling 18 ns
AUXILIARY INTERFACE
tAXDS AAUXDATA setup To AUXBCLK rising 10 ns
tAXDH AAUXDATA hold From AUXBCLK rising 5 ns
tDXDD DAUXDATA delay From AUXBCLK falling 18 ns
tXBH AUXBCLK high 10 ns
tXBL AUXBCLK low 10 ns
tDLS AUXLRCLK setup To AUXBCLK rising 10 ns
tDLH AUXLRCLK hold From AUXBCLK rising 5 ns
AD1939
Rev. D | Page 8 of 32
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter Rating
θJA represents thermal resistance, junction-to-ambient;
θJC represents the thermal resistance, junction-to-case.
All characteristics are for a 4-layer board.
Analog (AVDD) −0.3 V to +3.6 V
Digital (DVDD) −0.3 V to +3.6 V
VSUPPLY −0.3 V to +6.0 V Table 9. Thermal Resistance
Package Type θJA θJC
Input Current (Except Supply Pins) ±20 mA Unit
Analog Input Voltage (Signal Pins) –0.3 V to AVDD + 0.3 V 64-Lead LQFP 47 11.1 °C/W
Digital Input Voltage (Signal Pins) −0.3 V to DVDD + 0.3 V
Operating Temperature Range (Case) −40°C to +125°C ESD CAUTION
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD1939
Rev. D | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
64
NC
63
AVDD
62
LF
61
ADC2RN
60
ADC2RP
59
ADC2LN
58
ADC2LP
57
ADC1RN
56
ADC1RP
55
ADC1LN
54
ADC1LP
53
CM
52
AVDD
51
NC
50
NC
49
DVDD
17
DSDATA3
18
DSDATA2
19
DSDATA1
20
DBCLK
21
DLRCLK
22
VSUPPLY
23
VSENSE
24
VDRIVE
25
ASDATA2
26
ASDATA1
27
ABCLK
28
ALRCLK
29
CIN
30
COUT
31
DVDD
32
AGND 1
MCLKI/XI 2
MCLKO/XO 3
AGND 4
AVDD 5
OL3P 6
OL3N 7
OR3P 8
OR3N 9
OL4P 10
OL4N 11
OR4P 12
OR4N 13
PD/RST 14
DSDATA4 15
DGND 16
AGND
48
FILTR
47
AGND
46
AVDD
45
AGND
44
OR2N
43
OR2P
42
OL2N
41
OL2P
40
OR1N
39
OR1P
38
OL1P
36
CLATCH
35
CCLK
34
DGND
33
OL1N
37
AD1939
TOP VIEW
(Not to Scale)
DIFFERENTIAL
OUTPUT
NC = NO CONNECT
06071-021
Figure 2. 64-Lead LQFP, Differential Output, Pin Configuration
Table 10. Pin Function Descriptions
Pin No. In/Out Mnemonic Description
1 I AGND Analog Ground.
2 I MCLKI/XI Master Clock Input/Crystal Oscillator Input.
3 O MCLKO/XO Master Clock Output/Crystal Oscillator Output.
4 I AGND Analog Ground.
5 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
6 O OL3P DAC 3 Left Positive Output.
7 O OL3N DAC 3 Left Negative Output.
8 O OR3P DAC 3 Right Positive Output.
9 O OR3N DAC 3 Right Negative Output.
10 O OL4P DAC 4 Left Positive Output.
11 O OL4N DAC 4 Left Negative Output.
12 O OR4P DAC 4 Right Positive Output.
13 O OR4N DAC 4 Right Negative Output
14 I PD/RST Power-Down Reset (Active Low).
15 I/O DSDATA4 DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line
mode)/AUX DAC2 data out (to external DAC2).
16 I DGND Digital Ground.
17 I DVDD Digital Power Supply. Connect to digital 3.3 V supply.
18 I/O DSDATA3 DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line
mode)/AUX ADC2 data in (from external ADC2).
19 I/O DSDATA2 DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1
data in (from external ADC1).
20 I DSDATA1 DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
21 I/O DBCLK Bit Clock for DACs.
22 I/O DLRCLK LR Clock for DACs.
AD1939
Rev. D | Page 10 of 32
Pin No. In/Out Mnemonic Description
23 I VSUPPLY 5 V Input to Regulator, Emitter of Pass Transistor.
24 I VSENSE 3.3 V Output of Regulator, Collector of Pass Transistor.
25 O VDRIVE Drive for Base of Pass Transistor.
26 I/O ASDATA2 ADC Serial Data Output 2. Data Output from ADC2/TDM ADC data in/AUX DAC1 data
out (to external DAC1).
27 O ASDATA1 ADC Serial Data Output 1. Data Output from ADC1/TDM ADC data out/TDM data out.
28 I/O ABCLK Bit Clock for ADCs.
29 I/O ALRCLK LR Clock for ADCs.
30 I CIN Control Data Input (SPI).
31 I/O COUT Control Data Output (SPI).
32 I DVDD Digital Power Supply. Connect to digital 3.3 V supply.
33 I DGND Digital Ground.
34 I CCLK Control Clock Input (SPI).
35 I CLATCH Latch Input for Control Data (SPI).
36 O OL1P DAC 1 Left Positive Output.
37 O OL1N DAC 1 Left Negative Output.
38 O OR1P DAC 1 Right Positive Output.
39 O OR1N DAC 1 Right Negative Output.
40 O OL2P DAC 2 Left Positive Output.
41 O OL2N DAC 2 Left Negative Output.
42 O OR2P DAC 2 Right Positive Output.
43 O OR2N DAC 2 Right Negative Output.
44 I AGND Analog Ground.
45 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
46 I AGND Analog Ground.
47 O FILTR Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
48 I AGND Analog Ground.
49 NC No Connect.
50 NC No Connect.
51 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
52 O CM Common-Mode Reference Filter Capacitor Connection. Bypass with
47 μF||100 nF to AGND.
53 I ADC1LP ADC1 Left Positive Input.
54 I ADC1LN ADC1 Left Negative Input.
55 I ADC1RP ADC1 Right Positive Input.
56 I ADC1RN ADC1 Right Negative Input.
57 I ADC2LP ADC2 Left Positive Input.
58 I ADC2LN ADC2 Left Negative Input.
59 I ADC2RP ADC2 Right Positive Input.
60 I ADC2RN ADC2 Right Negative Input.
61 O LF PLL Loop Filter, Return to AVDD.
62 I AVDD Analog Power Supply. Connect to analog 3.3 V supply.
63 NC No Connect.
64 NC No Connect.
AD1939
Rev. D | Page 11 of 32
8
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0.08
0.06
0.04
0.02
0
–0.10
–0.08
–0.06
–0.04
–0.02
01161412108642
MAGNITUDE (dB)
FREQUENCY (kHz)
06071-002
Figure 3. ADC Pass-Band Filter Response, 48 kHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
045 101520253035
MAGNITUDE (dB)
FREQUENCY (kHz)
0
06071-003
Figure 4. ADC Stop-Band Filter Response, 48 kHz
0.0
6
0.04
0.02
–0.06
–0.04
–0.02
0
024168
MAGNITUDE (dB)
FREQUENCY (kHz)
06071-004
Figure 5. DAC Pass-Band Filter Response, 48 kHz
0
–150
–100
–50
0412 24 36
MAGNITUDE (dB)
FREQUENCY (kHz)
8
06071-005
Figure 6. DAC Stop-Band Filter Response, 48 kHz
0.10
–0.10
–0.05
0
0.05
09724824
MAGNITUDE (dB)
FREQUENCY (kHz)
6
06071-006
Figure 7. DAC Pass-Band Filter Response, 96 kHz
0
–150
–100
–50
0924 48 72
MAGNITUDE (dB)
FREQUENCY (kHz)
6
06071-007
Figure 8. DAC Stop-Band Filter Response, 96 kHz
AD1939
Rev. D | Page 12 of 32
0.5
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0681632
MAGNITUDE (dB)
FREQUENCY (kHz)
4
06071-008
Figure 9. DAC Pass-Band Filter Response, 192 kHz
–10
–8
–6
–4
–2
0
48 9664 80
MAGNITUDE (dB)
FREQUENCY (kHz)
06071-009
Figure 10. DAC Stop-Band Filter Response, 192 kHz
AD1939
Rev. D | Page 13 of 32
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
There are four analog-to-digital converter (ADC) channels in
the AD1939 configured as two stereo pairs with differential
inputs. The ADCs can operate at a nominal sample rate of 48 kHz,
96 kHz, or 192 kHz. The ADCs include on-board digital anti-
aliasing filters with 79 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 128
(48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are
supplied through two serial data output pins (one for each
stereo pair) and a common frame clock (ALRCLK) and bit
clock (ABCLK). Alternatively, one of the TDM modes can be
used to access up to 16 channels on a single TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to internal
switched capacitors. To isolate the external driving op amp from
the glitches caused by the internal switched capacitors, each in-
put pin should be isolated by using a series-connected external
100 resistor together with a 1 nF capacitor connected from
each input to ground. This capacitor must be of high quality, for
example, ceramic NP0 or polypropylene film.
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and do not need an external dc
bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a 1.4 Hz,
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff fre-
quency scales directly with sample frequency.
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The AD1939 digital-to-analog converter (DAC) channels are
arranged as differential, four stereo pairs giving eight analog
outputs for improved noise and distortion performance. The
DACs include on-board digital reconstruction filters with 70 dB
stop-band attenuation and linear phase response, operating at an
oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz
mode). Each channel has its own independently programmable
attenuator, adjustable in 255 steps in increments of 0.375 dB.
Digital inputs are supplied through four serial data input pins
(one for each stereo pair) and a common frame clock (DLRCLK)
and bit clock (DBCLK). Alternatively, one of the TDM modes can
be used to access up to 16 channels on a single TDM data line.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins, as well
as to provide differential-to-single-ended conversion in the case
of the differential output. Note that the use of op amps with low
slew rate or low bandwidth can cause high frequency noise and
tones to fold down into the audio band; exercise care in
selecting these components.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
The on-chip phase-locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI/XI pin. The default at power-up
is 256 × fS from the MCLKI/XI pin. In 96 kHz mode, the master
clock frequency stays at the same absolute frequency; therefore,
the actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if a
device in the AD1939 family is programmed in 256 × fS mode, the
frequency of the master clock input is 256 × 48 kHz = 12.288 MHz.
If the AD1939 is then switched to 96 kHz operation (by writing
to the SPI port), the frequency of the master clock should
remain at 12.288 MHz, which is 128 × fS in this example. In
192 kHz mode, this becomes 64 × fS.
The internal clock for the ADCs is 256 × fS for all clock modes.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for either the ADCs or DACs if
selected in the PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs set
to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock
stabilizes.
The internal master clock (MCLK) can be disabled in the PLL
and Clock Control 0 register to reduce power dissipation when
the AD1939 is idle. The clock should be stable before it is
enabled. Unless a standalone mode is selected (see the Serial
Control Port section), the clock is disabled by reset and must be
enabled by writing to the SPI port for normal operation.
To maintain the highest performance possible, limit the clock
jitter of the internal master clock signal to less than a 300 ps rms
time interval error (TIE). Even at these levels, extra noise or
tones can appear in the DAC outputs if the jitter spectrum
contains large spectral peaks. If the internal PLL is not used, it is
best to use an independent crystal oscillator to generate the
AD1939
Rev. D | Page 14 of 32
master clock. In addition, it is especially important that the
clock signal not pass through an FPGA, CPLD, or other large
digital chip (such as a DSP) before being applied to the
AD1939. In most cases, this induces clock jitter due to the
sharing of common power and ground connections with other
unrelated digital output signals. When the PLL is used, jitter in
the reference clock is attenuated above a certain frequency
depending on the loop filter.
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to their
default settings. To avoid pops, reset does not power down the
analog outputs. After RST is deasserted and the PLL acquires
lock condition, an initialization routine runs inside the
AD1939. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. To
guarantee proper startup, the RST pin should be pulled low by
an external resistor.
SERIAL CONTROL PORT
The AD1939 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. A standalone mode is also available for
operation without serial control; it is configured at reset using the
serial control pins. All registers are set to default, except the
internal MCLK enable is set to 1 and ADC BCLK and LRCLK
master/slave is set by the COUT pin. Standalone mode only
supports stereo mode with an I2S data format and 256 fS MCLK
rate. Refer to Table 11 for details. It is recommended to use a
weak pull-up resistor on CLATCH in applications that have a
microcontroller. This pull-up resistor ensures that the AD1939
recognizes the presence of a microcontroller.
The SPI control port of the AD1939 is a 4-wire serial control
port. The format is similar to the Motorola SPI format except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1939, the address is 0x04, shifted left one bit due to the R/W
bit. The second byte is the AD1939 register address and the
third byte is the data.
Table 11. Standalone Mode Selection
ADC Clocks CIN COUT CCLK CLATCH
Slave 0 0 0 0
Master 0 1 0 0
D0
D0
D8
D8
D22D23 D9
D9
C
LATCH
CCLK
CIN
COUT
t
CCH
t
CCL
t
CDS
t
CDH
t
CLS
t
CCP
t
CLH
t
COTS
t
COD
t
COE
06071-010
Figure 11. Format of the SPI Signal
AD1939
Rev. D | Page 15 of 32
POWER SUPPLY AND VOLTAGE REFERENCE
The AD1939 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
To minimize noise pickup, these pins should be bypassed with
100 nF ceramic chip capacitors placed as close to the pins as
possible. A bulk aluminum electrolytic capacitor of at least
22 F should also be provided on the same PC board as the
codec. For critical applications, improved performance is
obtained with separate supplies for the analog and digital sections.
If this is not possible, it is recommended that the analog and
digital supplies be isolated by means of a ferrite bead in series
with each supply. It is important that the analog supply be as
clean as possible.
The AD1939 includes a 3.3 V regulator driver that only requires
an external pass transistor and bypass capacitors to make a 5 V
to 3.3 V regulator. If the regulator driver is not used, connect
VSUPPLY, VDRIVE, and VSENSE to DGND.
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The ADC and DAC internal voltage reference (VREF) is brought
out on FILTR and should be bypassed as close as possible to the
chip with a parallel combination of 10 F and 100 nF. Any
external current drawn should be limited to less than 50 A.
The internal reference can be disabled in the PLL and Clock
Control 1 register and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. The total gain
from ADC input to DAC output remains constant.
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 F and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
SERIAL DATA PORTS—DATA FORMAT
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The four ADC channels use a common serial bit
clock (ABCLK) and left-right framing clock (ALRCLK) in the
serial data port. The clock signals are all synchronous with the
sample rate. The normal stereo serial modes are shown in
Figure 23.
The ADC and DAC serial data modes default to I2S. The ports
can also be programmed for left-justified, right-justified, and
TDM modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The DAC serial formats are
programmable according to the DAC Control 0 register. The
polarity of DBCLK and DLRCLK is programmable according to
the DAC Control 1 register. The ADC serial formats and serial
clock polarity are programmable according to the ADC Control 1
register. Both DAC and ADC serial ports are programmable to
become the bus masters according to DAC Control 1 register
and ADC Control 2 register. By default, both ADC and DAC
serial ports are in the slave mode.
TIME-DIVISION MULTIPLEXED (TDM) MODES
The AD1939 serial ports also have several different TDM serial
data modes. The first and most commonly used configurations
are shown in Figure 12 and Figure 13. In Figure 12, the ADC
serial port outputs one data stream consisting of four on-chip
ADCs followed by four unused slots. In Figure 13, the eight on-
chip DAC data slots are packed into one TDM stream. In this
mode, both DBCLK and ABCLK are 256 fS.
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB MSB–1 MSB–2 DATA
BCLK
LRCLK
SLOT 5 SLOT 6 SLOT 7 SLOT 8
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
06071-016
Figure 12. ADC TDM (8-Channel I2S Mode)
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
MSB MSB–1 MSB–2 DATA
BCLK
LRCLK
SLOT 5
LEFT 3
SLOT 6
RIGHT 3
SLOT 7
LEFT 4
SLOT 8
RIGHT 4
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
06071-017
Figure 13. DAC TDM (8-Channel I2S Mode)
The I/O pins of the serial ports are defined according to the
serial mode that is selected. For a detailed description of the
function of each pin in TDM and AUX modes, see Table 12.
The AD1939 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The DAC TDM-AUX mode is shown in Figure 14. In this mode,
the AUX channels are the last four slots of the TDM data stream.
These slots are extracted and output to the AUX serial port. It
should be noted that due to the high DBCLK frequency, this mode
is available only in the 48 kHz/44.1 kHz/32 kHz sample rate.
The AD1939 also allows system configurations with more than
four ADC channels as shown in Figure 15 (using 8 ADCs) and
Figure 16 (using 16 ADCs). Again, due to the high ABCLK fre-
quency, this mode is available only in the 48 kHz/44.1 kHz/32 kHz
sample rate.
AD1939
Rev. D | Page 16 of 32
Combining the AUX ADC and DAC modes results in a system
configuration of 8 ADCs and 12 DACs. The system, then, con-
sists of two external stereo ADCs, two external stereo DACs,
and one AD1939. This mode is shown in Figure 17 (combined
AUX DAC and ADC modes).
Table 12. Pin Function Changes in TDM and AUX Modes
Pin Mnemonic Stereo Modes TDM Modes AUX Modes
ASDATA1 ADC1 Data Out ADC TDM Data Out TDM Data Out
ASDATA2 ADC2 Data Out ADC TDM Data In AUX Data Out 1 (to Ext. DAC 1)
DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In
DSDATA2 DAC2 Data In DAC TDM Data Out AUX Data In 1 (from Ext. ADC 1)
DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) AUX Data In 2 (from Ext. ADC 2)
DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to Ext. DAC 2)
ALRCLK ADC LRCLK In/ADC LRCLK Out ADC TDM Frame Sync In/ADC TDM Frame Sync Out TDM Frame Sync In/TDM Frame Sync Out
ABCLK ADC BCLK In/ADC BCLK Out ADC TDM BCLK In/ADC TDM BCLK Out TDM BCLK In/TDM BCLK Out
DLRCLK DAC LRCLK In/DAC LRCLK Out DAC TDM Frame Sync In/DAC TDM Frame Sync Out AUX LRCLK In/AUX LRCLK Out
DBCLK DAC BCLK In/DAC BCLK Out DAC TDM BCLK In/DAC TDM BCLK Out AUX BCLK In/AUX BCLK Out
LEFT RIGHT
MSB MSB
MSB MSB
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
DLRCLK
(AUX PORT)
DBCLK
(AUX PORT)
ASDATA2
(
AUX1_OUT)
DSDATA4
(
AUX2_OUT)
MSB
EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2
8 ON-CHIP DAC CHANNELS
AUXILIARY DAC CHANNELS
APPEAR AT
AUX DAC PORTSUNUSED SLOTS
32 BITS
0
6071-051
Figure 14. 16-Channel DAC TDM-AUX Mode
AD1939
Rev. D | Page 17 of 32
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
ASDATA1
(TDM_OUT)
DLRCLK
(AUX PORT)
DBCLK
(AUX PORT)
DSDATA2
(AUX1_IN)
DSDATA3
(AUX2_IN)
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
ADC L1 ADC R1 ADC L2 ADC R2 AUX L1 AUX R1 AUX L2 AUX R2
8 ON-CHIP DAC CHANNELS
4 ON-CHIP ADC CHANNELS 4 AUX ADC CHANNELS
32 BITS
LEFT RIGHT
MSB
MSB MSB
MSB MSB
0
6071-050
Figure 15. 8-Channel AUX ADC Mode
LEFT RIGHT
MSB MSB
MSB MSB
DLRCLK
(AUX PORT)
DBCLK
(AUX PORT)
DSDATA2
(AUX1_IN)
DSDATA3
(AUX2_IN)
ALRCLK
ABCLK
ASDATA1
(TDM_OUT)
MSB
ADC L1 ADC R1 ADC L2 ADC R2 AUX L1 AUX R1 AUX L2 AUX R2 UNUSED UNUSED UNUSED UNUSEDUNUSED UNUSED UNUSED UNUSED
4 ON-CHIP ADC CHANNELS AUXILIARY ADC CHANNELS UNUSED SLOTS
32 BITS
06071-052
Figure 16. 16-Channel AUX ADC Mode
AD1939
Rev. D | Page 18 of 32
LEFT RIGHT
DLRCLK
(AUX PORT)
DBCLK
(AUX PORT)
MSB MSB
DSDATA2
(AUX1_IN)
MSB MSB
DSDATA3
(AUX2_IN)
MSB MSB
ASDATA2
(
AUX1_OUT)
MSB MSB
DSDATA4
(
AUX2_OUT)
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
EMPTY EMPTY EMPTY EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2
8 ON-CHIP DAC CHANNELS
AUXILIARY DAC CHANNELS
APPEAR AT
AUX DAC PORTSUNUSED SLOTS
ASDATA1
(TDM_OUT)
ADC L1 ADC R1 ADC L2 ADC R2 AUX L1 AUX R1 AUX L2 AUX R2 UNUSED UNUSED UNUSED UNUSEDUNUSED UNUSED UNUSED UNUSED
4 ON-CHIP ADC CHANNELS AUXILIARY ADC CHANNELS UNUSED SLOTS
0
6071-053
Figure 17. Combined AUX DAC and ADC Mode
AD1939
Rev. D | Page 19 of 32
DAISY-CHAIN MODE
The AD1939 also allows a daisy-chain configuration to expand
the system to 8 ADCs and 16 DACs (see Figure 18). In this
mode, the DBCLK frequency is 512 fS. The first eight slots of the
DAC TDM data stream belong to the first AD1939 in the chain
and the last eight slots belong to the second AD1939. The second
AD1939 is the device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1939 can be configured into a dual-line, TDM mode as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1939 in the chain and the last four channels belong to
the second AD1939.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1939 as shown in Figure 20.
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 fS
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 fS ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1939 must be grounded in
all modes of operation.
The I/O pins of the serial ports are defined according to the
serial mode selected. See Table 13 for a detailed description of
the function of each pin. See Figure 26 for a typical AD1939
configuration with two external stereo DACs and two external
stereo ADCs.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1939
DSDATA2 (TDM_OUT)
OF THE SECOND AD1939
THIS IS THE TDM
TO THE FIRST AD1939
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1939
FIRST
AD1939
06071-054
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1939 Daisy Chain)
AD1939
Rev. D | Page 20 of 32
06071-055
DLRCLK
DBCLK
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN) DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2
DSDATA3
(IN) DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4
DSDATA2
(OUT) DAC L1 DAC R1 DAC L2 DAC R2
DSDATA4
(OUT) DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
DSP
SECOND
AD1939
FIRST
AD1939
MSB
Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two-AD1939 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain
DLRCLK
DBCLK
DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2
DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4
32 BITS
MSB
06071-058
Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
ALRCLK
ABCLK
ASDATA2 (TDM_IN
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2
4 ADC CHANNELS OF FIRST IC IN THE CHAIN4 ADC CHANNELS OF SECOND IC IN THE CHAIN
ASDATA1 (TDM_OUT
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2
32 BITS
MSB
DSP
SECOND
AD1939
FIRST
AD1939
06071-056
Figure 21. ADC TDM Daisy-Chain Mode (256 fS ABCLK, Two-AD1939 Daisy Chain)
AD1939
Rev. D | Page 21 of 32
ALRCLK
ABCLK
4 ADC CHANNELS OF
SECOND IC IN THE CHAIN
4 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2
ASDATA1 (TDM_OUT
OF THE SECOND AD1939
IN THE CHAIN)
ADC L1 ADC R1 ADC L2 ADC R2
ASDATA2 (TDM_IN
OF THE SECOND AD1939
IN THE CHAIN)
32 BITS
MSB
DSP
SECOND
AD1939
FIRST
AD1939
06071-057
Figure 22. ADC TDM Daisy-Chain Mode (512 fS ABCLK, Two-AD1939 Daisy Chain)
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LRCLK
BCLK
SDAT
A
LSB LSB
LSB
LSB
LSB LSB
LEFT CHANNEL RIGHT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
LEFT CHANNEL RIGHT CHANNEL
MSB MSB
MSB
MSB
MSB MSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDAT
A
LSB LSB
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
MSB MSB
1/fS
06071-013
Figure 23. Stereo Serial Modes
AD1939
Rev. D | Page 22 of 32
DBCLK
DLRCLK
DSDATAx
LEFT-JUSTIFIED
MODE
DSDATAx
RIGHT-JUSTIFIED
MODE
DSDATAx
I
2
S-JUSTIFIED
MODE
t
DLH
t
DBH
t
DBL
t
DLS
t
DDS
MSB
MSB
MSB LSB
MSB–1
t
DDH
t
DDS
t
DDH
t
DDS
t
DDH
t
DDH
t
DDS
06071-014
Figure 24. DAC Serial Timing
ABCLK
ALRCLK
ASDATAx
LEFT-JUSTIFIED
MODE
ASDATAx
RIGHT-JUSTIFIED
MODE
ASDATAx
I2S-JUSTIFIED
MODE
tABH
LSB
MSB
MSB
MSB
MSB–1
tABL
tALS
tABDD
tABDD
tABDD
tALH
0
6071-015
Figure 25. ADC Serial Timing
AD1939
Rev. D | Page 23 of 32
Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12)
Pin Mnemonic Stereo Modes TDM Modes AUX Modes
ASDATA1 ADC1 Data Out ADC TDM Data Out TDM Data Out
ASDATA2 ADC2 Data Out ADC TDM Data In AUX Data Out 1 (to Ext. DAC 1)
DSDATA1 DAC1 Data In DAC TDM Data In TDM Data In
DSDATA2 DAC2 Data In DAC TDM Data Out AUX Data In 1 (from Ext. ADC 1)
DSDATA3 DAC3 Data In DAC TDM Data In 2 (Dual-Line Mode) AUX Data In 2 (from Ext. ADC 2)
DSDATA4 DAC4 Data In DAC TDM Data Out 2 (Dual-Line Mode) AUX Data Out 2 (to Ext. DAC 2)
ALRCLK ADC LRCLK In/ADC LRCLK Out ADC TDM Frame Sync In/ADC TDM Frame Sync Out TDM Frame Sync In/TDM Frame Sync Out
ABCLK ADC BCLK In/ADC BCLK Out ADC TDM BCLK In/ADC TDM BCLK Out TDM BCLK In/TDM BCLK Out
DLRCLK DAC LRCLK In/DAC LRCLK Out DAC TDM Frame Sync In/DAC TDM Frame Sync Out AUX LRCLK In/AUX LRCLK Out
DBCLK DAC BCLK In/DAC BCLK Out DAC TDM BCLK In/DAC TDM BCLK Out AUX BCLK In/AUX BCLK Out
AUX
ADC 1
LRCLK
BCLK
DATA
MCLK
AUX
ADC 2
LRCLK
BCLK
DATA
MCLK
AUX
DAC 1
AUX
DAC 2
LRCLK
BCLK
DATA
MCLK
LRCLK
BCLK
DATA
MCLK
30MHz
12.288MHz
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
SHARC
®
AD1939
TDM MASTER
AUX MASTER
FSYNC-TDM (RFS)
RxCLK
RxDATA
TxCLK
TxDATA
TFS (NC)
ASDATA2
DSDATA4
DBCLK
DLRCLK
DSDATA2
DSDATA3
MCLKI/XI
ASDATA1 ALRCLK ABCLK DSDATA1
06071-019
Figure 26. Example of AUX Mode Connection to SHARC (AD1939 as TDM Master/AUX Master Shown)
AD1939
Rev. D | Page 24 of 32
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1939 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address R/W Register Address Data
Bit 23:17 16 15:8 7:0
Table 15. Register Addresses and Functions
Address Function
0 PLL and Clock Control 0
1 PLL and Clock Control 1
2 DAC Control 0
3 DAC Control 1
4 DAC Control 2
5 DAC individual channel mutes
6 DAC L1 volume control
7 DAC R1 volume control
8 DAC L2 volume control
9 DAC R2 volume control
10 DAC L3 volume control
11 DAC R3 volume control
12 DAC L4 volume control
13 DAC R4 volume control
14 ADC Control 0
15 ADC Control 1
16 ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit Value Function Description
0 0 Normal operation PLL power-down
1 Power-down
2:1 00 INPUT 256 (× 44.1 kHz or 48 kHz) MCLKI/XI pin functionality (PLL active), master clock rate setting
01 INPUT 384 (× 44.1 kHz or 48 kHz)
10 INPUT 512 (× 44.1 kHz or 48 kHz)
11 INPUT 768 (× 44.1 kHz or 48 kHz)
4:3 00 XTAL oscillator enabled MCLKO/XO pin, master clock rate setting
01 256 × fS VCO output
10 512 × fS VCO output
11 Off
6:5 00 MCLKI/XI PLL input
01 DLRCLK
10 ALRCLK
11 Reserved
7 0 Disable: ADC and DAC idle Internal master clock enable
1 Enable: ADC and DAC active
AD1939
Rev. D | Page 25 of 32
Table 17. PLL and Clock Control 1 Register
Bit Value Function Description
0 0 PLL clock DAC clock source select
1 MCLK
1 0 PLL clock ADC clock source select
1 MCLK
2 0 Enabled On-chip voltage reference
1 Disabled
3 0 Not locked PLL lock indicator (read only)
1 Locked
7:4 0000 Reserved
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
Bit Value Function Description
0 0 Normal Power-down
1 Power-down
2:1 00 32 kHz/44.1 kHz/48 kHz Sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
5:3 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
7:6 00 Stereo (normal) Serial format
01 TDM (daisy chain)
10 DAC AUX mode (ADC-, DAC-, TDM-coupled)
11 Dual-line TDM
Table 19. DAC Control 1 Register
Bit Value Function Description
0 0 Latch in mid cycle (normal) BCLK active edge (TDM in)
1 Latch in at end of cycle (pipeline)
2:1 00 64 (2 channels) BCLKs per frame
01 128 (4 channels)
10 256 (8 channels)
11 512 (16 channels)
3 0 Left low LRCLK polarity
1 Left high
4 0 Slave LRCLK master/slave
1 Master
5 0 Slave BCLK master/slave
1 Master
6 0 DBCLK pin BCLK source
1 Internally generated
7 0 Normal BCLK polarity
1 Inverted
AD1939
Rev. D | Page 26 of 32
Table 20. DAC Control 2 Register
Bit Value Function Description
0 0 Unmute Master mute
1 Mute
2:1 00 Flat De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)
01 48 kHz curve
10 44.1 kHz curve
11 32 kHz curve
4:3 00 24 Word width
01 20
10 Reserved
11 16
5 0 Noninverted DAC output polarity
1 Inverted
7:6 00 Reserved
Table 21. DAC Individual Channel Mutes
Bit Value Function Description
0 0 Unmute DAC 1 left mute
1 Mute
1 0 Unmute DAC 1 right mute
1 Mute
2 0 Unmute DAC 2 left mute
1 Mute
3 0 Unmute DAC 2 right mute
1 Mute
4 0 Unmute DAC 3 left mute
1 Mute
5 0 Unmute DAC 3 right mute
1 Mute
6 0 Unmute DAC 4 left mute
1 Mute
7 0 Unmute DAC 4 right mute
1 Mute
Table 22. DAC Volume Controls
Bit Value Function Description
7:0 0 No attenuation DAC volume control
1 to 254 −3/8 dB per step
255 Full attenuation
AD1939
Rev. D | Page 27 of 32
ADC CONTROL REGISTERS
Table 23. ADC Control 0 Register
Bit Value Function Description
0 0 Normal Power-down
1 Power down
1 0 Off High-pass filter
1 On
2 0 Unmute ADC 1L mute
1 Mute
3 0 Unmute ADC 1R mute
1 Mute
4 0 Unmute ADC 2L mute
1 Mute
5 0 Unmute ADC 2R mute
1 Mute
7:6 00 32 kHz/44.1 kHz/48 kHz Output sample rate
01 64 kHz/88.2 kHz/96 kHz
10 128 kHz/176.4 kHz/192 kHz
11 Reserved
Table 24. ADC Control 1 Register
Bit Value Function Description
1:0 00 24 Word width
01 20
10 Reserved
11 16
4:2 000 1 SDATA delay (BCLK periods)
001 0
010 8
011 12
100 16
101 Reserved
110 Reserved
111 Reserved
6:5 00 Stereo Serial format
01 TDM (daisy chain)
10 ADC AUX mode (ADC-, DAC-, TDM-coupled)
11 Reserved
7 0 Latch in mid cycle (normal) BCLK active edge (TDM in)
1 Latch in at end of cycle (pipeline)
AD1939
Rev. D | Page 28 of 32
Table 25. ADC Control 2 Register
Bit Value Function Description
0 0
50/50 (allows 32, 24, 20, or 16 bit clocks (BCLKs)
per channel)
LRCLK format
1 Pulse (32 BCLKs per channel)
1 0 Drive out on falling edge (DEF) BCLK polarity
1 Drive out on rising edge
2 0 Left low LRCLK polarity
1 Left high
3 0 Slave LRCLK master/slave
1 Master
5:4 00 64 BCLKs per frame
01 128
10 256
11 512
6 0 Slave BCLK master/slave
1 Master
7 0 ABCLK pin BCLK source
1 Internally generated
AD1939
Rev. D | Page 29 of 32
ADDITIONAL MODES
The AD1939 offers several additional modes for board level
design enhancements. To reduce the EMI in board level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configura-
tion is applicable when the AD1939 master clock is generated
by the PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1939 in
cases of high speed TDM data transmission, the AD1939 can
latch in the data using the falling edge of DBCLK. This effec-
tively dedicates the entire BCLK period to the setup time. This
mode is useful in cases where the source has a large delay time
in the serial data driver. Figure 28 shows this pipeline mode of
data transmission.
Both the BCLK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
INTERNAL
DBCLK
DSDATAx
DLRCLK
INTERNAL
DBCLK
T
DM-DSDATAx
32 BITS
06071-059
Figure 27. Serial DAC Data Transmission in TDM Format Without DBCLK
(Applicable Only If PLL Locks to DLRCLK, This Mode Is Also Available in the ADC Serial Data Port)
DLRCLK
DBCLK
DSDATAx
DATA MUST BE VALID
AT THIS BCLK EDGE
MSB
0
6071-060
Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission
(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission,
This Mode Is Also Available in the ADC Serial Data Port)
AD1939
Rev. D | Page 30 of 32
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended
loop filters for LR clock and master clock as the PLL reference are shown in Figure 30. Output filters for the DAC outputs are shown in
Figure 31 and a regulator circuit is shown in Figure 32.
2
1
3OP275
–
+
6
7
5OP275
–
+
5.76kΩ
5.76kΩ237Ω
5.76kΩ
120pF
600Z
A
UDIO
INPUT
100pF
5.76kΩ
120pF
4.7µF
+
237Ω
4.7µF
+
100pF
1nF
NPO
1nF
NPO
ADCxN
ADCxP
06071-029
Figure 29. Typical ADC Input Filter Circuit
39nF
+2.2nF
LF LRCL
K
A
VDD2
3.32kΩ
5.6nF
390pF
LF MCLK
AVDD2
562Ω
06071-030
Figure 30. Recommended Loop Filters for LRCLK or MCLK PLL Reference
06071-031
2
1
3OP275
–
+2.2nF
NPO
AUDIO
OUTPUT
604Ω
68pF
NPO
560pF
NPO
270pF
NPO
DAC
O
UTN
3.01kΩ11kΩ
DAC
OUTP 1.50kΩ5.62kΩ
11kΩ
5.62kΩ
Figure 31. Typical DAC Output Filter Circuit (Differential)
10µF
+
E
C
B
VSUPPLY 5V
VSENSE 3.3V
FZT953
VDRIVE
1kΩ
100nF
10µF
+
100nF
06071-032
Figure 32. Recommended 3.3 V Regulator Circuit
AD1939
Rev. D | Page 31 of 32
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BCD
051706-A
TOP VIEW
(PINS DOWN)
1
16
17
33
32
48
4964
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
12.20
12.00 SQ
11. 80
PIN 1
1.60
MAX
0.75
0.60
0.45
10.20
10.00 SQ
9.80
VIEW A
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTATED 90° CCW
SEATING
PLANE
0.15
0.05
7°
3.5°
0°
Figure 33. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
AD1939YSTZ –40°C to +105°C 64-Lead LQFP ST-64-2
AD1939YSTZRL –40°C to +105°C 64-Lead LQFP, 13” Tape and Reel ST-64-2
AD1939WBSTZ –40°C to +105°C 64-Lead LQFP ST-64-2
AD1939WBSTZ-RL –40°C to +105°C 64-Lead LQFP, 13” Tape and Reel ST-64-2
EVAL-AD1939AZ Evaluation Board
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD1939W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
AD1939
Rev. D | Page 32 of 32
NOTES
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06071-0-7/11(D)
