HYMP112S648-Y5 - SK Hynix - Product.Network

This document is a general product description and is subject t o change without notice. Hynix Semiconductor do es not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.2 / Sep. 2005 1

200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 1Gb 1st ver.

This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 1Gb 1st ver. DDR2 SDRAMs

in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 1Gb 1st ver. based Unbuffered

DDR2 SO-DIMM series pr ovide a high perf ormance 8 byte inte rface in 67.60mm width form f actor of industry s tandard.

It is suitable for easy interchange and addition.

FEATURES

ORDERING INFORMATION

Notes:

* : ‘M’ stands for Hynix Dual Die Package(DDP) based module .

Part Name Density Organization # of

DRAMs # of

ranks Materials

HYMP112S648-E3/C4/Y5 1GB 128Mx64 8 1 Leaded

HYMP325S64M*8-E3/C4/Y5 2GB 256Mx64 16 2 Leaded

HYMP112S64P8-E3/C4/Y5 1GB 128Mx64 8 1 Lead free

HYMP325S64M*P8-E3/C4/Y5 2GB 256Mx64 16 2 Lead free

• JEDEC standard Double Data Rate2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

• All inputs and outputs are compatible with SS TL_1.8

interface

•Posted CAS

• Programmable CAS Latency 3 ,4 ,5

• OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

• Fully differential clock operations (CK & CK)

• Programmable Burst Length 4 / 8 with both

sequential and interleave mode

• Auto refresh and self refresh supported

• 8192 refresh cycles / 64ms

• Serial presence detect with EEPROM

• DDR2 SDRAM Package: 68 ball FBGA

• 67.60 x 30.00 mm form factor

• Lead-free Products are RoHS compliant

Rev. 1.2 / Sep. 2005 2

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

SPEED GRADE & KEY PARAMETERS

ADDRESS TABLE

E3 (DDR2-400) C4 (DDR2-533) Y5 (DDR2-667) Unit

Speed@CL3 400 400 400 Mbps

Speed@CL4 400 533 533 Mbps

Speed@CL5 - - 667 Mbps

CL-tRCD-tRP 3-3-3 4-4-4 5-5-5 tCK

Density Organization Ranks SDRAMs # of

DRAMs # of row/bank/column Address Refresh

Method

1GB 128M x 64 2 128Mb x 8 8 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms

2GB 256M x 64 2 128Mb x 8 16 14(A0~A13)/3(BA0~BA2)/10(A0~A9) 8K / 64ms

Rev. 1.2 / Sep. 2005 3

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN DESCRIPTION

Symbol Type Polarity Pin Description

CK[1:0], CK[1:0] Input Cross

Point

The system clock inputs. All adress an co mmands lines are sampled on the cross point

of the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is

driven from the clock inputs and ou tp ut timing for read operations is synchroni zed to

the input clock.

CKE[1:0] Input Active

High

Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when

low. By deactivating the clocks, CKE low initiates the Power Down mode or the Self

Refresh mode.

S[1:0] Input Active

Low

Enables the associated DDR2 SDRAM command decoder when low and disables the

command decoder when high. When the command decoder is disab led, new commands

are ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is

selected by S1

RAS, CAS, WE Input Active

Low When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS,

RAS and WE define the operation to be excecuted by the SDRAM.

BA[2:0] Input Selects which DDR2 SDRAM internal bank of four or eight is activated.

ODT[1:0] Input Active

High Asserts on-die terminat io n for DQ , DM, DQS and DQS signals if enabled via the DDR2

SDRAM mode register.

A[9:0], A10/AP,

A[15:11] Input

During a Bank Activate command cycle, difines the row address when sampled at the

cross point of the rising edge of CK and falling edge of CK. During a Read or Write com-

mand cycle, defines the column address when sampled at the cross point of the rising

edge of CK and falling edge of CK. In addition to the column address, AP is used to

invoke autoprecharge operation at the end of the burst read or write cycle. If AP is

high., autoprecharge is selected and BA0-BAn defines the bank to be precharged. If AP

is low, autoprecharge is disabled. During a Precharge command cycle., AP is used in

conjunction with BA0-BAn to control which bank(s) to precharge. If AP is high, all banks

will be prechar ged regardless of the state of BA0-BAn inputs. If AP is lo w, then BA0-BAn

are used to define which bank to precharge.

DQ[63:0] In/Out Data Input/Output pins.

DM[7:0] Input Active

High

The data write masks, associated with one data byte. In Write mode, DM operates as a

byte mask by allowing input data to be written if it is low but blocks the write operation

if it is high. In Read mode, DM lines have no effect.

DQS[7:0], DQS[7:0] In/Out Cross

point

The data strobe, associat ed w ith one data byte, sourced w hit data transfers. In Write

mode, the data strobe is sourced by the controller and is centered in the data window.

In Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading

edge of the data window. DQS signals are complements, and timing is relative to the

crosspoint of respective DQS and DQS. If the module is to be operated in single ended

strobe mode, all DQS signals must be tied on the system board to VSS and DDR2

SDRAM mode registers programmed approriately.

VDD, VDDSPD,VSS Supply Power supplies for core, I/O, Serial Presense Detect, and ground for the module.

SDA In/Out This is a bidirectional pin used to transfer data into or out of the SPD EE PROM. A

resister must be connected to VDD to act as a pull up.

SCL Input This signals is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from SCL to VDD to act as a pull up.

SA[1:0] Input Address pins used to select the Serial Presence Detect base address.

TEST In/Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory

modules(SODIMMs).

Rev. 1.2 / Sep. 2005 4

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN ASSIGNMENT

Pin Location

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side Pin

NO. Front

Side Pin

NO. Back

Side

1 VREF 2 VSS 51 DQS2 52 DM2 101 A1 102 A0 151 DQ42 152 DQ46

3 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47

5 DQ0 6 DQ5 55 DQ18 56 DQ22 105 A10/AP 106 BA1 155 VSS 156 VSS

7 DQ1 8 VSS 57 DQ19 58 DQ23 107 BA0 108 RAS 157 DQ48 158 DQ52

9 VSS 10 DM0 59 VSS 60 VSS 109 WE 110 S0 159 DQ49 160 DQ53

11 DQS0 12 VSS 61 DQ24 62 DQ28 111 VDD 112 VDD 161 VSS 162 VSS

13 DQS0 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODT0 163 NC,TEST 164 CK1

15 VSS 16 DQ7 65 VSS 66 VSS 115 NC/S1 116 A13 165 VSS 166 CK1

17 DQ2 18 VSS 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6 168 VSS

19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC/ODT1 120 NC 169 DQS6 170 DM6

21 VSS 22 DQ13 71 VSS 72 VSS 121 VSS 122 VSS 171 VSS 172 VSS

23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54

25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55

27 VSS 28 VSS 77 VSS 78 VSS 127 VSS 128 VSS 177 VSS 178 VSS

29 DQS1 30 CK0 79 CKE0 80 NC/CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60

31 DQS1 32 CK0 81 VDD 82 VDD 131 DQS4 132 VSS 181 DQ57 182 DQ61

33 VSS 34 VSS 83 NC 84 NC/A15 133 VSS 134 DQ38 183 VSS 184 VSS

35 DQ10 36 DQ14 85 BA2 86 NC/A14 135 DQ34 136 DQ39 185 DM7 186 DQS7

37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 VSS 187 VSS 188 DQS7

39 VSS 40 VSS 89 A12 90 A11 139 VSS 140 DQ44 189 DQ58 190 VSS

41 VSS 42 VSS 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62

43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 144 VSS 193 VSS 194 DQ63

45 DQ17 46 DQ21 95 VDD 96 VDD 145 VSS 146 DQS5 195 SDA 196 VSS

47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SA0

49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1

Front Back

139 41 199

240 200

42

Rev. 1.2 / Sep. 2005 5

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

1GB(128Mbx64) : HYMP112S648-E3/C4

CKE0

DQS0

ODT0

D0

/CS O DT CKE

DQS0 DQS

/DQS0 /DQS

DM0 DM

DQ0 I/O 0

DQ1 I/O 1

DQ2 I/O 2

DQ3 I/O 3

DQ4 I/O 4

DQ5 I/O 5

DQ6 I/O 6

I/O 7

DQ7

D1

/C S O DT CK E

DQS1 DQS

/DQS1 /DQS

DM1 DM

DQ8 I/O 0

DQ8 I/O 1

DQ10 I/O 2

DQ11 I/O 3

DQ12 I/O 4

DQ13 I/O 5

DQ14 I/O 6

I/O 7

DQ15

D2

/C S O DT CK E

DQS2 DQS

/DQS2 /DQS

DM2 DM

DQ16 I/O 0

DQ17 I/O 1

DQ18 I/O 2

DQ19 I/O 3

DQ20 I/O 4

DQ21 I/O 5

DQ22 I/O 6

I/O 7

DQ23

D3

/C S O DT CK E

DQS3 DQS

/DQS3 /DQS

DM3 DM

DQ24 I/O 0

DQ25 I/O 1

DQ26 I/O 2

DQ27 I/O 3

DQ28 I/O 4

DQ29 I/O 5

DQ30 I/O 6

I/O 7

DQ31

SCL SDA

A0

A1

A2

Serial PD

SCL SDA

WP

SA0

SA1

D5

/C S O DT CKE

DQS5 DQS

/DQS5 /DQS

DM5 DM

DQ40 I/O 0

DQ41 I/O 1

DQ42 I/O 2

DQ43 I/O 3

DQ44 I/O 4

DQ45 I/O 5

DQ46 I/O 6

I/O 7

DQ47

D6

/C S O DT CKE

DQS6 DQS

/DQS6 /DQS

DM6 DM

DQ48 I/O 0

DQ49 I/O 1

DQ50 I/O 2

DQ51 I/O 3

DQ52 I/O 4

DQ53 I/O 5

DQ54 I/O 6

I/O 7

DQ55

D7

/C S O DT CKE

DQS0 DQS

/DQS0 /DQS

DM0 DM

DQ56 I/O 0

DQ57 I/O 1

DQ58 I/O 2

DQ59 I/O 3

DQ60 I/O 4

DQ61 I/O 5

DQ62 I/O 6

I/O 7

DQ63

D4

/C S O DT CK E

DQS4 DQS

/DQS4 /DQS

DM4 DM

DQ32 I/O 0

DQ33 I/O 1

DQ34 I/O 2

DQ35 I/O 3

DQ36 I/O 4

DQ37 I/O 5

DQ38 I/O 6

I/O 7

DQ39

/S1 N.C.

ODT1 N.C.

CKE1 N.C.

3Ω+/− 5%

BA0-BA2

3Ω +/- 5%

A0-AN

/RAS

/CAS

/WE

SDRAMS D0-7

4 loads

CK0

/CK0

4 loads

CK1

/CK1 1. R esistor values are 22 Ohm +/- 5% .

Notes :

VDD SPD

VDD

VREF

VSS

Serial PD

SDRAMS DO-D7

SD R AM S D O-D 7, VD D and VD DQ

SDRAMS DO-D7, SPD

Rev. 1.2 / Sep. 2005 6

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

FUNCTIONAL BLOCK DIAGRAM

2GB(256Mbx64) : HYMP351S64M8-E3/C4

CKE1

/S1

ODT1

SCL SDA

A0

A1

A2

Serial PD

SCL SDA

WP

SA0

SA1

:

3Ω+/− 5%

D0,D8(DDP)

DQS0 DQS

/DQS0 /DQS

DM0 DM

DQ0 I/O 0

DQ1 I/O 1

DQ2 I/O 2

DQ3 I/O 3

DQ4 I/O 4

DQ5 I/O 5

DQ6 I/O 6

I/ O 7

DQ7

D1,D9(DDP)

DQS1 DQS

/DQS1 /DQS

DM1 DM

DQ8 I/ O 0

DQ8 I/ O 1

DQ10 I/ O 2

DQ11 I/ O 3

DQ12 I/ O 4

DQ13 I/ O 5

DQ14 I/ O 6

I/ O 7

DQ15

DQS2 DQS

/DQS2 /DQS

DM2 DM

DQ16 I/ O 0

DQ17 I/ O 1

DQ18 I/ O 2

DQ19 I/ O 3

DQ20 I/ O 4

DQ21 I/ O 5

DQ22 I/ O 6

I/ O 7

DQ23

DQS3 DQS

/DQS3 /DQS

DM3 DM

DQ24 I/ O 0

DQ25 I/ O 1

DQ26 I/ O 2

DQ27 I/ O 3

DQ28 I/ O 4

DQ29 I/ O 5

DQ30 I/ O 6

I/ O 7

DQ31

DQS5 DQS

/DQS5 /DQS

DM5 DM

DQ40 I/ O 0

DQ41 I/ O 1

DQ42 I/ O 2

DQ43 I/ O 3

DQ44 I/ O 4

DQ45 I/ O 5

DQ46 I/ O 6

I/ O 7

DQ47

DQS6 DQS

/DQS6 /DQS

DM6 DM

DQ48 I/ O 0

DQ49 I/ O 1

DQ50 I/ O 2

DQ51 I/ O 3

DQ52 I/ O 4

DQ53 I/ O 5

DQ54 I/ O 6

I/ O 7

DQ55

DQS7 DQS

/DQS7 /DQS

DM7 DM

DQ56 I/ O 0

DQ57 I/ O 1

DQ58 I/ O 2

DQ59 I/ O 3

DQ60 I/ O 4

DQ61 I/ O 5

DQ62 I/ O 6

I/ O 7

DQ63

DQS4 DQS

/DQS4 /DQS

DM4 DM

DQ32 I/ O 0

DQ33 I/ O 1

DQ34 I/ O 2

DQ35 I/ O 3

DQ36 I/ O 4

DQ37 I/ O 5

DQ38 I/ O 6

I/ O 7

DQ39

CKE0

/S0

ODT0

/CS 0 ODT 0 CKE 0 /CS 1 ODT 1 CKE1/CS 0 ODT 0 CKE0 /CS 1 OD T 1 CKE1

/ CS 0 ODT 0 CKE 0 /CS 1 ODT 1 CKE1

/CS 0 ODT 0 CKE 0 / CS 1 ODT 1 CKE 1

D2,D10(DDP)

D3,D11(DDP) D7,D15(DDP)

D6,D14(DDP)

D5,D13(DDP)

D4,D12(DDP)

1. Resistor values are 22 Ohm +/- 5%

Notes :

VDD SPD

VDD

VREF

VSS

Serial PD

SDRAMS DO-D15

SDRAMS DO- D15, VDD and V DD Q

SDRAMS DO- D15, SPD

BA0 ? BA2 10Ω+/-5 %

A0-AN

/RAS

/CAS

/WE

SDRAMS D0-15

8 loads

CK0

/CK0 8 loads

9.1 pF

8 loads

CK1

/CK1 8 loads

9.1 pF

Rev. 1.2 / Sep. 2005 7

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

ABSOLUTE MAXIMUM RATINGS

Notes:

1. Stress greater than those listed may cause permanent dama ge to the device. This is a stress r ating only, and device

functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating con

ditions for extended periods may affect reliablility.

OPERATING CONDITIONS

Notes:

1. Up to 9850 ft.

2. If the DRAM case temperature is Above 85oC, the Auto-Ref r esh command interval has to be reduced to

tREFI=3.9us. For Measurement conditions of TCASE, please refer to the JEDEC document JESD51-2.

DC OPERATING CONDITIONS (SSTL_1.8)

Notes:

1. VDDQ must be less than or equal to VDD.

2. Peak to peak ac noise on VREF may not exeed +/-2% VREF(dc)

3. VTT of transmitting device must track VREF of receiving device.

Parameter Symbol Value Unit Note

Voltage on VDD pin relative to Vss VDD - 1.0 V ~ 2.3 V V 1

Voltage on VDDL pin relative to Vss VDDL -0.5V ~ 2.3 V V 1

Voltage on VDDQ pin relative to Vss VDDQ - 0.5 V ~ 2.3 V V 1

Voltage on any pin relative to Vss VIN, VOUT - 0.5 V ~ 2.3 V V 1

Storage Temperature TSTG -50 ~ +100 oC1

Storage Humidity(without condensation) HSTG 5 to 95 % 1

Parameter Symbol Rating Units Notes

DIMM Operating temperature(ambient) TOPR 0 ~ +55 oC

DIMM Barometric Pressure(operating & storage) PBAR 105 to 69 K Pascal 1

DRAM Component Case Temperature Range TCASE 0 ~+95 oC2

Parameter Symbol Min Max Unit Note

Power Supply Voltage

VDD 1.7 1.9 V

VDDL 1.7 1.9 V

VDDQ 1.7 1.9 V 1

Input Reference Voltage VREF 0.49 x VDDQ 0.51 x VDDQ V2

EEPROM Supply Voltage VDDSPD 1.7 3.6 V

Termination Voltage VTT VREF-0.04 VREF+0.04 V 3

Rev. 1.2 / Sep. 2005 8

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

INPUT DC LOGIC LEVEL

INPUT AC LOGIC LEVEL

AC INPUT TEST CONDITIONS

Notes:

1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device

under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges

and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.

3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions

and VIH(ac) to VIL(ac) on the negative transitions.

Parameter Symbol Min Max Unit Note

Input High Voltage VIH(DC) VREF + 0.125 VDDQ + 0.3 V

Input Low Voltage VIL(DC) -0.30 VREF - 0.125 V

Parameter Symbol DDR2 400/533 DDR2 667 Unit

Min Max Min Max

AC Input logic High VIH(AC) VREF + 0.250 - VREF + 0.200 - V

AC Input logic Low VIL(AC) -V

REF - 0.250 - VREF - 0.200 V

Symbol Condition Value Units Notes

VREF Input reference voltage 0.5 * VDDQ V1

VSWING(MAX) Input signal maximum peak to peak swing 1.0 V 1

SLEW Input signal minimum slew rate 1.0 V/ns 2, 3

VDDQ

VIH(ac) min

VIH(dc) min

VREF

VIL(dc) max

VIL(ac) max

VSS

V

SWING(MAX)

delta TRdelta TF

VREF

-

VIL

(ac)

max

delta TF

Falling Slew = Rising Slew =

VIH

(ac)

min

- V

REF

delta TR

< Figure : AC Input Test Signal Waveform>

Rev. 1.2 / Sep. 2005 9

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Differential Input AC logic Level

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS,

LDQS, UDQS and UDQS.

2. VID(DC) specifies the input differential voltage |VTR -V CP | required for switching, where VTR is the true input

(such as CK, DQS, LDQS or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level.

The minimum value is equal to VIH(DC) - VIL(DC).

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal

(such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS).

The minimum value is equal to V IH(AC) - VIL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to

track variations in VDDQ . VIX(AC) indicates the voltage at whitch differential input signals must cross.

DIFFERENTIAL AC OUTPUT PARAMETERS

Notes:

1. The typical v a lue of V OX(AC) is expected to be about 0.5 * VDDQ of the transmitting devi ce and VOX(AC) is expected to

track variations in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Symbol Parameter Min. Max. Units Note

VID (ac) ac differential input voltage 0.5 VDDQ + 0.6 V 1

VIX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175 V 2

Symbol Parameter Min. Max. Units Note

VOX (ac) ac differential cross point voltage 0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125 V 1

VDDQ

Crossing point

VSSQ

VTR

VCP

VID VIX or VOX

< Differential signal levels >

Rev. 1.2 / Sep. 2005 10

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

OUTPUT BUFFER LEVELS

OUTPUT AC TEST CONDITIONS

Notes:

1. The VDDQ of the device under test is referenced.

OUTPUT DC CURRENT DRIVE

Notes:

1. VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and

VDDQ - 280 mV.

2. VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.

3. The dc value of VREF applied to the receiving device is set to VTT

4. The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device

drive current capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an

SSTL_18 receiver.

The actual current values are deriv ed by shifting the desir ed driv er operating poin t along a 21 ohm load line to defin e

a convenient driver current for measurement.

Symbol Parameter SSTL_18 Units Notes

VOTR Output Timing Measurement Reference Level 0.5 * VDDQ V1

Symbol Parameter SSTl_18 Units Notes

IOH(dc) Output Minimum Source DC Current - 13.4 mA 1, 3, 4

IOL(dc) Output Minimum Sink DC Current 13.4 mA 2, 3, 4

Rev. 1.2 / Sep. 2005 11

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PIN Capacitance (VDD=1.8V,VDDQ=1.8V, TA=25℃. f=1MHz )

1GB : HYMP112S64[P]8

2GB : HYMP351S64M[P]8

Notes:

1. Pins not under test are tied to GND.

2. These value are guaranteed by design and tested on a sample basis only.

Pin Symbol Min Max Unit

CK, CK CCK 13 21 pF

CKE, ODT,CS CI1 24 38 pF

Address, RAS, CAS, WE CI2 23 40 pF

DQ, DM, DQS, DQS CIO 5 8 pF

Pin Symbol Min Max Unit

CK, CK CCK 25 49 pF

CKE, ODT,CS CI1 32 58 pF

Address, RAS, CAS, WE CI2 47 96 pF

DQ, DM, DQS, DQS CIO 16 20 pF

Rev. 1.2 / Sep. 2005 12

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

IDD SPECIFICATIONS (TCASE : 0 to 95oC)

1GB, 128M x 64 SO- DIMM : HYMP112S64[P]8

2GB, 256M x 64 SO - DIMM : HYMP325S64M[P]8

Notes:

1. IDD6 current values are guaranted up to Tcase of 85℃ max.

Symbol E3(DDR2 400@CL3) C4(DDR2 533@CL 4) Y5(DDR2 667@CL 5) Unit note

IDD0 800 880 960 mA

IDD1 880 960 1040 mA

IDD2P 48 48 56 mA

IDD2Q 320 400 480 mA

IDD2N 360 440 520 mA

IDD3P(F) 200 240 280 mA

IDD3P(S) 56 64 72 mA

IDD3N 480 560 640 mA

IDD4R 1040 1360 1840 mA

IDD4W 1120 1440 1920 mA

IDD5B 2160 2160 2160 mA

IDD6 64 64 64 mA 1

IDD6(L) 40 40 40 mA 1

IDD7 1920 2400 2720 mA

Symbol E3(DDR2 400@CL 3) C4(DDR2 533@CL 4) Y5(DDR2 667@CL 5) Unit note

IDD0 1280 1440 1600 mA

IDD1 1360 1520 1680 mA

IDD2P 96 96 112 mA

IDD2Q 640 800 960 mA

IDD2N 720 880 1040 mA

IDD3P(F) 400 480 560 mA

IDD3P(S) 112 128 144 mA

IDD3N 960 1120 1280 mA

IDD4R 1520 1920 2480 mA

IDD4W 1760 2080 2560 mA

IDD5B 2640 2720 2800 mA

IDD6 128 128 128 mA 1

IDD6(L) 80 80 80 mA 1

IDD7 2720 3120 3360 mA

Rev. 1.2 / Sep. 2005 13

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

IDD Meauarement Conditions

Notes:

1. IDD specifications are tested after the device is properly initialized

2. Input slew rate is specified by AC Parametric Test Condition

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS . IDD values must be met with all combinations

of EMRS bits 10 and 11.

5. Definiti ons for IDD

LOW is defined as Vin ≤ VILAC(max)

HIGH is defined as Vin ≥ VIHAC(min)

STABLE is defined as inputs stable at a HIGH or LOW level

FLOATING is defined as inputs at VREF = VDDQ/2

SWITCHING is defined as: inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and

control signals, and inputs changing between HIGH and LOW every other data transfer (once per clock)

for DQ signals not including masks or strobes.

Symbol Conditions Units

IDD0 Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS-

min(IDD);CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus

inputs are SWITCHIN G mA

IDD1 Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH

between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W mA

IDD2P Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2Q Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING mA

IDD2N Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD3P Active power-down current; All banks open; tCK = tCK(IDD); CKE is LOW ;

Other control and address bus inputs are STABLE; Data bus inputs are FLOAT-

ING

Fast PDN Exit MRS(12) = 0 mA

Slow PDN Exit MRS(12) = 1 mA

IDD3N Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is

HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHIN G mA

IDD4W Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK =

tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between v alid co mmands; Addr ess

bus inputs are SWITCHING; Data bus inputs are SWITCHING mA

IDD4R Operating burst read current; All banks open, Con ti nuo us burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL

= 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid com-

mands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W mA

IDD5B Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is

HIGH between valid commands; Other control an d a ddress bus inputs are SWITCHING; Data bus in puts are

SWITCHING mA

IDD6 Self refresh current; CK and CK at 0V; CKE ≤ 0.2V ; Other control and address bus inputs are FLOATING; Data

bus inputs are FLOATING. IDD6 current values are guaranted up to Tcase of 85 ℃ max. mA

IDD7

Operating bank interleave read current; All bank interleavi ng reads, IOUT = 0mA; BL = 4, CL = CL(IDD),

AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is

HIGH, CS is HIGH between v al id commands; Ad dress b us inputs are STABLE during DESELECTs; Data patt ern is

same as IDD4R; - Refer to the following page for detailed timing conditions

mA

Rev. 1.2 / Sep. 2005 14

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Electrical Characteristics & AC Timings

Speed Bins and CL,tRCD,tRP , tRC and tRAS for Corr esponding Bin

AC Timing Parameters by Speed Grade

Speed DDR2-667 (Y5) DDR2-533 (C4) DDR2-400 (E3) Unit

Bin(CL-tRCD-tRP) 5-5-5 4-4-4 3-3-3

Parameter min min min

CAS Latency 5 4 3 tCK

tRCD 15 15 15 ns

tRP 151515ns

tRAS 45 45 40 ns

tRC 606055ns

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps

DQS-Out edge to Clock edge Skew tDQSCK -500 500 -450 450 ns

Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK

Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK

Clock Half Period tHP min

(tCL,tCH) -min

(tCL,tCH) -ns

System Clock Cycle Time tCK 5000 8000 3750 8000 ps

DQ and DM input setup time tDS 150 - 100 - ps 1

DQ and DM input hold time tDH 275 - 225 - ps 1

DQ and DM input setup time(single-ended strobe) tDS1 25 - -25 - ps 1

DQ and DM input hold time(single-ended strobe) tDH1 25 - -25 - ps 1

Control & Address input Pulse Width for each input tIPW 0.6 - 0.6 - tCK

DQ and DM input pulse witdth for each input pul se

width for each input tDIPW 0.35 - 0.35 - tCK

Data-out high-impedance window from CK, /CK tHZ - tAC max - tAC max ps

DQS low-impedance time from CK/C K tLZ(DQS) tAC min tAC max t AC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 350 -300ps

DQ hold skew factor tQHS - 450 -400ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -tHP - tQHS -ps

First DQS latching transition to associated clock edge tDQSS -0.25 +0.25 -0.25 +0.25 tCK

DQS input high pulse width tDQSH 0.35 -0.35 -tCK

DQS input low pulse width tDQSL 0.35 -0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -0.2 -tCK

Mode register set com mand cycle time tMRD 2 - 2 - tCK

Write postamble tWPST 0.4 0.6 0.4 0.6 tCK

Write preamble tWPRE 0.35 -0.35 -tCK

Data-Out edge to Clock edge Skew tAC -600 600 -500 500 ps

Address and co ntrol input set u p time tIS 350 -250-ps

Rev. 1.2 / Sep. 2005 15

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

- Continued -

Notes:

1. For details and notes, please refer to the relevant Hynix component datasheet(HY5PS1G831(L)F).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-400 DDR2-533 Unit Note

Min Max Min Max

Address and control input hold time tIH 475 -375-ps

Read pr eambl e tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

Auto-Refresh to Active/Au to-Refresh command

period tRFC 127.5 -127.5 -ns

Row Active to Row Active Delay for 1KB page si ze tRRD 7.5 - 7.5 - ns

Four Activate Window for 1KB page size tFAW 37.5 - 37.5 - ns

Four Activate Window for 2KB page size tFAW 50 - 50 - ns

CAS to CAS command delay tCCD 2 2 tCK

Write recovery time tWR 15 -15-ns

Auto Precharge Write Recovery + Precharge Time tDAL tWR+tRP - tWR+tRP - tCK

Write to Read Command Delay tWTR 10 - 7.5 -ns

Internal read to precharge command delay tRTP 7.5 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 -200 -tCK

Exit precharge power down to any non-read

command tXP 2 - 2 - tCK

Exit active power down to read command tXARD 2 2 tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 6 - AL 6 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 33tCK

ODT turn-on delay tAOND 2222tCK

ODT turn-on tAON tAC(min) tAC(max)

+1 tAC(min) tAC(max)

+1 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+tAC

(max)+1 tAC(min)+2 2tCK+tAC

(max)+1 ns

ODT turn-off delay tAOFD 2.52.52.52.5tCK

ODT turn-off tAOF tAC(min) tAC(max)+

0.6 tAC(min) tAC(max)+

0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)+2 2.5tCK+tAC

(max)+1 tAC(min)+2 2.5tCK+tAC

(max)+1 ns

ODT to power down entry latency tANPD 3 3 tCK

ODT power down exit latency tAXPD 8 8 tCK

OCD drive mode output delay tOIT 0 12 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW tDelay tIS+tCK+tIH tIS+tCK+tIH ns

Average periodic Refresh Interval tREFI - 7.8 - 7.8 us 2

tREFI -3.9 -3.9 us 3

Rev. 1.2 / Sep. 2005 16

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

Parameter Symbol DDR2-667 Unit Note

min max

DQ output access time from CK/CK tAC -450 +450 ps

DQS output access time from CK/CK tDQSCK -400 +400 ps

CK high-level width tCH 0.45 0.55 tCK

CK low-level width tCL 0.45 0.55 tCK

CK half period tHP min(tCL,

tCH) -ps

Clock cycle time, CL=x tCK 3000 8000 ps

DQ and DM inpu t setup time

(differen t ial strobe ) tDS 100 - ps 1

DQ and DM input hold time

(differen t ial strobe ) tDH 175 - ps 1

Control & Address input pulse width for each input tIPW 0.6 - tCK

DQ and DM input pulse width for each input tDIPW 0.35 - tCK

Data-out high-impe dan ce time from CK/CK tHZ - tAC max ps

DQS low-impedance time from CK/C K tLZ(DQS) tAC min tAC max ps

DQ low-impedance time from CK/CK tLZ(DQ) 2*tAC min tAC max ps

DQS-DQ skew for DQS and associated DQ signals tDQSQ - 240 ps

DQ hold skew factor tQHS - 340 ps

DQ/DQS output hold time from DQS tQH tHP - tQHS -ps

First DQS latching transition to associated clock edge tDQSS - 0.25 + 0.25 tCK

DQS input high pulse width tDQSH 0.35 -tCK

DQS input low pulse width tDQSL 0.35 -tCK

DQS falling edge to CK setup time tDSS 0.2 -tCK

DQS falling edge hold time from CK tDSH 0.2 -tCK

Mode register set com mand cycle time tMRD 2 - tCK

Write postamble tWPST 0.4 0.6 tCK

Write preamble tWPRE 0.35 -tCK

Address and control input setup time tIS 200 -ps

Address and control input hold time tIH 275 -ps

Read pr eambl e tRPRE 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 tCK

Activate to precharge command tRAS 45 70000 ns

Active to active command period for 1KB page size

products tRRD 7.5 -ns

Four Active Window for 1KB page size products tFAW 37.5 -ns

Rev. 1.2 / Sep. 2005 17

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

- continued -

Note :

1. For details and notes, please refer to the relevant HYNIX component datasheet(HY5PS1G831(L)F).

2. 0°C ≤ TCASE ≤ 85°C

3. 85°C ＜ TCASE ≤ 95°C

Parameter Symbol DDR2-667 Unit Note

min max

CAS to CAS command delay tCCD 2tCK

Write recovery time tWR 15 -ns

Auto precharge write recovery + precharge time tDAL WR+tRP -tCK

Internal write to read command delay tWTR 7.5 -ns

Internal read to precharge command delay tRTP 7.5 ns

Exit self refresh to a non-read command tXSNR tRFC + 10 ns

Exit self refresh to a read command tXSRD 200 -tCK

Exit precharge power down to any non-read command tXP 2 - tCK

Exit active power down to read command tXARD 2tCK

Exit active power down to read command

(Slow exit, Lower power) tXARDS 7 - AL tCK

CKE minimum pulse width

(high and low pulse width) tCKE 3tCK

ODT turn-on delay tAOND 22tCK

ODT turn-on tAON tAC(min) tAC(max)

+0.7 ns

ODT turn-on(Power-Down mode) tAONPD tAC(min)+2 2tCK+

tAC(max)+1 ns

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC(min) tAC(max)+ 0.6 ns

ODT turn-off (Power-Down mode) tAOFPD tAC(min)

+2 2.5tCK+

tAC(max)+1 ns

ODT to power down entry latency tANPD 3 tCK

ODT power down exit latency tAXPD 8 tCK

OCD drive mode output delay tOIT 0 12 ns

Minimum time clocks remains ON after CKE

asynchronously drops LOW tDelay tIS+tCK+tIH ns

Average periodic Refresh Interval tREFI -7.8us2

tREFI -3.9 us 3

Rev. 1.2 / Sep. 2005 18

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

128Mx64 - HYMP112S64[P]8

Front

67.60

2.00 Min

4.00 +/-0.10

PIN 1 PIN 39 PIN 41 PIN 199

11.40 2.70

4.20

47.40

20.00

6.00

30.00

2.45 2.40

11.40 47.40

PIN 2 PIN 40 PIN 42 PIN 200

Back

3.8 max

1.00 ± 0.10

Side

note:

1. all dimension Units are millimeters.

2. all outline dimensions and tolerances match up to the JEDEC standard.

Detail-B

Detail-A

0.45±0.03

0.60

0.20±0.15

Detail of Contacts A

2.55

Detail of Contacts B (Front)

1.0±0.05

4.00±0.10

4.20

2.70±0.10

4.20

2.40±0.10 1.80

1.50

Detail of Contacts B (Back)

Rev. 1.2 / Sep. 2005 19

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

PACKAGE OUTLINE

256Mx64 - HYMP325S64M[P]8

Front

67.60

2.00 Min

4.00 +/-0.10

PIN 1 PIN 39 PIN 41 PIN 199

11.40 2.70

4.20

47.40

20.00

6.00

30.00

2.45 2.40

11.40 47.40

PIN 2 PIN 40 PIN 42 PIN 200

Back

note:

1. all dimension Units are millimeters.

2. all outline dimensions and tolerances match up to the JEDEC standard.

Side

3.8 max

1.00 ± 0.10

0.45±0.03

0.60

0.20±0.15

Detail of Contacts A

2.55

Detail of Contacts B (Front)

1.0±0.05

4.00±0.10

4.20

2.70±0.10

4.20

2.40±0.10 1.80

1.50

Detail of Contacts B (Back)

Detail-B

Detail-A

Rev. 1.2 / Sep. 2005 20

1200pin Unbuffered DDR2 SDRAM SO-DIMMs

REVISION HISTORY

Revision History Date

1.0 First Version Release - Data sheet coverage is changed from an individual module

part to a component based module family. Feb. 2005

1.1 Corrected module outline. Mar. 2005

Added VDDL spec, corrected tDS & tDH spec values. Apr. 2005

1.2 Added DDR2 667 Speed bin part Sep. 2005