ISP1763A PCI evaluation
board
UM0865
User manual
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
Abstract
This document describes board level operations of the ISP1763A PCI evaluation board.
Two version of the board are available: one for the TFBGA package and the other for the
VFQFPN package.
The ISP1763A PCI evaluation board allows engineers and software developers to create
USB host, device, and OTG features for customer applications.
Keywords
isp1763a; usb; universal serial bus; host controller; otg; on-the-go
ISP1763A PCI evaluation board User manual Legal information
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Legal information
© Copyright ST-Ericsson, 2010. All rights reserved.
Disclaimer
The contents of this document are subject to change without prior notice. ST-Ericsson
makes no representation or warranty of any nature whatsoever (neither expressed nor
implied) with respect to the matters addressed in this document, including but not limited
to warranties of merchantability or fitness for a particular purpose, interpretability or
interoperability or, against infringement of third party intellectual property rights, and in no
event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or
consequential damages and or loss whatsoever (including but not limited to monetary
losses or loss of data), that might arise from the use of this document or the information in
it.
ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of
companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget
LM Ericsson.
All other names are the property of their respective owners.
Trademark list
All trademarks and registered trademarks are the property of their respective owners.
ISP1763A PCI evaluation board User manual Contents
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Contents
1 About this document 5
1.1 Purpose 5
1.2 Revision information 5
1.3 Board history 5
1.4 Reference list 5
2 Introduction 6
2.1 Key features 6
2.2 Basic operation 8
2.2.1 Working with Linux OS 8
2.2.2 Working with Windows CE OS 8
3 Physical description 9
3.1 Board layout 9
3.2 Connectors 9
3.2.1 J1 PLX signals probe connector 10
3.2.2 J2 ISP1763A bus interface 10
3.2.3 J3, J4, J5, and J6 bus test headers 11
3.2.4 USB ports 11
3.2.5 JP1 Xilinx 3-state input 11
3.2.6 JP2 Xilinx PROG input 11
3.2.7 JP3 Xilinx JTAG connector 11
3.2.8 JP4 GND connector 12
3.2.9 JP5 GND connector 12
3.2.10 JP6 +5 V power select 12
3.2.11 JP7 VCC(I/O) select 12
3.2.12 PS1 PC power connector 12
3.2.13 PS2 DC power socket 12
3.2.14 CON1 PCI connector 12
3.2.15 CN1 PXA320 platform connector 13
3.2.16 DC1 DM357platform connector 13
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3.2.17 Conf1* butterfly configuration 13
3.3 LEDs 14
3.4 Board components 15
3.4.1 ISP1763A chip 15
3.4.2 PLX9054 and 93LC56C EEPROM 16
3.4.3 Xilinx XC3S500E 17
4 Schematics 18
5 List of materials 25
Glossary 29
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1 About this document
1.1 Purpose
This document provides description on how to use the evaluation module to develop
software for customers.
1.2 Revision information
Table 1 Revision history
Date Rev. Comments
2010-02-12 1 First release.
2010-04-05 2 Updated the last paragraph of Section 3.2.3 and Section 3.2.7.
Changed the package name from HVQFN to VFQFPN.
1.3 Board history
Table 2 Board history
Date Rev. Comments
2009-10-30 09283-1 ISP1763 PCI evaluation board (TFBGA) first release.
2009-10-30 09282-1 ISP1763 PCI evaluation board (VFQFPN) first release.
1.4 Reference list
[1] Universal Serial Bus Specification Rev. 2.0 www.usb.org
[2] PCI Local Bus Specification Version 2.2
[3] PLX PCI 9054 Data Sheet
[4] ISP1763A PCI evaluation board - FPGA design
(UM0887) CD00259895
[5] ISP1763A Hi-Speed USB OTG controller data sheet CD00264885
[6] ISP1763A programming guide (PM007 0) CD00265095
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2 Introduction
This section provides a description of the ISP1763A PCI evaluation board along with the
key features and a block diagram of the circuit board.
2.1 Key features
The ISP1763A is a Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) dual-role
controller with two USB ports. Port 1 is configurable as a host controller, an OTG
controller, or a peripheral controller, while port 2 is always assigned to the host controller.
The ISP1763A bus interface provides SRAM, general-multiplex, NOR, and NAND modes
to communicate with most types of microcontrollers and microprocessors.
The PCI bridge board allows you to demonstrate the functionality of the ISP1763A on a
standard PC with at least one PCI slot.
ISP1763A
PLX9054
PCI CONNECTOR
XILINX
EEPROM
JTAG
POWER
3.3 V SUPPLY
2.5 V SUPPLY
1.8 V SUPPLY
Figure 1 Block diagram of the ISP1763A PCI evaluation board
Key features include:
• 12 MHz crystal clock input
• One OTG port, one host only port
• Four types of bus interfaces
• FPGA configuration
• PCI connection
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• Multiple voltage power supply
• All local bus signals are easily accessible on test headers designed for direct
connection of a standard Tektronix logic analyzer
Figure 2 ISP1763A PCI evaluation board—VFQFPN
Figure 3 ISP1763A PCI evaluation board—TFBGA
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2.2 Basic operation
2.2.1 Working with Linux OS
Any x86-based computer that has a PCI slot (32-bit, 33 MHz) running with Linux Red Hat
kernel can be used. The type of Linux Red Hat installation determines minimum system
requirements. The minimum recommended system configuration is a Pentium-class
processor (1 GHz) with 128 MB RAM.
2.2.2 Working with Windows CE OS
An x86-based computer that has an available PCI slot (32-bit, 33 MHz) running Windows
CE ver. 5.0 or ver. 6.0 OS can be used. For ST-Ericsson set-up example, use Gigabyte
GA-945GZM-S2 motherboard (on board Ethernet controller disabled) with RealTek PCI
Ethernet card (PCI vendor ID is 10ECh and device ID is 8139h), and a standard 1.44 MB
floppy disk drive (for system boot up). Follow this hardware configuration as much as
possible, especially the motherboard and the Ethernet card.
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3 Physical description
This section describer the physical layout of the ISP1763A PCI evaluation board and its
interface.
3.1 Board layout
The ISP1763A PCI evaluation board is 150 x 101.6 mm six-layer (TFBGA) or four-layer
(VFQFPN) printed-circuit board that is powered by the PCI slot power.
Figure 4 shows the layout of the top view of the ISP1763A PCI evaluation board.
Figure 4 ISP1763A PCI evaluation board - top view
3.2 Connectors
These connectors and jumpers are described in the following sections.
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Table 3 Connectors
Connector Function
J1 PLX signals probe connector 1
J2 ISP1763A bus interface
J3 Bus test header. Lower 8-bit AD bus.
J4 Bus test header. Control signal of the ISP1763A.
J5 Bus test header. Upper 8-bit AD bus.
J6 Bus test header. 8-bit address bus.
S3 / port 1 Micro-AB USB connector.
S2 / port 2 Standard-A USB connector.
JP1 Xilinx Tristate input. Tristate input to Xilinx to 3-state signals to the
ISP1763A.
JP2 Xilinx PROG input. When this jumper is connected, the FPGA code will
be loaded to Xilinx from U5.
JP3 Xilinx JTAG connector
JP4 GND connector
JP5 GND connector
JP6 +5 V power select
JP7 VCC(I/O) select
PS1 PC power connector
PS2 DC power socket
CON1 PCI connector
CN1 PXA320 platform connector
DC1 DM357 platform connector
Conf1* Butterfly configuration
3.2.1 J1 PLX signals probe connector
This is only for using the logic analyzer. Probe debug signals between FPGA and
PLX9054 communication.
The default setting is not mounted on board.
3.2.2 J2 ISP1763A bus interface
This header has all the address bus, data bus, and control signals of the ISP1763A.
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Figure 5 J2 bus interface
3.2.3 J3, J4, J5, and J6 bus test headers
These headers are only used to probe bus interface signals. Only for testing.
The J3 male header is for lower 8-bit AD[7:0] signals.
The J5 male header is for upper 8-bit AD[15:8] signals.
The J4 male header is for the DACK, DREQ, IRQ, CLE, ALE/ADV_N,
WR_N/RW_N/WE_N, RD_N/DS_N/RE_N/OE_N, and CS_N/CE_N control signals.
The J6 male header is for 8-bit A[7:0] signals.
3.2.4 USB ports
The ISP1763A has two ports.
• Port 1 can be configured as either the host controller or the peripheral controller.
Has a micro-AB USB connector on board.
• Port 2 is configured as the host controller. Has a standard-A USB host connector on
board.
3.2.5 JP1 Xilinx 3-state input
This is the 3-state input to Xilinx.
Connect pin 1 and pin 2. The Xilinx pins connected to the ISP1763A are not 3-stated.
Connect pin 3 and pin 2. The Xilinx pins connected to the ISP1763A are 3-stated.
3.2.6 JP2 Xilinx PROG input
This is the Xilinx PROG input. When this jumper is connected, the FPGA code will be
loaded to Xilinx from U5.
3.2.7 JP3 Xilinx JTAG connector
Figure 6 JP3 JTAG connector
Through the JTAG interface, download program into Xilinx XC3S500E.
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Use the Xilinx USB blaster to connect the JTAG interface on board. LED1 turns on when
FPGA successfully completes configuration.
3.2.8 JP4 GND connector
The GND connector is to connect the oscilloscope or logic analyzer probe.
3.2.9 JP5 GND connector
The GND connector is to connect the oscilloscope or logic analyzer probe.
3.2.10 JP6 +5 V power select
This is the 5 V power supply select.
Connect pin 1 and pin 2. 5 V is supplied by external power supply PS1 or PS2.
Connect pin 2 and pin 3. 5 V is supplied by the PCI slot (default).
3.2.11 JP7 VCC(I/O) select
This is the VCC(I/O) power supply select.
Connect pin 1 and pin 2. VCC(I/O) is powered by 3.3 V (default).
Connect pin 2 and pin 3. VCC(I/O) is powered by 1.8 V.
3.2.12 PS1 PC power connector
Used for external supply of +12 V from the PC power supply. Connect pin 1 and pin 2 of
JP6. 5 V is supplied by external power supply PS1.
This is not used when the ISP1763A is inserted into the PCI slot.
3.2.13 PS2 DC power socket
Used for the external supply of +12 V / 3 A from the DC power supply. Connect pin 1 and
pin 2 of JP6. 5 V is supplied by external power supply PS2.
This is not used when the ISP1763A is inserted into the PCI slot.
3.2.14 CON1 PCI connector
This is the standard PCI bus interface that is compliant with PCI Local Bus Specification
Ver. 2.2.
All PCI signals are connected to PLX9054 PCI-to-local bus I/O accelerator chip.
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3.2.15 CN1 PXA320 platform connector
By default, this connector is not mounted. Only for the BSQUARE PXA320 platform use.
While using this connector with the PXA320 platform, the ISP1763A PCI evaluation board
is powered by external DC +12 V / 3 A power supply PS2.
1. Connect pin 1 and pin 2 of jumper JP6. The evaluation board is powered by the
external power supply.
2. Connect pin 1 and pin 2 of jumper JP7. The I/O voltage of the ISP1763A is set at
3.3 V. The PXA320 platform does not provide 1.8 V.
3. Connect pin 2 and pin 3 of jumper JP1. It 3-states all I/O pins from the FPGA
connected to the ISP1763A IC.
4. Connect pin 1 and pin 2 of jumper JP2. The FPGA program is loaded from U5.
The program has the logic for the 3-state of the pins.
3.2.16 DC1 DM357platform connector
By default, this connector is not mounted. Only for the DAVINCI DM357 platform use.
While using this connector with the DM357 platform, the ISP1763A PCI evaluation board
is powered by external DC +12 V / 3 A power supply PS2.
1. Connect pin 1 and pin 2 of jumper JP6. The evaluation board is powered by the
external power supply.
2. Connect pin 2 and pin 3 of jumper JP7. The I/O voltage of the ISP1763A is set at
1.8 V. The DM357 platform does not provide 3.3 V.
3. Connect pin 2 and pin 3 of jumper JP1. It 3-states all I/O pins from the FPGA
connected to the ISP1763A IC.
4. Connect pin 1 and pin 2 of jumper JP2. The FPGA program is loaded from U5.
The program has the logic for the 3-state of pins.
3.2.17 Conf1* butterfly configuration
Frequency selection is done using pins FREQSEL1 and FREQSEL2. The corresponding
resistors are mounted to connect FREQSEL1 and FRESEL2 to GND or VCC(I/O).
• To connect FREQSEL2 to LOW, mount R111 and remove R113.
• To connect FREQSEL2 to HIGH, mount R113 and remove R111.
• To connect FREQSEL1 to LOW, mount R112 and remove R114.
• To connect FREQSEL1 to HIGH, mount R114 and remove R112.
The PIO mode selection is needed only for the actual platform validation.
On the x86 platform, PIO mode selection is done using the Xilinx FPGA code. The
mounting of resistors (R119 to R122) do not affect the mode selection done by Xilinx. To
configure in various modes, refer to ISP1763A PCI evaluation board - FPGA design
(UM0887).
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When the ISP1763A is connected to customer platform, mode selection is done using
pins CLE and ALE/ADV_N. The corresponding resistors are mounted to connect CLE and
ALE/ADV_N to GND or VCC(I/O).
• To connect CLE to LOW, mount R120 and remove R122.
• To connect CLE to HIGH, mount R122 and remove R120.
• To connect ALE/ADV_N to LOW, mount R119 and remove R121.
• To connect ALE/ADV_N to HIGH, mount R121 and remove R119.
Figure 7 Butterfly configuration
Table 4 Clock frequency and bu s interface configuration
Clock
frequency 12 MHz
(default) 19.2 MHz 24 MHz Reserved Comment
FREQSEL2 LOW LOW HIGH HIGH Through R111 to GND. Through
R113 to VCC(I/O).
FREQSEL1 LOW HIGH LOW HIGH Through R112 to GND. Through
R114 to VCC(IO).
Bus interface SRAM
(default) NAND NOR General
multiplex Comment
CLE HIGH LOW LOW HIGH Through R120 to GND. Through
R122 to VCC(I/O).
ALE/ADV_N HIGH LOW HIGH LOW Through R119 to GND. Through
R121 to VCC(I/O).
3.3 LEDs
The ISP1763A PCI evaluation board has seven LEDs that are located on the top side of
the board. Information regarding these LEDs is given in Table 5.
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Table 5 LED
LED Use Color
LED1 JTAG download or program done indicator Orange
LED2 VBUS2 volts indicator (After loading the host software, the light will be turned on.) Red
LED3 VBUS1 volts indicator (After loading the host software, the light will be turned on.) Red
LED4 +5 V indicator Blue
LED5 +1.8 V indicator Red
LED6 +2.5 V indicator Yellow
LED7 +3.3 V indicator Green
3.4 Board components
This describes the operation of the major board components on the ISP1763A PCI
evaluation board.
3.4.1 ISP1763A chip
The ISP1763A PCI evaluation board is available in two packages: TFBGA and VFQFPN.
Figure 8 ISP1763A VFQFPN
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Figure 9 ISP1763A TFBGA
Table 6 ISP1763A chip package information
Product Package Package description
ISP1763AETTM TFBGA64 64 balls; body 4 × 4 × 0.8 mm
ISP1763AHNTM VFQFPN64 64 terminals; body 9 × 9 × 1.0 mm
For the schematic design, there is no difference, except the chip footprint.
For the PCB layout, TFBGA is six-layered design whereas VFQFPN is only four-layered
design. All the components are same on both the boards, except the ISP1763A IC
package.
3.4.2 PLX9054 and 93LC56C EEPROM
PLX9054 is a PCI-to-local-bus accelerator. The ISP1763A is always a PCI target during
initialization, as well as during the data transfer phase to or from the ISP1763A memory.
Figure 10 PLX9054
When powering on or asserting the PCI_RESET signal, PLX9054 attempts to read the
serial EEPROM to check its presence.
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The 93LC56C EEPROM is required for the correct initialization of PLX9054. The serial
EEPROM contains information required to initialize PLX9054 registers. For details, refer
to Chapter 11 of PLX PCI 9054 Data Sheet.
The initial programming of 93C56 must be done in a serial EEPROM programmer.
Displaying and adjusting of certain parameters can be done using the PLXmon utility.
Figure 11 EEPROM 93C56
3.4.3 Xilinx XC3S500E
FPGA ensures adaptation between the ISP1763A generic bus interface and the PLX9054
local bus interface. The FPGA programming can be downloaded through the JTAG
interface.
Figure 12 Xilinx XC3S500E
For detail description of the FPGA programming, refer to ISP1763A PCI evaluation board
- FPGA design (UM088 7).
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4 Schematics
ISP1763A PCI EVALUATION BOARD
ISP1763A USB PORTS FPGA
PCI POWER CONNECTORS
Figure 13 Main
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GND
D13
DREQ
VBUS1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D14
D15
CS#
RD#
WE#
IRQ
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR7
ADDR6
DACK#
ALE
CLE
RESET#
FREQSEL1
FREQSEL2
GND
GND
PSW1_N
GND
DM1_Chip
GND
DP1_Chip
GND
ID
GND
PSW2_N
OC2
DM2_Chip
GND
DP2_Chip
GND
GND
Decoupling capacitor
VCC(IO)_Chip
ALE
FREQSEL1
FREQSEL2
CLE
12K , 1%
R116
12K,1%
R115
10K 0603 1/16W 1%_LF
R114
10K 0603 1/16W 1%_L F
R112
10K 0603 1/16W 1%_LF
R113
10K 0603 1/16W 1%_L F
R111
10K 0603 1/1 6W 1%_ LF
R121
10K 0603 1/16W 1%_L F
R119
10K 0603 1/16W 1%_LF
R122
10K 0603 1/16W 1%_L F
R120
100NF/50V 0603 10%_LF
C107
10NF/50V 0603 10% X7R_LF
C106
10NF/50V 0603 10% X7R_LF
C98
10NF/50V 0603 10% X7R_LF
C100
10NF/50V 0603 10% X7R_LF
C102
10NF/50V 0603 10% X7R_LF
C104
100NF/50V 0603 10%_LF
C99
100NF/50V 0603 10%_LF
C101
100NF/50V 0603 10%_LF
C103
100NF/50V 0603 10%_LF
C105
VCC(IO)_Chip
FSEL0_datasheet
FSEL1_datasheet
00
01
1
0
FREQSEL1
FREQSEL2
12MHz 19.2MHz 24MHzC lk f requenc y:
00
01
1
0
ALE
CLE
NAND NORB US in te r face
1
1
SRAM
General
Multiplex
ID
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
D15
D14
D13
D12
D11
D10
D9
D8
RD#
WE#
CS#
IRQ
ALE
DREQ
DACK#
CLE
D7
D6
D5
D4
D3
D2
D1
D0
PL ACE SUFFICIENT SPACE BETWEEN THE HEADERS FOR L A PROBE CONNECT ION
VCC(IO)_Chip
VCC(IO)_Chip
VCC(IO)_Chip
VCC(3V3)_Chip
VCC(3V3)_Chip
RREF1
RREF2
100NF/50V 0603 10%_LF
C113
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
CLE
ALE
DACK#
DREQ
IRQ
WE#
RD#
CS#
RESET# RESET#
OC2
VCC(IO)_Chip
TP4
VBUS1
DM1_Chip
DP1_Chip
PSW1_N
PSW2_N
DM2_Chip
DP2_Chip
DNM
TP3
TP5
DNM
DNM
DNM
DNM
VREG
VREG
5
1
2 3
4
SMB SO CKET
S1
10K
R117
10K
DNM R118
0RR123 0R
DNM
R124
100nF
C109
+
4.7uF/10V
C108
+
4.7uF/10V
DNM
C112
18PF/50V
0 60 3 5% _LF
C111
18PF/50V 0603 5%_LF
C110
1 2
3 4
5 6
78
910
11 12
13 14
15 16
HEADER2X8_LF
J3
1 2
3 4
5 6
78
910
11 12
13 14
15 16
HEADER2X8_LF
J5
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
HEADER2X8_LF
J4
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
HEADER2X8_LF
J6
CS10 12 .000MAB J-UT
X2
AGND
1
AD0
2
AD1
3
AD2
4
AD3
5
VCC(I/O)
6
AD4
7
AD5
8
AD6
9
AD7
10
AD8
11
AD9
12
AD10
13
AD11
14
VCC(I/O)
15
AD12
16
AD13
17
AD14
18
AD15
19
VREG(1V2)
20
CS_N/CE_N
21
RD_N/DS_N/RE_N/OE_N
22
WR_N/RW_N/WE_N
23
INT
24
VCC(I/O)
25
A0
26
A1
27
A2
28
A3
29
A4
30
A5
31
VREG(1V2)
32
A6 33
A7 34
V(CC(I/O) 35
DREQ 36
DACK 37
ALE/ADV_N 38
CLE 39
RESET_N 40
FREQSEL1 41
FREQSEL2 42
AGND 43
X1/CLKIN 44
X2 45
VREG(1V2) 46
AGND 47
PSW1_N 48
OC1/VBUS1 49
RREF1 50
AGND 51
DM1 52
53
DP1 54
AGND 55
ID 56
VCC(3V3) 57
RREF2 58
59
PSW2_N 60
OC2/VBUS2 61
DM2 62
63
DP2 64
DIEPAD
0
ISP1763A VFQFPN
U6
AGND
AGND
AGND
Figure 14 ISP1763A
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DNM
DNM
DM2_Chip
DP2_Chip
ID
VBUS1
DP1_Chip
DM1_Chip
PSW1_N
ENA 1
FLGA 2
FLGB 3
ENB 4
OUTB
5GND
6VIN
7OUTA
8
MIC2026-2
U8
+5V_usb_Chip
OC2
+5V_usb_Chip
+5V_usb_Chip
OC2
OUT2
OUT2
PSW2_N
10KR130
Host Socket
VBUS 1
D- 2
D+ 3
GND 4
Chassis 5
Chassis 6
USB CO N T YPE A RE CEPTACLE
S2
DNM
DNM
10K
DNM
R131
ID=0, A
ID=1, B
ID
OC2
OUT1
VBUS1
DM1_Chip
DP1_Chip
VBUS1
PSW1_N
VBUS1
PSW2_N
OC2
DM2_Chip
DP2_Chip
Port 1
Port2
V3V3
V3V3
100NF/50V
0603 10%_LF
C116
10KR127 10KR128
10KR129
10K
DNM
R135
0R
DNM
R133 0RR134
0R
R132
560R 0603 1/16W 1%_LF
R137
LED RED 3MM_LF
LED3
0R
DNM R126
100N F/50V 0603 1 0%_L F
C115
+
100uF/16V
C114
LED RED 3MM_LF
LED2
560R 0603 1/16W 1%_LF
R125
100K
R136
+
4.7uF/35V
C117
100nF
C118 +
100uF/16V
DNMC119
0RR138
OTG Sock e t
VBUS 1
D- 2
D+ 3
ID 4
Chassis 8
Chassis 9
Chassis 7
Chassis 6
GND 5
USB_AB_MICRO
S3
BLM31A260S
FB1
BLM31A260S
FB2
B2
A2
A1
B1
USBULC6-2F3
U7
B2
A2
A1
B1
USBULC6-2F3
U9
B2
A2
A1
B1
USBULC6-2F3
U10
B2
A2
A1
B1
USBULC6-2F3
U11
Figure 15 USB ports
ISP1763A PCI evaluation board User manual Schematics
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
21 (29)
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA31
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
TSIZ0
TSIZ1
LW/R#
PROG_B
LW/R#
LA[31..16]
TSIZ0
TSIZ1
GCLK
DIN
INIT
RESET#
CLK
DONE
TMS
TDOI
TCK
TDI
LA30
LA29
LA28
LA27
LA26
LA25
LA24
D15
D14
D13
D12
RD#
WE#
CS#
IRQ
ALE
DREQ
DACK#
CLE
D11
D10
D9
D8
ADDR7
D7
ADDR6
D6
ADDR5
D5
D4
ADDR4
ADDR3
D3
D2
ADDR2
D1
D0
ADDR1
ADDR0
LINT#
LRESET#
BLAST#
LSERR#
ADS#
LHOLDA
LINT#
LRESET#
BLAST#
LS ERR#
ADS#
LHOL DA
LHOLD
LREADY#
LD[15..0]
D0
1
NC
2
CLK
3
TDI
4
TMS
5
TCK
6
CF
7
OE/RST
8
NC
9
CE
10 GND 11
NC 12
CEO 13
NC 14
NC 15
NC 16
TDO 17
VCCINT 18
VCCO 19
VCCJ 20
XCF04S
U5
V3V3
V2V5
V2V5 VIO V3V3
DIN
CLK
TDOI
TMS
TCK
TDO
V3V3
PROG_B
INIT
DONE
V2V5
V1V2
V3V3
V3V3
V2V5
V3V3
VIO
V2V5
V1V2
VIOVIOV2V5
V2V5 V1V2
V3V3 V3V3
V2V5 V3V3
V2V5
VIO
V1V2
VIO
VIO
V2V5
V3V3
TCK
TDO
TDI
TMS
V1V2
V3V3
V3V3
V2V5
VIO
VIO
LD15
LD14
LD13
LD12
V2V5
GND
V1V2
GND
V3V3
GND
GND
V3V3
V3V3
V2V5
GND
GND
VIO
V2V5
V1V2
GND
VIO
GND
GND
VIO
V2V5
GNDV2V5
V1V2
GND
V3V3
GND
GND
GND
V2V5
V3V3
V3V3
GND
LHOLD
GND
V2V5
VIO
V1V2
GND
VIO
GND
GND
VIO
V2V5
GND
V3V3
V3V3
Bank 0
Bank 3
Bank 2
Bank 1
TEST
LREADY#
1 00 NF/5 0V 0603 Y5V_LF
C33 C38 C43 C48 C53 C58 C63 C68 C73 C78
C39
1 00 NF/5 0V 0603 Y5V_LF
C34 C44 C49 C54 C59 C64 C69 C74 C79
10 NF/50V 0603 10% X7R _LF
C35 C40 C45 C50 C55 C60 C65 C70 C75 C80
1 00 NF/5 0V 0603 Y5V_LF
C36
10 NF/50V 0603 10% X7R _LF
C37
C41
C42
C46 C51 C56 C61 C66 C71 C76 C81
C47 C52 C57 C62 C67 C72 C77 C82
100NF/50V 0603 Y5V_LF
C83 C85 C86 C87 C88 C89 C90 C91 C92C84
100NF/50V
0603 Y5V_LF
C93
1 00NF /50V 0603 Y5 V_LF
C95
4U7F/10V 0603 Y5V_LF
C96
OSCCLK
OSCCLK
Female - IDE connector
pin orientation of the header as seen from
the top view (top layer)
2 PIN MALE HEADER FOR CRO PROBE
GCLK
LCLK
GCLK
LCLK
OSCCLK
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
DACK#
CLE
IRQ
RD#
CS#
RESET#
WE#
D0
D1
D2
D3
D4
D5
D6
D7
DREQ
D8
D9
D10
D11
D12
D13
D14
D15
GND
GND
GND
GND
GND
GND
GND
ALE
0RR61
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0 ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
RESET#
CLE
ALE
DACK#
DREQ
IRQ
WE#
RD#
CS#
DR EQ 0#
DACK0#
VIO
hswap
du ring configuration:
HSWAP: 0:user io pull up enable
HSWAP: 1:user io pull up disable
VIO
Dout
V2V5
V3V3
TP1
TP2
TEST
M2
M1
M0
When connect
jumper, FPGA
can be loaded
W\hen disconnect
jumper, FPGA
can’t be loaded
1763_tristate_n
1763_tristate_n
For De bu g For DebugFor DebugFor Debug
LD12
hswap
10K
R49 10K
R50
10K
R51
10KR52 10KR53 10KR54 10KR55
10KR56 10KR57
10KR58 10KR59
10KR60
0RR62 0RR63 0RR64 0RR65
0RR66 0RR67
0RR68 0RR69
0RR70 0RR71
0RR72 0RR73
0RR74 0RR75 0RR76 0RR77
0RR78 0RR79 0RR80 0RR81
0RR82 0RR83 0RR84 0RR85
0RR90 0RR91 0RR92 0RR93
0R
R94 0RR95 0RR96 0RR97
0R
R99
0R
DNM
R98
0R
DNM
R88
0R
DNM
R89
68R
DNM R100
4.7K
R101
4.7K
R110
22RR86
22RR87
4.7K
DNM
R106
4.7KR107
0R
R109
1 20 R 0603 1/1 0W 1%_ LF
R108
100RR102 100RR103 100RR104 100RR105
L ED OR ANGE 06 03_L F
LED1
4U 7F/10V 0603 Y5V_LF
C97
1 5 PF /50V 06 03 5 %_L F
C94
PROG_B 1
IO3_L01P 2
IO3_L01N 3
IO3_L02P 4
IO3_L02N/VREF 5
IP 6
VCCAUX 7
IO3_L03P 8
IO3_L03N 9
GND 10
IO3_L04P 11
IO3_L04N 12
VCCINT 13
IP 14
IO3_L05P 15
IO3_L05N 16
GND 17
IO3_L06P 18
IO3_L06N 19
IP/VREF 20
VCCO3 21
IO3_L07P/LHCLK0 22
IO3_L07N/LHCLK1 23
IO3_L08P/LHCLK2 24
IO3_L08N/LHCLK3 25
IP 26
GND 27
IO3_L09P/LHCLK4 28
IO3_L09N/LHCLK5 29
IO3_L10P/LHCLK6 30
IO3_L10N/LHCLK7 31
IP 32
IO3_L11P 33
IO3_L11N 34
IO3_L12P 35
IO3_L12N 36
GND 37
VCCO3 38
IO3_L13P 39
IO3_L13N 40
IO3_L14P 41
IO3_L14N 42
IP 43
VCCAUX 44
IO/VREF 45
VCCO3 46
IO3_L15P 47
IO3_L15N 48
IO3_L16P 49
IO3_L16N 50
IP 51
GND 52
GND 53
IP 54
IO2_L01P/CSOB 55
IO2_L01N/INTB 56
IP2_L02P 57
IP2_L02N 58
VC CO2 59
IO2_L03P/DOUT/BUSY 60
IO2_L03N/MOSI/CSIB 61
IO2_L04P 62
IO2_L04N 63
IO2_L05P 64
IO2_L05N 65
VCCAUX 66
VCCINT 67
IO2_L06P 68
IO2_L06N 69
GND 70
IP2_L07P 71
IP2_L07N/VREF 72
VC CO2 73
IO2_L08P/D7/GCLK12 74
IO2_L08N/D6/GCLK13 75
IO/D5 76
IO2_L09P/D4/GCLK14 77
IO2_L09N/D3/GCLK15 78
GND 79
IP2_L10P/RDWRB/GCLK0 80
IP2_L10N/M2/GCLK1 81
IO2_L11P/D2/GCLK2 82
IO2_L11N/D1/GCLK3 83
IO/M1 84
GND 85
IO2_L12P/M0 86
IO2_L12N/DIN/D0 87
VC CO2 88
IO2_L13P 89
IO2_L13N 90
IP 91
VCCAUX 92
IO2_L14P/A23 93
IO2_L14N/A22 94
GND 95
IO2_L15P/A21 96
IO2_L15N/A20 97
IO2/VREF 98
IO2_L16P/VS2/A19 99
IO2_L16N/VS1/A18 100
IP 101
IO2_L17P/VS0/A17 102
IO2_L17N/CCLK 103
DONE 104
GND
105
IO1_L01P/A16
106
IO1_L01N/A15
107
IO1_L02P/A14
108
IO1_L02N/A13
109
IP
110
VCCAUX
111
IO1_L03P
112
IO1_L03N/VREF
113
VCCO1
114
IO1_L04P
115
IO1_L04N
116
VCCINT
117
IP
118
IO1_L05P/A12
119
IO1_L05N/A11
120
GND
121
IO1_L06P
122
IO1_L06N/VREF
123
IP
124
VCCO1
125
IO1_L07P/A10/RHCLK
126
IO1_L07N/A9/RHCLK1
127
IO1_L08 P/A8 /RHCLK2
128
IO1_L08N/A7/RHCLK3
129
IP
130
GND
131
IO1_L09 P/A6 /RHCLK4
132
IO1_L09N/A5/RHCLK5
133
IO1_L10 P/A4 /RHCLK6
134
IO1_L10N/A3/RHCLK7
135
IP/VREF
136
IO1_L11P/A2
137
IO1_L11N/A1
138
IO1_L12P
139
IO1_L12N/A0
140
GND
141
IP
142
VCCO1
143
IO1_L13P
144
IO1_L13N
145
IO1_L14P
146
IO1_L14N
147
IP
148
VCCAUX
149
IO1_L15P/HDC
150
IO1_L15N/LDC0
151
IO1_L16P/LDC1
152
IO1_L16N/LDC2
153
IP
154
TMS
155
GND
156
TDO
157
TC K
158
IP
159
IO0_L01P
160
IO0_L01N
161
IO0_L02P
162
IO0_L02N/VREF
163
IO0_L03P
164
IO0_L03N
165
VCCAUX
166
IO0_L04P
167
IO0_L04N/VREF
168
IP
169
VCCINT
170
IO0_L05P
171
IO0_L05N
172
GND
173
IO0_L06P
174
IO0_L06N
175
VCCO0
176
IO0_L07P/GCLK4
177
IO0_L07N/GCLK5
178
IO0/VREF
179
IO0_L08P/GCLK6
180
IO0_L08N/GCLK7
181
GND
182
IO0_L09P/GCLK8
183
IO0_L09N/GCLK9
184
IO0_L10P/GCLK10
185
IO0_L10N/GCLK11
186
IO
187
GND
188
IO0_L11P
189
IO0_L11N
190
VCCO0
191
IO0_L12P
192
IO0_L12N/VREF
193
IP
194
VCCAUX
195
IO0_L13P
196
IO0_L13N
197
GND
198
IO0_L14P
199
IO0_L14N/VREF
200
VCCO0
201
IO0_L15P
202
IO0_L15N
203
IP
204
IO0_L16P
205
IO0_L16N/HSWAP
206
TDI
207
GND
208
XC3S500E
U3
OSC
1
1
2
2
33
44
50MHz
SPXO018044
X1
1
2
HEADER1X2_LF
JP4
1
2
HEADER1X2_LF
JP5
1
2
HEADER1X2_LF
JP2
10KR48
10K
R47
1
2
3
HEADER1X3_LF
JP1
1 2
3 4
5 6
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
FD2X20_LF
J2
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
2Y1
9
GND
10 2A1 11
1Y4 12
2A2 13
1Y3 14
2A3 15
1Y2 16
2A4 17
1Y1 18
2OE 19
Vcc 20
1OE
1
SN74LVT244BPW
U4
DNM
FPGA CO NFIG
SW1
1
2
3
4
5
6
JTAG
JP3
Figure 16 FPGA
ISP1763A PCI evaluation board User manual Schematics
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
22 (29)
VDD
1
AD28
2
AD27
3
AD26
4
AD25
5
C/BE3
6
IDSEL
7
AD24
8
AD23
9
AD22
10
AD21
11
AD20
12
AD19
13
AD18
14
AD17
15
C/BE2
16
FRAME
17
IRDY
18
VSS
19
VDD
20
TRDY
21
DEVSEL
22
STOP
23
LOCK
24
PERR
25
SERR
26
VSS
27
VDD
28
PAR
29
C/BE1
30
AD16
31
AD15
32
AD14
33
AD13
34
VDD
35
AD12
36
AD11
37
AD10
38
AD9
39
AD8
40
C/BE0
41
AD7
42
AD6
43
VSS
44
VDD
45
AD5
46
AD4
47
AD3
48
AD2
49
AD1
50
AD0
51
ENUM
52
LEDon/ LEDin
53
LA0
54
LA1
55
LA2
56
LA3
57
LA4
58
LA5
59
LA6
60
VS S
61
VDD
62
LA7
63
LA8
64
LA9
65
LA10
66
LA11
67
LA12
68
VS S
69
VDD
70
LA13
71
LA14
72
LA15
73
LA16
74
LA17
75
LA18
76
LA19
77
LA20
78
LA21
79
LA22
80
LA23
81
LA24
82
LA25
83
LA26
84
LA27
85
LA28
86
LA29
87
VS S
88
VDD 89
RD/WR 90
TSIZ1 91
TSIZ0 92
LA30 93
LA31 94
LD0 95
LD1 96
LD2 97
LD3 98
VDD 99
LD4 100
LD5 101
LD6 102
LD7 103
LD8 104
LD9 105
LD10 106
LD11 107
VSS 108
VDD 109
LD12 110
LD13 111
LD14 112
LD15 113
LD16 114
VSS 115
VDD 116
LD17 117
LD18 118
LD19 119
LD20 120
LD21 121
LD22 122
LD23 123
LD24 124
LD25 125
LD26 126
LD27 127
LD28 128
LD29 129
LD30 130
LD31 131
VSS 132
VDD 133
BI/BTERM 134
TA 135
DP0 136
DP1 137
DP2 138
DP3 139
VS S 140
VDD 141
LCLK 142
BR/LHOLD 143
BG 144
TS/ADS 145
TEA 146
VDD 147
BURST/BLAST 148
RE TRY /BR EQo 149
BB/BREQi 150
BDIP 151
LR ESE To 152
MDREQ/DMPAF/EOT 153
LIN T 154
TEST 155
MODE0 156
MODE1 157
USERo/DREQo/LLOC Ko 158
USERi/DACK0/LLOC Ki 159
CCS 160
VS S 161
VDD 162
BIGEND/WAIT 163
EECS 164
EESK 165
EEDI/ EEDO 166
PME 167
INTA 168
RST 169
PCLK 170
GNT 171
REQ 172
AD31 173
AD30 174
AD29 175
VS S 176
PCI9054
U2
V3V3
LREADY#
LREADY#
V3V3
LC LK
LHOLD
ADS#
LSERR#
V3V3
BLAST#
V3V3
LRESET#
LINT#
V3V3
DREQ0#
DACK0#
V3V3
EECS
EESK
EEDI
PME#
INTA#
RST#
PCICLK
GNT#
REQ#
AD31
AD30
AD29
V3V3
V3V3 V3V3
V3V3
V3V3
V3V3
V3V3
TSIZ1
TSIZ0
V3V3
V3V3
V3V3
AD28
AD27
AD26
AD25
C/BE3#
IDSEL
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
C/BE2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
LOCK#
PERR#
SERR#
PAR
C/BE1#
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
C/BE0#
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
LA[31.. 16]
LD[15..0]
CS
1
SK
2
DI
3
DO
4GND 5
ORG 6
NC 7
VCC 8
u93LC56C
U1
V3V3
V3V3
V3V3
EEDI
EESK
EECS
V3V3
LCLK
LHOLD
LHOLDA
ADS#
LSERR#
BLAST#
LRESET#
LINT#
TEST
LA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
LA24
LA25
LA26
LA27
LA28
LA29
LD15
LD14
LD13
LD12
LD11
LD10
LD9
LD8
LD7
LD6
LD5
LD4
LD3
LD2
LD1
LD0
LA31
LA30
TSIZ0
TSIZ1
LW/R#
TRST A1
+12V A2
TMS A3
TDI A4
+5V A5
INTA A6
INTC A7
+5V A8
RESERVED A9
VIO A10
RESERVED A11
3V3_AUX A14
RST A15
VIO A16
GNT A17
GND A18
PME A19
AD30 A20
3V3 A21
AD28 A22
AD26 A23
GND A24
AD24 A25
IDSEL A26
3V3 A27
AD22 A28
AD20 A29
GND A30
AD18 A31
AD16 A32
3V3 A33
FRAME A34
GND A35
TRDY A36
GND A37
STOP A38
3V3 A39
RESERVED A40
RESERVED A41
GND A42
PAR A43
AD15 A44
3V3 A45
AD13 A46
AD11 A47
GND A48
AD9 A49
C/BE0 A52
3V3 A53
AD6 A54
AD4 A55
GND A56
AD2 A57
AD0 A58
VIO A59
REQ64 A60
+5V A61
+5V A62
-12V
B1
TCK
B2
GND
B3
TDO
B4
+5V
B5
+5V
B6
INTB
B7
INTD
B8
PRSNT1
B9
RESERVED
B10
PRSNT2
B11
RESERVED
B14
GND
B15
CLK
B16
GND
B17
REQ
B18
VIO
B19
AD31
B20
AD29
B21
GND
B22
AD27
B23
AD25
B24
3V3
B25
C/BE3
B26
AD23
B27
GND
B28
AD21
B29
AD19
B30
3V3
B31
AD17
B32
C/BE2
B33
GND
B34
IRDY
B35
3V3
B36
DEVSEL
B37
GND
B38
LOCK
B39
PERR
B40
3V3
B41
SERR
B42
3V3
B43
C/BE1
B44
AD14
B45
GND
B46
AD12
B47
AD10
B48
M66EN
B49
AD8
B52
AD7
B53
3V3
B54
AD5
B55
AD3
B56
GND
B57
AD1
B58
VIO
B59
ACK64
B60
+5V
B61
+5V
B62
CON1
V5V0_PCI
PCICLK
AD31
AD29
AD27
AD25
V3V3_PCI C/BE3#
AD23
AD21
AD19
AD17
C/BE2#
IRDY#
DEVSEL#
LOCK#
PERR#
SERR#
C/BE1#
AD14
AD12
AD10
AD8
AD7
AD5
AD3
AD1
C/BE0#
AD6
AD4
AD2
AD0
RST#
GNT#
PME#
AD30
AD28
AD26
AD24
IDSEL
AD22
AD20
AD18
AD16
FRAME#
TRDY#
STOP#
PAR
AD15
AD13
AD11
AD9
INTA# V3V3
GND
V3V3
GND
V3V3
GND
V3V3
GND
V3V3
GND
V3V3
GND
V3V3
V3V3
V3V3
GND
GND
V3V3
GND
V3V3
V3V3
GND
V3V3
V3V3
GND
GND
V3V3
TEST
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
REQ#
x86 Mo de
V3V3
V3V3
V3V3
LCLK
V3V3
TS IZ0
V3V3
TS IZ1
V3V3
LW /R #
V3V3
ADS#
V3V3
LS ERR#
V3V3
LR EA DY#
V3V3
LIN T#
V3V3
BLAST#
LHOLD
LHOLDA
100nF/50V
C1
10nF/50V
C2
100nF/50V
C3
10nF/50V
C4
100nF/50V
C5
10nF/50V
C6
100nF/50V
C7
10 NF/50V 06 03 10%_LF
C8
100nF/50V
C9
10 NF/50V 06 03 10%_LF
C10
100nF/50V
C11
10 NF/50V 06 03 10%_LF
C12
100nF/50V
C13
10 NF/50V 06 03 10%_LF
C14
100nF/50V
C15
10 NF/50V 06 03 10%_LF
C16
100nF/50V
C17
10 NF/50V 06 03 10%_LF
C18
100nF/50V
C19
10 NF/50V 06 03 10%_LF
C20
100nF/50V
C21
10 NF/50V 06 03 10%_LF
C22
100nF/50V
C23
10 NF/50V 06 03 10%_LF
C24
100nF/50V
C25
10 NF/50V 06 03 10%_LF
C26
100nF/50V
C27
10 NF/50V 06 03 10%_LF
C28
100nF/50V
C29
10 NF/50V 06 03 10%_LF
C30
10KR4
10K
R22
V3V3
LW/R#
LHOLDA
DREQ0#
DACK0#
DREQ0#
DACK0#
LD8
LD9
LD12
LD14
LD15
LD13
LD7
LD6
LD10
LD11
LD5
LD0
LD1
LD2
LD3
LD4
LW/R#
ADS#
BLAST#
BLAST#
ADS#
LW/R#
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
TEST
TEST note: TEST should be 0
V3V3
V5V0_PCI
V5V0_PCI
V5V0_PCI V5V0_PCI
V3V3_PCI
V3V3_PCI
V3V3_PCI
V3V3_PCI
V3V3_PCI V3V3_PCI
V3V3_PCI
V3V3_PCI
V3V3_PCI
V3V3_PCI
V3V3_PCI
1
MECHOLE
MH2
1
MECHOLE
MH1
LA17
LA16
LA26
LA31
LA30
LA29
LA28
LA27
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LD8
LD9
LD12
LD14
LD15
LD13
LD7
LD6
LD10
LD11
LD5
LD0
LD1
LD2
LD3
LD4
Female socket to attach test probe
LRESET#
LW/R#
ADS#
BLAST#
LINT#
LSERR#
LREADY#
LHOLD
LHOLDA
BLAST#
ADS#
LW/R# LHOLDA
LRESET#
LINT#
LSERR#
LA31
LA30
LA29
LA28
LA27
LA26
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LA17
LA16
LD0
LD1
LD2
LD3
LD4
LD5
LD6
LD7
LD8
LD9
LD10
LD11
LD12
LD13
LD14
LD15
LREADY#
LHOLD
Adapter bo ard pin number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
Ad a pter bo ard pin n umbe r
DNM
33
34
35
DNM
DNM
DNM
32
31
30
29
28
27
26
25
24
23
22
21
20
0RR1 0RR2 0RR3 0RR24
10KR5 10KR6 10KR7
10KR10
10KR11 10KR12
10KR18
10K
R19
10KR20 10KR21
10K
R23
10K
R31
10K
R28
10K
R29
10K
R32
10K
R27
10K
R30
10K
R33
10K
R44
0R
R45 0R
R46
10KR43 10KR42
10K
R40
10K
R41
10K
R34
10K
R35
0R
DNM
R38
0RR39
1KR8 1KR9
1KR14 1KR15 1KR16 1KR17
1K
DNM
R36
1K
R37
1KR25
1KR26
510RR13
0.1uF
C31
100PF/50V 0603 5%_LF
C32
12
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
43
42
41
40
39
767130-1
J1
TPGNT#1
TPREQ#1
LA17
LA16
LA26
LA31
LA30
LA29
LA28
LA27
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LA31
LA30
LA29
LA28
LA27
LA26
LA25
LA24
LA23
LA22
LA21
LA20
LA19
LA18
LA17
LA16
LRESET#
LINT#
LSERR#
LRESET#
LINT#
LSERR#
LREADY#
LHOLD
LHOLDA LHOLDA
LREADY#
LHOLD
Figure 17 PCI
ISP1763A PCI evaluation board User manual Schematics
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
23 (29)
DC POWER SOCKET 2 .5M M DIA
12V IN THE CENTRE
AND GND ON THE SHEILD
GND
GND
1
2
3
DC P OWE R SOCKET
2.5MM DIA
PS2
100nF/50VC121
100nF/50V
C122
PC5V
CDRH104RNP-7R0NC
L1
Take care t he o rientation
of this connector
1 0 0 NF / 50V 06 0 3 1 0 % _LF
C125
1 0 0 NF / 50V 06 0 3 1 0 % _LF
C126
TP7
TP6
VCC(3V3)_Chip
V5V0
PC I pow e r
mai n power
Vref=1.25v
+5V_usb_Chip
V12V0_ext
V5V0_PCI
V5V0
V5V0
V3V3
V5V0 V1V2
1
Vin
3
Tab 4
Vout 2
GND
LD1117S12TR
U14
TP9 TP10
V5V0 V2V5
TP11 V1V8V5V0
TP12
V5V0
V5V0 V3V3
Super Pure Green
LED GREEN 0603, SML312ECT
LED7
TP13
V3V3_PCI
V3V3
V1V8
TP8
VIO
VCC(IO)_Chip
DL_P
DL_P
GND
0R
DNM
R139
0R
R140
+
10uF/25V
C120
100nF/50V
C123
10R
R142 0R
R145
0R
R146
0RR149
0RR150
LED BLUE 0603_LF
LED4
200R 060 3 1/16 W 1%_ LF
R144
10K
DNM
R143
33K
DNM
R141
+
10uF/25V
C127 +
10uF/25V
C128
+
10uF/25V
C131 +
10uF/25V
C132
240R 0603 1/8W 1%_L F
R151
51R 0603 1/16W 1% _LF
R152
LED YELLOW 0603_LF
LED6
+10uF/25V
C134
0RR153
0R
DNM R148
33R 0603 1/16W 1% _LF
R154
+
2 2 UF / 25V 20 % TAN- D_LF
C133
+
10uF/25V
C129 +10uF/25V
C130
LED RED 0603_LF
LED5
3 R 06 03 1/1 0W 1% _L F
R147
1
2
3
4
DP04PR
PS1
VL
1REF
2
FB
3
OUT
4SHDN
5
VP 10
DH 9
CS 8
DL 7
GND 6
MAX1791EUB+
U12 S1
1
G1
2
S2
3
G2
4D2 5
D2 6
D1 7
D1 8
FDS8958A
U13
1
2
3
HEADER1X3_LF
JP6
1
2
3
HEADER1X3_LF
JP7
IN
3OUT 2
GND
1
LD1086D2T25TR
U15
IN
3OUT 2
GND
1
LD1086D2T18TR
U16
GND
1
OUT 2
IN
3LD1086D2T33TR
U17
+
220uF/10V
C124
BYG22D
PD1
Figure 18 Power
ISP1763A PCI evaluation board User manual Schematics
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
24 (29)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
WE#
RD#
ALE_1
ALE_1
ALE
NOR Flash
BSQUARE PXA320 SRAM INTERFACE
DACK#
DREQ
IRQ
VCC(IO)_Chip
ALE
D0
D2
D4
D6
D8
D10
D14
D12
IRQ
RD#
D15
D13
D11
D9
D7
D5
D3
D1
CS#
RESET#
CLE
WE#
S amte c con n ect or
CONN,SMT,VERTICAL,PLUG,35X2 FM-135-32-S-D-A
CS#
RESET#
RESET#
RESET#
DAVINCI DM357 NAND INTERFACE
C O NN, 0.5 0"SQ Sh r oude d H ead er, S MT , 100pin. 0.465" BTB
0R
DNM
R155
0R
DNM
R158
0R
DNM
R162
0R
DNM
R161
0R
DNM
R164 0R
DNM
R163
0R
DNM
R165
0R
DNM
R166 0R
DNM
R167
0R
DNM
R168
2K 0603 1/10W 1%_LF
R156
3K 0603 1/16W 1%_LF
R157
3V3
1GND 2
3V3
3GND 4
D0_BUF
5GND 6
D1_BUF
7GND 8
D2_BUF
9GND 10
D3_BUF
11 GND 12
D4_BUF
13 GND 14
D5_BUF
15 GND 16
D6_BUF
17 GND 18
D7_BUF
19 GND 20
D8_BUF
21 GND 22
D9_BUF
23 GND 24
D10_BUF
25 GND 26
D11_BUF
27 GND 28
D12_BUF
29 GND 30
D13_BUF
31 GND 32
D14_BUF
33 GND 34
D15_BUF
35 GND 36
NONMUX_A0_BUF
37 FLASH_HDR_nCS2 38
NONMUX_A1_BUF
39 FLASH_HDR_nCS3_63MB 40
NONMUX_A2_BUF
41 SCLK_BUF 42
NONMUX_A3_BUF
43 nLLA 44
A0_BUF
45 TP26 46
A1_BUF
47 nBE0 48
A2_BUF
49 nBE1 50
A3_BUF
51 TP25 52
A4_BUF
53 PC_BVD1 54
A5_BUF
55 PC_nCD 56
A6_BUF
57 nXCVREN 58
A7_BUF
59 nPWAIT 60
A8_BUF
61 nIOIS16 62
A9_BUF
63 RDnWR 64
A10_BUF
65 nPCE1 66
A11_BUF
67 nPCE2 68
A12_BUF
69 nPIOW 70
A13_BUF
71 ALE_nWE 72
A14_BUF
73 nPREG 74
A15_BUF
75 nPIOR 76
A16_BUF
77 CLE_nOE 78
A17_BUF
79 FLASH_HDR_nIRQ 80
A18_BUF
81 FLASH_HDR_RESET 82
A19_BUF
83 GPIO_OUT5 84
A20_BUF
85 GPIO_IN5 86
A21_BUF
87 I2 C _S CL 88
A22_BUF
89 I2C_SDA 90
A23_BUF
91 PER_nRESET 92
A24_BUF
93 nRESET_OUT 94
TP27
95 FLASH_HDR_RDY 96
3V3
97 GND 98
3V3
99 GND 100
SFM-150-02-S-D-A
CN1
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
65
67
67
69
69
22
44
66
88
10 10
12 12
14 14
16 16
18 18
20 20
22 22
24 24
26 26
28 28
30 30
32 32
70 70
68 68
66 66
64 64
62 62
60 60
58 58
34 34
36 36
38 38
40 40
42 42
44 44
46 46
48 48
50 50
52 52
54 54
56 56
TFM-135-32-S-D-A
DC1
10K
R159
0R
DNM
R160
T
Figure 19 Connectors
ISP1763A PCI evaluation board User manual List of materials
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
25 (29)
5 List of materials
Table 7 List of materials
Part type Designator Footprint Description
0 R80, R81, R83, R82, R77, R76, R79, R78,
R93, R92, R95, R94, R85, R84, R91, R90,
R75, R64, R63, R66, R65, R39, R38, R62,
R61, R72, R71, R74, R73, R68, R67, R70,
R69, R155, R148, R162, R158, R149,
R146, R153, R150, R167, R166, R160,
R168, R164, R161, R165, R163, R145,
R89, R88, R123, R109, R97, R96, R98,
R99, R138, R126, R140, R139, R133,
R124, R132, R134, R3, R2, R1, R45, R46,
R24
R0603 Resistor SMD 0603 1/16W
1% 0 , lead free
1 k R25, R37, R26, R9, R8, R14, R15, R16,
R36, R17
R0603 Resistor SMD 0603 1/10W
1% 1 k lead free
2 k R156 R0603 Resistor SMD 0603 1/10W
1% 2 k, lead free
3 k R157 R0603 Resistor SMD 0603 1/16W
1% 3 k, lead free
3 R147 R0603 Resistor SMD 0603 1/10W
1% 3 , lead free
4.7 k R107, R110, R106, R101 R0603 Resistor SMD 0603 1/10W
1% 4K7 lead free
4.7 µF C108, C112 TAN SMD-A Capacitor tan SMD-A
4u7F/10 V +/-20%, lead free
4.7 µF C96, C97 C0603 Capacitor SMD 0603
4u7F/10 V Y5V +80%-20%,
lead free
4.7 µF C117 ELE SMD-B Capacitor Ele SMD-B
4u7F/35 V +/-20%, lead free
10 k R59, R60, R57, R56, R58, R43, R118,
R44, R130, R49, R47, R117, R55, R111,
R42, R121, R113, R50, R114, R112, R52,
R53, R54, R51, R119, R122, R120, R6,
R7, R143, R5, R12, R135, R10, R11, R41,
R40, R34, R35, R159, R48, R4, R22, R32,
R27, R28, R29, R131, R33, R127, R30,
R18, R19, R129, R128, R23, R31, R20,
R21
C0603 Resistor SMD 0603 1/16W
1% 10 k lead free
10 nF C80, C75, C70, C104, C42, C37, C65,
C45, C40, C35, C60, C55, C50, C102,
C82, C77, C72, C106, C98, C100,C52,
C47, C57, C67, C62, C24, C12, C14, C26,
C10, C30, C28, C8, C4, C2,C22, C20, C6,
C16, C18
C0603 Capacitor SMD 0603
10 nF/50 V 10% X7R
ISP1763A PCI evaluation board User manual List of materials
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
26 (29)
Part type Designator Footprint Description
10 R147 C0603 Resistor SMD 0603 1/16W
1% 10 , lead free
10 µF C128, C130, C120, C127, C129, C134,
C132, C131
ELE SMD-B Capacitor Ele SMD-B
10uF/25 V +/-20%, lead free
12 k R115, R116 C0603 Resistor SMD 0603 1/16W
1% 12 k, lead free
15 pF C94 C0603 Capacitor SMD 0603
15 pF/50 V 5%, lead free
18 pF C110, C111 C0603 Capacitor SMD 0603 18 pF /
50 V 5%
22 R86, R87 C0603 Resistor SMD 0603 1/16W
1% 22 , lead free
22 µF C133 TAN SMD-D Capacitor tan SMD-D
22 µF/25 V +/-20%, lead free
33 k R141 C0603 Resistor SMD 0603 1/16W
1% 33 k, lead free
33 R154 C0603 Resistor SMD 0603 1/16W
1% 33 lead free
51 R152 C0603 Resistor SMD 0603 1/16W
1% 51 , lead free
68 R100 C0603 Resistor SMD 0603 1/16W
1% 68
100 k R136 C0603 Resistor SMD 0603 1/10W
1% 100 k lead free
100 nF C61, C23, C51, C21, C15, C56, C66, C49,
C59, C76, C58, C71, C68, C63, C46, C19,
C34, C44, C36, C64, C41, C39, C11, C73,
C69, C74, C13, C78, C79, C33, C38, C5,
C7, C48, C53, C9, C43, C17, C54, C25,
C31, C29, C3, C1, C27, C95, C81, C87,
C88, C83, C85, C86, C92, C84, C93, C89,
C90, C91
C0603 Capacitor SMD 0603
100 nF/50 V +80-20%, lead
free
100 nF C126, C125, C121, C122, C115, C118,
C101, C103, C107, C99, C105, C123,
C116, C113, C109
C0603 Capacitor SMD 0603
100 nF/50 V 10%, lead free
100 pF C32 C0603 Capacitor SMD 0603
100 pF/50 V 5% NPO
100 R103, R102, R105, R104 C0603 Resistor SMD 0603 1/10W
1% 100 lead free
100 µF C114 ELE SMD-D Capacitor Ele SMD-D
100 µF/16 V 20%, lead free
120 R108 C0603 Resistor SMD 0603 1/10W
1% 120 lead free
200 R144 C0603 Resistor SMD 0603 1/16W
1% 200 , lead free
220 µF C124 ELE SMD-E Capacitor Ele SMD
220 µF/10 V FK series, low
ESR, +/-20%, lead free
ISP1763A PCI evaluation board User manual List of materials
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
27 (29)
Part type Designator Footprint Description
240 R151 C0603 Resistor SMD 0603 1/8W 1%
240 , lead free
510 R13 C0603 Resistor SMD 0603 1/10W
1% 510 lead free
560 R125, R137 C0603 Resistor SMD 0603 1/16W
1% 560 , lead free
767130-1 J1 767130-1 Connector recept 38Pos
0.025CL 767130-1
B3S-1000 SW1 B3S-1000 Switch tact SMD
6 mm x 6 mm white
BLM31A260S FB1, FB2 R1206 Murata ferrite bead, 1206
case, 0.05 DC resistance
CDRH104RNP-
7R0NC
L1 CDRH104RNP Inductor SMD 7 µH/4.5 A
DR1040-7R0-R
CS10 12.000MABJ-
UT
X2 CS10 Crystal 12 MHz 6 x 3.5 mm
CS10-12.000MABJ-UT
DC power socket
2.5 mm DIA
PS2 DC power socket Socket DC jack 2.5 mm PCB
Mt
DP04PR PS1 DP04PR Power disk drive RA 4-way
FD2X20_LF J2 FD2X20 Connector PCB Mt 0.100"
2 x 20-way
FDS8958A U13 SOIC-8_4 x 5 mm Transistor FDS8958A NP SO-
8
Header1 x 2_LF JP2, JP4, JP5 Header1 x 2 Header pin 0.100" 1 x 2-way
gold, lead free
Header1 x 3_LF JP1, JP6, JP7 Header1 x 3 Header pin 0.100" 1 x 3-way
gold, lead free
Header1 x 6_LF JP3 Header1 x 6 Header pin 0.100" 1 x 6-way
gold, lead free
Header2 x 8_LF J3, J4, J5, J6 Header2 x 8 Header pin 0.100" 2 x 8-way
gold, lead free
ISP1763 VFQFPN U6 VFQFPN-64 -
LD1086D2T18TR U16 D2PAK IC reg LDO POS 1.8 V 1.5 A
D2PAK
LD1086D2T25TR U15 D2PAK IC reg LDO POS 2.5 V 1.5 A
D2PAK
LD1086D2T33TR U17 D2PAK IC reg LDO positive 3.3 V
D2PAK
LD1117S12TR U14 SOT-223 IC reg LDO POS 800MA
1.2 V SOT223
LED blue 0603_LF LED4 LED0603 LED blue 0603
LED green 0603,
SML312ECT
LED7 LED0603 Chip LED, green, SMD, 0603
package, 0.8 x 1.6 x 0.8 mm
LED orange
0603_LF
LED1 LED0603 LED orange 0603
LED red 3MM_LF LED2, LED3 LED3mm LED 3 mm red diffused
LED red 0603_LF LED5 LED0603 LED red 0603
ISP1763A PCI evaluation board User manual List of materials
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
28 (29)
Part type Designator Footprint Description
LED yellow
0603_LF
LED6 LED0603 LED yellow 0603
MAX1791EUB+ U12 MSOP-10_3 x 3 mm IC MAX1791EUB+
MIC2026-2 U8 SOIC-8_4 x 5 mm IC MIC2026-2YM
PCI9054 U2 F-QFP176/P.5N -
SFM-150-02-S-D-A CN1 SFM-150-02-S-D-A Connector SMT 0.5" 2x50
SFM-150-02-S-D-A
SMB PCB VERT S1 SMB SMB jack 50 PCB Mt ST
SN74LVT244BPW U4 TSSOP20_4.4 x 6.5
mm
IC 74LVT244BPW 20-TSSOP
SPXO018044 X1 SPXO018044 Oscillator 50.000 MHz
HCMOS 3.3 V 1/2 size
Test point 1.8 TPREQ#1, TPGNT#1, TP11, TP12, TP13,
TP10, TP7, TP6, TP9, TP4, TP1, TP2,
TP3, TP8, TP5
TP18 Test point
TFM-135-32-S-D-A DC1 TFM-135-32-S-D-A Samtec connector SMT,
vertical, plug, 35 x 2, TFM-
135-32-S-D-A
USB con type A
receptacle
S2 USB_A USB type A RA 4-way 87520-
0010B
USBULC6-2F3 U7, U9, U10, U11 USBULC6-2F3 ESD protection diode
USB_AB_MICRO S3 USB micro type AB Micro USB type AB SMD R/A
ZX62-AB-5P
XC3S500E U3 PQ208 IC Spartan XC3S500E-
4PQG208C PQFP
XCF04S U5 TSSOP20_4.4 x 6.5
mm
IC programmable
XCF04SVOG20C 20-TSSOP
u93LC56C U1 DIP8 IC 93LC56C-I/P, EEPROM
DIP-8, lead free
ISP1763A PCI evaluation board User manual Glossary
UM0865
CD00257207 Rev 2 2010-04-05 ISP1763A
© Copyright ST-Ericsson, 2010. All rights reserved.
29 (29)
Glossary
EEPROM Electrically Erasable
Programmable Read-Only
Memory
FPGA Field-Programmable Gate
Array
NAND Not AND
NOR Nor OR
OS Operating System
OTG On-The-Go
PCI Peripheral Component
Interconnect
PIO Parallel Input/Output
RAM Random-Access Memory
SRAM Static Random Access
Memory
USB Universal Serial Bus
