3 Volt Fast Boot Block Flash Memory
28F800F3 and 28F160F3
Product Features
Intel® 3 Volt Fast Boot Block Flash memory offers the highest performance synchronous burst
reads—making it an ideal memory solutio n for burst CPUs. The Intel 3 Volt Fast Boo t Blo c k
Flash memory also supports asynchronous page mode operation for non-clocked memory
subs ystems. Com bining high read performance with the intrinsic nonvolatility of flas h memory
eliminates the traditional redundant memory paradigm of shadowing code from a slower
nonvolatile storag e source to a faster execution memory device, (e.g., SRAM SDRAM), for
improved system per formance. By adding 3 Volt Fast Boot Bl ock Flash memory to yo ur sy st em
you could reduce the total memo ry requ irement, which helps increase reliability and redu ce
overall system power consumption—all while reducing system cost.
This family of products is manufactured on Intel® 0.4 µm ETOX™ V pro cess techno logy. They
are available in a wide variety of industry-standard packaging technologies.
■High Performance
—Up to 60 MHz Eff ective Zero Wait-State
Performance
—Synchronous Burst-Mode Reads
—Asynchro nou s Pag e-Mode Reads
■SmartVoltage Technology
—2.7V−3.6 V Read and Write Operation s
for Low Power Designs
—12V VPP Fast Factory Programming
■Flexibl e I/O Voltage
—1.65 V I/O Reduces Overall System
Power Consumption
■5 V-Safe I/O Enables Interfacing to
5 V Devices
■Enhanced Data Protection
—Abs olute Write Protection w ith
VPP = GND
—Block Locking
—Block Erase/Program Lockout during
Power Transitions
■Density Upgrade Path
—8 and 16 Mbit
■Manufactured on ETOX™ V Flash
Technology
■Support s Cod e Plus Data Storag e
—Optimized for Intel® Flash Data
Integrator (IFDI) and other Intel®
Software
—Fast Program Suspend Capa bility
—Fast Erase Susp end Capability
■Flexible Blocking Architecture
—Eight 4-Kword Blocks for Data
—32-Kword Main Blocks for Code
—Top or Bottom Boot Config urations
■Extended Cycling Capability
—Minimum 100,000 Block Erase Cycles
■Low Power Consumption
—Automatic Power Savings Mode
Decreases Power Consumption
■Automated Program and Block Erase
Algorithms
—Command User Interface for
Automation
—Status Register for System Feedback
■Industry-Standard Packaging
—56-Lead SSOP
—56-Lead TSOP
—µBGA* CSP
—Intel® Easy BGA
Order Number: 290644-005
January 2000
Notice: This document contains information on products in full production. The specifications
are subject to change without notice. V erify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability , or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F800F3 and 28F160F3 may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation 1998–2000
*Other brands and names are the property of their respective owners.
iii
28F800F3 and 28F160F3
Contents
1.0 Introduction..................................................................................................................1
1.1 Product Overview..................................................................................................1
2.0 Product Description..................................................................................................2
2.1 Pinouts ..................................................................................................................2
2.2 Pin Description......................................................................................................2
2.3 Memory Blocking Organization .............................................................................7
2.3.1 Parameter Blocks.....................................................................................7
2.3.2 Main Blocks..............................................................................................7
3.0 Principles of Operation..........................................................................................10
3.1 Bus Operations....................................................................................................10
3.1.1 Read.......................................................................................................10
3.1.2 Output Disable........................................................................................10
3.1.3 Standby..................................................................................................11
3.1.4 Write.......................................................................................................11
3.1.5 Reset......................................................................................................11
4.0 Command Definitions.............................................................................................12
4.1 Read Array Command.........................................................................................13
4.2 Read Identifier Codes Command........................................................................13
4.3 Read Status Register Command.........................................................................14
4.4 Clear Status Register Command.........................................................................14
4.5 Block Erase Command........................................................................................14
4.6 Program Command............ ...... ....... ...... ...... ....... ...... ....... ...... ....... ................... ....15
4.7 Block Erase Suspend/Resume Command..........................................................16
4.8 Program Suspe nd/ Res ume Comman d .............. ................... .................... ...... ....16
4.9 Set Read Configuration Command .....................................................................17
4.9.1 Read Configuration – (RCR.15) .............................................................18
4.9.2 Frequency Configuration Code Setting (FCC) – (RCR.13-11)...............18
4.9.3 Data Output Configuration – (RCR.9) ....................................................20
4.9.4 Wait # Configuration – (RCR.8)..............................................................21
4.9.5 Burst Sequence – (RCR.7).....................................................................21
4.9.6 Clock Configuration – (RCR.6)...............................................................22
4.9.7 Burst Length – (RCR.2—0)....................................................................22
4.9.8 Continuou s Burs t Lengt h................ ....... ................... .................... ...... ....2 2
5.0 Data Protection.........................................................................................................27
5.1 VPP ≤ VPPLK for Complete Protection..................................................................27
5.2 WP# = VIL for Block Locking ...............................................................................27
5.3 WP# = VIH for Block Unlocking ...........................................................................27
28F800F3 and 28F160F3
iv
6.0 VPP Voltages...............................................................................................................28
7.0 P ower Consumption...............................................................................................28
7.1 Active Power .......................................................................................................28
7.2 Automatic Power Savings ...................................................................................28
7.3 Standby Power....................................................................................................28
7.4 Power-Up/Down Operation.................................................................................29
7.4.1 RST# Connec tio n........... ....... ...... ................... .................... ...... ..............29
7.4.2 VCC, VPP and RST# Transitions.............................................................29
7.5 Power Supply Decoupling...................................................................................29
7.5.1 VPP Trace on Printed Circuit Boards......................................................30
8.0 Electrical Specifications........................................................................................30
8.1 Absolute Maximum Ratings ................................................................................30
8.2 Extended Temperature Operating Conditions.....................................................31
8.3 Capacitance........................................................................................................31
8.4 DC Characteristics—Extended Temperature......................................................32
8.5 AC Characteristics—Read-Only Operations—Extended Temperature...............35
8.6 AC Characteristics—Write Operations—Extended Temperature .......................41
8.7 AC Characteristics—Reset Operation—Extended Temperature ........................43
8.8 Extended Temperature Block Erase and Program Performance........................44
9.0 Ordering Infor mat ion..............................................................................................45
10.0 Additional Information...........................................................................................46
v
28F800F3 and 28F160F3
Revision History
Date of
Revision Version Description
05/12/98 -001 Original version
11/ 15/98 -002 Minor text modifications
Revised Page mode read waveform
Revised Single synchronous read waveform
Improved automotive specifications
Changed name from
Fast Boot Block Flash Memory Family 8 and
16 Mbit
.
03/22/99 -003 Added Easy BGA pinout graphic
Added TSOP and Easy BGA part number nomenclature
09/17/99 -004 Minor text modifications
Revised Figure 1,
8x8 Easy BGA Package Ballout
Revised Section 4.9.2,
Frequency Configuration
Added Figure 7,
Data Output with FCC Setting at Code 3
Revised Figure 12,
Block Erase Suspend/Resume Flowchart
Revised tELCH, and tCHQX Specification
Added tEHEL Specification
01/12/2000 -005 Corrected TSOP Pinout Diagram
Corrected Frequency Configuration Settings Table
Added ICCES and ICCWS spec ifications
Increased tELCH and tCHQV
28F800F3 and 28F160F3
1
1.0 Introduction
This datasheet contains 8- and 16-Mbit 3 Volt Intel® Fast Boot Block Flash memory information.
Section 1.0 provides a flash memory overview. Sections 2.0 through 8.0 describe the memory
functionality and electrical specifications for extended temperature product offerings.
1.1 Product Overview
The 3 Volt F as t Bo ot B l ock Fl as h m e mory p r ov id es densit y u pgrades wit h p i nou t compatibility for
8- and 16 -Mbit dens ities . This fa mily o f prod ucts is a hi gh-per for mance, lo w-vol tage memory with
a 16-bit data bus and individually erasable blocks. These blocks are optimally-sized for code and
data storage. Eight 4-Kword parameter blocks are positioned at either the top (denoted by -T
suffix) or bottom (denoted by -B suffix) of the address map. The rest of the device is grouped into
32-Kword main blocks. The upp er two (or lower two ) parameter bl ocks can be locked (WP # = VIL)
for complete code protection.
The device’s optimized architecture and interface dramatically increase read performance beyond
previously attainable levels. It supports synchronous burst reads and asynchronous page-mode
reads from main blocks (parameter blocks support single synchronous and asynchronous reads).
Upon initial power-up or return from reset, the main blocks of the de vice default to a page-mod e
read configuration. Page-mode read configuration is ideal for non-clocked memory systems and is
compatible with page-mode ROM. Synchronous burst reads are enabled by configuring the read
configuration register using the standard two-bus-cycle algorithm. In synchronous burst mode, the
CLK input increments an internal burst address generator, synchro nizes the flash memory with the
host CPU, and outputs dat a on every ri s ing (or falling) CLK edge up to 60 MHz. An out put si gnal ,
WAIT#, is also p rovided t o ease CPU-to-f lash memory communicati on and synch ronization dur ing
continuous burst operations that are not initiated on a four-word boundary.
In addition to the enhanced architecture and optimized interface, this family of products
incorporates SmartVoltage technology which enables fast 12 Volt factory programming and 2.7 V–
3.6 V in system programming for low power designs. Specifically designed for low-voltage
systems, 3 Volt Fast Boot Block Flash memory components support read operations at 2.7 V–3.6 V
(3.0 V–3.6 V for automotive temperature) VCC and block erase and program operations at 2.7 V–
3.6 V (3.0 V–3.6 V for automotive temperature) and 12 V VPP. The 12 V VPP option renders the
fastest program performance to increase factory programming throughput. With the 2.7 V –3.6 V
(3.0 V–3.6 V for automotive temperature) VPP option, VCC and VPP can be tied together for a
simple, low power design. In addition to the voltage flexibility, the ded icated VPP pin gives
complete data protection when VPP ≤ VPPLK.
The flexible input/output (I/O) voltage feature of the device helps reduce system power
consumption and simplifies interfacing to sub 2.7 V CPUs. Powered by the VCCQ pins, the I/O
buff e rs can op erat e indep e nde nt ly of th e core voltage. The F lexi ble I/ O ri ng of th e devi ce wo rks in
three modes:
1. With VCCQ voltage at 1.65 V, the I/Os can s win g b etween GND and 1.65 V, reducing I/O po wer
consumption by 65% over standard 3 V flash memory components.
2. W ith VCC and VCCQ at 2.7 V–3. 6V the device is an ideal fit for singl e supply vol tage, low power ,
and battery-powered applications.
3. The 5 V-safe feature allows easy interface to 5 V I/O systems by tolerating 5 V CMOS input
levels. This he lps ease CPU interfacing by adapting to CPU’s bus voltag e without using
buffers or level shifters.
28F800F3 and 28F160F3
2
The device’s Command User Interface (CUI) serves as the interface between the system processor
and internal flash memory operation. A valid com mand seque nce written to the CUI initiates
device automation. T his automation is contro lled by an internal W rite S tate Machine (WSM) which
automatically executes the algorithms and timings necessary for block erase and program
operations. The status register provides WSM feedback by signifying block erase or program
completion and status.
Block erase and program automation allows erase and program operations to be executed using an
industry-standard two-write command sequence. A block erase operation erases one block at a
time, and data is program med in word (16 bit) increments. The erase suspend featu re allows system
softwar e to su spend an ongo in g bl o c k eras e operati o n i n ord er t o read fr om or program data to an y
other block. The program suspend feature allows system software to suspend an ongoing program
operation in order to read from any other location.
The 3 Volt Fast Boot Block Flash memory devices offer two low-power savings features:
Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode
following the completion of a read cycle. Standby mode is initiated when the system deselects the
device by driving CE# inactive or R ST# active. RST# a lso resets the device to read array, provides
write protection, and clears the status register. Combined, these two features significantly reduce
power consumpt io n.
2.0 Product Description
This section describes the pinout and block architecture of the device family.
2.1 Pinouts
Intel 3 Volt Fast Boot Block Flash memory provides upgrade paths in each package pinout up to
the 16-Mbit density . The fam ily is available in Easy BGA, µB GA CSP, 56-lead SSOP and 56 -lead
TSOP packages. Pinouts for the 8- and 16-Mbit components are illustrated in Figure 1, Figure 2,
Figure 3 and Figure 4.
2.2 Pin Description
The pin description table describes pin usage.
28F800F3 and 28F160F3
3
EasyPin01
NOTES:
1. A20 is only valid on 32-Mbit densities and above, A21 is only valid on 64-Mbit densities and above, A22 is only
valid on 128-Mbit densities and above. All locations are populated with solder balls.
2. Shaded connections on the Top View indicate possible future upgrade address connections.
3. Reference the
Preliminary Mechanical Specification for Easy BGA Package
at the Intel® Flash Packaging
Data website, http: //developer.int el.com/design/flash/p ackdat a/index.htm, for det ailed p ackage specifications.
Figure 1. 8 x 8 Easy BGA Package Ballout
1 2 3 4 5 6 7 8
A
B
C
D
E
F
G
H
Top View - Ball Side Down Bottom View - Ball Side Up
A
1
A
6
A
18
V
PP
V
CC
GND A
10
A
15
A
2
A
17
A
19
RST# CLK A
20(1)
A
11
A
14
A
3
A
7
WP# WE# ADV# A
21(1)
A
12
A
13
A
4
A
5
DU
DQ
8
DQ
1
DQ
9
DQ
3
DQ
12
DQ
6
DU DU
CE# DQ
0
DQ
10
DQ
11
DQ
5
DQ
14
DU DU
A
0
V
SSQ
DQ
2
DQ
4
DQ
13
DQ
15
GND A
16
A
22(1)
OE# V
CCQ
V
CC
V
SSQ
DQ
7
V
CCQ
WAIT#
DU DU DU A
8
A
9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
A
15
A
10
GND V
CC
V
PP
A
18
A
6
A
1
A
14
A
11
A
20(1)
CLK RST# A
19
A
17
A
2
A
13
A
12
A
21(1)
ADV# WE# WP# A
7
A
3
A
9
A
8
DU
DU DU DQ
6
DQ
12
DQ
3
DQ
9
DQ
1
DQ
8
DU DU DQ
14
DQ
5
DQ
11
DQ
10
DQ
0
CE#
A
16
GND D
15
D
13
DQ
4
DQ
2
V
SSQ
A
0
WAIT# V
CCQ
D
7
V
SSQ
V
CC
V
CCQ
OE# A
22(1)
DU DU DU A
5
A
4
28F800F3 and 28F160F3
4
NOTES:
1. Shaded connections on the Top View indicate upgrade address connections. Lower density devices will not
have upper address solder balls. Routing is not recommended in this area.
2. A20 and A21 are the upgrade addresses for potential 32-Mbit and 64-Mbit devices.
3. Reference the
µBGA* Package Mec hanical and Shipping Media Specification
at the Intel® Flash Packaging
Data website, http:/ /developer.intel.com/design/flash/packdata/index.htm, f or detail ed p ackage specifications.
Figure 2. 56-Ball µBGA* Package Ballout
V
PP
V
CC
GNDCLK A
15
A
14
A
11
WE# ADV# A
8
A
17
A
7
A
18
WP# A
9
A
10
A
13
V
CCQ
DQ
7
DQ
13
DQ
12
DQ
4
DQ
11
DQ
10
DQ
9
DQ
1
DQ
2
DQ
3
V
CC
DQ
5
DQ
6
DQ
15
A
16
A
12
87654321
DQ
8
V
CCQ
GND DQ
14
GND WAIT#
A
B
C
D
E
F
910
A
4
A
1
A
5
A
2
A
3
A
6
DQ
0
CE#
A
0
OE#
GND
RST#
A
19
A
12
A
15
GND CLK V
CC
A
17
WE#ADV#A
8
A
11
A
14
A
13
A
10
A
9
WP# A
18
A
7
DQ
9
DQ
10
DQ
11
DQ
4
DQ
12
DQ
13
DQ
7
V
CCQ
A
16
DQ
15
DQ
6
DQ
5
V
CC
DQ
3
DQ
2
DQ
1
V
PP
12345678
A
B
C
D
E
Pin #1
Indicator
WAIT# GND DQ
14
GND V
CCQ
DQ
8
F
A
4
A
5
A
6
DQ
0
OE#
9
GND
A
1
A
2
A
3
CE#
A
0
10
RST#
A
19
Top View, Ball Side Down
A
20
A
21
A
20
A
21
Botto m View, Ba ll Side Up
28F800F3 and 28F160F3
5
NOTE: A20 and A21 are the upgrade addresses for potential 32-Mbit and 64-Mbit devices.
NOTE: A20 and A21 are the upgrade addresses for potential 32-Mbit and 64-Mbit devices.
Figure 3. SSOP Pinout
16-Mbit
WE# WE#
RST# RST#
VPP VPP
WP# WP#
NC A19
A1A1
A2A2
A3A3
A4A4
A5A5
A6A6
A7A7
A17 A17
A18 A18
DQ9DQ9
DQ1DQ1
DQ8DQ8
DQ0DQ0
OE# OE#
GND GND
CE# CE#
A0A0
NC NC
VCCQ VCCQ
DQ2DQ2
DQ10 DQ10
DQ3DQ3
DQ11 DQ11
VCC
VCC CLKCLK ADV#ADV# GNDGND NCNC A15
A15 A14
A14 A13
A13 A12
A12 A11
A11 A10
A10 A9
A9A8
A8NCNC GNDGND DQ6
DQ6DQ14
DQ14 DQ7
DQ7DQ15
DQ15 GNDGND VCCQ
VCCQ A16
A16 WAIT#WAIT# DQ13
DQ13 DQ5
DQ5DQ12
DQ12 DQ4
DQ4VCC
VCC
56-Lead SSOP
16 mm x 23.7 mm
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
8-Mbit 8-Mbit 16-Mbit
--A
20
32-Mbit
--A
21
64-Mbit
Figure 4. TSOP Pinout
56-Lead TSOP
14 mm x 20 mm
Top View
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
WAIT#
GND
DQ
15
DQ
14
DQ
6
DQ
7
GND
DQ
5
DQ
12
DQ
13
DQ
3
DQ
10
DQ
9
V
CCQ
DQ
2
DQ
1
DQ
0
OE#
DQ8
GND
NC
CE#
V
CC
DQ
4
28F800F3
DQ
11
V
CCQ
A
16
8Mbit 16Mbit
WAIT#
GND
DQ
15
DQ
14
DQ
6
DQ
7
GND
DQ
5
DQ
12
DQ
13
DQ
3
DQ
10
DQ
9
V
CCQ
DQ
2
DQ
1
DQ
0
OE#
DQ
8
GND
NC
CE#
V
CC
DQ
4
28F160F3
DQ
11
V
CCQ
A
16
16Mbit 8Mbit
A
0
A
0
A
11
A
9
A
8
A
10
NC
GND
ADV#
NC
RST#
WP#
V
CC
CLK
28F800F3
WE#
A
14
A
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
NC
V
PP
A
12
A
13
A
11
A
9
A
8
A
10
NC
GND
ADV#
NC
RST#
WP#
V
CC
CLK
28F800F3
WE#
A
14
A
15
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
17
A
18
V
PP
A
12
A
13
A
19
--A
21
64MBit
--A
20
32MBit
28F800F3 and 28F160F3
6
Table 1. Pin Descriptions
Sym Type Name and Function
A0–A19 INPUT ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally
latched during read and write cycles.
8-Mbit: A0–18, 16-Mbit: A0–19
DQ0–
DQ15 INPUT/
OUTPUT
DATA INPUT/ OUTPUT S: Input s data and commands during write cycles, outputs data during memory
array, st atus register (DQ0–DQ7), and identifier code read cycles. Data pins float to high-impedance
when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle.
CLK INPUT
CLOCK: Synchronizes the flash memory to the system operating frequency during synchronous burst
mode read operations. When configured for synchronous burst-mode reads, the address is latched on
the first rising (or falling, depending upon the read configuration register setti ng) CLK edge when ADV#
is active or upon a rising ADV# edge, whichever occurs first. CLK is ignored during asynchronous
page-mode read and write operations.
ADV# INPUT ADDRESS VALID: Indicates that a valid address is present on the address inputs. Addresses are
latched on the rising edge of ADV# during read and write operations. ADV# may be tied active during
asynchronous read and write operations.
CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and sense amplifiers.
CE#-high deselects the device and reduces power consumption to standby levels.
RST# INPUT RESET: When driven low, RST# inhibits write operations which provides data protection during power
transitions, and it resets internal automation. RST#-high enables normal operation. Exit from reset sets
the device to asynchronous read array mode.
OE# INPUT OUTPUT ENABLE: Gates data outputs during a read cycle.
WE# INPUT WRITE ENABLE : Controls writes to the CUI and array. Addres ses and data are latched on the rising
edge of the WE# pulse.
WP# INPUT
WRITE PROTECTION: Provides a method for locking and unlocking two parameter blocks.
When WP# is at logic low, lockable blocks are locked. If a program or erase operation is attempted on
a locked block, SR.1 and either SR.4 [program] or SR.5 [block erase] will be set to indicate the
operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
WAIT# OUTPUT WAIT: Provides data valid feedback only when configured for synchronous burst mode and the burst
length is set to continuous. This signal is gated by OE# and CE# and is internally pull-up to VCCQ via a
resistor. WAIT# from several components can be tied together to form one system WAIT# signal.
VPP SUPPLY
BLOCK ERASE AND PROGRAM POWER SUP PLY (2.7 V–3.6 V, 11.4 V–12.6 V ): For erasing array
blocks or programming data, a valid voltage must be applied to this pin. With VPP ≤ VPPLK, memory
contents cannot be altered. Block erase and program with an invalid VPP voltage should not be
attempted.
Applying 11.4 V–12.6 V to VPPcan only be done for a maximum of 1000 cycles on main blocks and
2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum
(see Section 6.0 for details).
VCC SUPPLY DEVICE POWER SUPPLY (2.7 V–3.6 V): With VCC ≤ VLKO, all write attempts to the fl ash memory are
inhibited. Device operations at invalid VCC voltages should not be attempted.
VCCQ SUPPLY
OUTPUT POWER SUPPLY (1.65 V–2.5 V, 2.7 V–3.6 V): Enables all outputs to be driven to 1.65 V to
2.5 V or 2.7 V to 3.6 V. When VCCQ equals 1.65 V–2.5 V, VCC voltage must not exceed 3.3 V and
should be regulated to 2.7 V–2.85 V to achieve lowest power operation (see
DC Characteristics
for
detailed information).
For 5 V-tolerant operation VCCQ must equal VCC voltage and must be regulated to 2.7 V to 3.6 V.
This input may be tied directly to VCC.
GND SUPPLY GROUND: Do not float any ground pins.
NC NO CONNECT: Lead is not internally connected; it may be driven or floated. (Pins noted as possible
upgrades to 32-Mbit and 64-Mbit densities can be connected to the appropriate address lines to pre-
enable designs for possible future devices.).
28F800F3 and 28F160F3
7
2.3 Memory Blocking Organization
The 3 Volt Fast Boot Block Flash memory family is an asymmetrically-blocked architecture that
enables system integration of code and data within a single flash device. For the address locations
of each block, see the memory maps in Figure 5, “8- and 16-Mbit Top Boot Memory Map” on
page 8 (top boot blocking) and Figure 6, “8- and 16-Mbit Bottom Boot Memory Map” on page 9
(bottom boot blocking).
2.3.1 Parameter Blocks
The 3 Volt Fast Boot Block Flash memory architecture includes parameter blocks to facilit ate
storage of frequently updated small parame ters that would norm ally be stored in an EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated. Each 8-
and 16-Mbit device contains eight 4-Kwords (4,096-words) parameter blocks.
2.3.2 Main Blocks
After the parameter blocks, the remainder of the array is divided into equal size main blocks for
code and/or data storage. The main blocks are the area of the device that support four-, eight-, and
continuous burst operations. The 8-Mbit device contains fifteen 32-Kword (32,768-word) main
blocks, and the 16-Mbit device contains thirty-one 32-Kword (32,768-word) main blocks.
28F800F3 and 28F160F3
8
0644_05
Figure 5. 8- and 16-Mbit Top Boot Memory Map
16-Mbit8-Mbit
70000H - 77FFFH
68000H - 6FFFFH
60000H - 67FFFH
58000H - 5FFFFH
50000H - 57FFFH
48000H - 4FFFFH
40000H - 47FFFH
38000H - 3FFFFH
30000H - 37FFFH
28000H - 2FFFFH
20000H - 27FFFH
18000H - 1FFFFH
10000H - 17FFFH
08000H - 0FFFFH
00000H - 07FFFH
4-Kword
Parameter Block 19
4-Kword
Parameter Block 20
4-Kword
Parameter Block 21
4-Kword
Parameter Block 22
Paramet er Blocks
4-Kword
Parameter Block 18
4-Kword
Parameter Block 17
4-Kword
Parameter Block 16
4-Kword
Parameter Block 15
7F000H - 7FFFFH
7E000H -7EFFFH
7D000H - 7DFFFH
7C000H - 7CFFFH
7B000H - 7BFFFH
7A000H - 7AFFFH
79000H - 79FFFH
78000H - 78FFFH
EEPROM
Replacement Lockable
Blocks
32-Kword
Main Block 0
32-Kword
Main Block1
32-Kword
Main Block 2
32-Kword
Main Block 3
32-Kword
Main Block 4
32-Kword
Main Block 5
32-Kword
Main Block 6
32-Kword
Main Block 7
32-Kword
Main Block 8
32-Kword
Main Block 9
32-Kword
Main Block 10
32-Kword
Main Block 11
32-Kword
Main Block 12
32-Kword
Main Block 13
32-Kword
Main Block 14
Main Blocks
Burstable Area
32-Kword
Main Block 0
32-Kword
Main Block 1
32-Kword
Main Block 2
32-Kword
Main Block 3
32-Kword
Main Block 4
32-Kword
Main Block 5
32-Kword
Main Block 6
32-Kword
Main Block 7
32-Kword
Main Block 8
32-Kword
Main Block 9
32-Kword
Main Block 10
32-Kword
Main Block 11
32-Kword
Main Block 12
32-Kword
Main Block 13
32-Kword
Main Block 14
32-Kword
Main Block 15
32-Kword
Main Block 16
32-Kword
Main Block 30
32-Kword
Main Block 17
32-Kword
Main Block 18
32-Kword
Main Block 19
32-Kword
Main Block 20
32-Kword
Main Block 21
32-Kword
Main Block 22
32-Kword
Main Block 23
32-Kword
Main Block 24
32-Kword
Main Block 25
32-Kword
Main Block 26
32-Kword
Main Block 27
32-Kword
Main Block 28
32-Kword
Main Block 29
Main Blocks
Burstable Area
F0000H - F7FFFH
E8000H - EFFFFH
E0000H - E7FFFH
D8000H - DFFFFH
D0000H - D7FFFH
C8000H - CFFFFH
C0000H - C7FFFH
B8000H - BFFFFH
B0000H - B7FFFH
A8000H - AFFFFH
A0000H - A7FFFH
98000H - 9FFFFH
90000H - 97FFFH
88000H - 8FFFFH
80000H - 87FFFH
78000H - 7FFFFH
70000H - 77FFFH
68000H - 6FFFFH
60000H - 67FFFH
58000H - 5FFFFH
50000H - 57FFFH
48000H - 4FFFFH
40000H - 47FFFH
38000H - 3FFFFH
30000H - 37FFFH
28000H - 2FFFFH
20000H - 27FFFH
18000H - 1FFFFH
08000H - 0FFFFH
00000H - 07FFFH
10000H - 17FFFH
4-Kword
Parameter Block 35
4-Kword
Parameter Block 36
4-Kword
Parameter Block 37
4-Kword
Parameter Block 38
Parameter Blocks
4-Kword
Parameter Block 34
4-Kword
Parameter Block 33
4-Kword
Parameter Block 32
4-Kword
Parameter Block 31
EEPROM
Replacement Lockable
Blocks
FF000H - FFFFFH
FE000H - FEFFFH
FD000H - FDFFFH
FC000H - FCFFFH
FB000H - FBFFFH
FA000H - FAFFFH
F9000H - F9FFFH
F8000H - F8FFFH
Address RangeAddress Range
28F800F3 and 28F160F3
9
0644_06
Figure 6. 8- and 16-Mbit Bottom Boot Memory Map
16-Mbit8-Mbit
07000H - 07FFFH
06000H - 06FFFH
05000H - 05FFFH
04000H - 04FFFH
03000H - 03FFFH
02000H - 02FFFH
01000H - 01FFFH
00000H - 00FFFH
32-Kword
Main Block 8
32-Kword
Main Block 9
32-Kword
Main Block 10
32-Kword
Main Block 11
32-Kword
Main Block 12
32-Kword
Main Block 13
32-Kword
Main Block 14
32-Kword
Main Block 15
32-Kword
Main Block 16
32-Kword
Main Block 17
32-Kword
Main Block 18
32-Kword
Main Block 19
32-Kword
Main Block 20
32-Kword
Main Block 21
32-Kword
Main Block 22
Main Blocks
Burstable Area
78000H - 7FFFFH
70000H - 77FFFH
68000H - 6FFFFH
60000H - 67FFFH
58000H - 5FFFFH
50000H - 57FFFH
48000H - 4FFFFH
40000H - 47FFFH
38000H - 3FFFFH
30000h - 37FFFh
28000H - 2FFFFH
20000H - 27FFFH
18000H - 1FFFFH
10000H - 17FFFH
08000H - 0FFFFH
32-Kword
Main Block 8
32-Kword
Main Block 9
32-Kword
Main Block 10
32-Kword
Main Block 11
32-Kword
Main Block 12
32-Kword
Main Block 13
32-Kword
Main Block 14
32-Kword
Main Block 15
32-Kword
Main Block 16
32-Kword
Main Block 17
32-Kword
Main Block 18
32-Kword
Main Block 19
32-Kword
Main Block 20
32-Kword
Main Block 21
32-Kword
Main Block 22
32-Kword
Main Block 23
32-Kword
Main Block 24
32-Kword
Main Block 38
32-Kword
Main Block 25
32-Kword
Main Block 26
32-Kword
Main Block 27
32-Kword
Main Block 28
32-Kword
Main Block 29
32-Kword
Main Block 30
32-Kword
Main Block 31
32-Kword
Main Block 32
32-Kword
Main Block 33
32-Kword
Main Block 34
32-Kword
Main Block 35
32-Kword
Main Block 36
32-Kword
Main Block 37
Main Blocks
Burstable Area
F8000H - FFFFFH
F0000H - F7FFFH
E8000H - EFFFFH
E0000H - E7FFFH
D8000H - DFFFFH
D0000H - D8FFFH
C8000H - CFFFFH
C0000H - C7FFFH
B8000H - BFFFFH
B0000H - B7FFFH
A8000H - AFFFFH
A0000H - A7FFFH
98000H - AFFFFH
90000H - 97FFFH
88000H - 8FFFFH
80000H - 87FFFH
78000H - 7FFFFH
70000H - 77FFFH
68000H - 6FFFFH
60000h - 67FFFh
58000H - 5FFFFH
50000H - 57FFFH
48000H - 4FFFFH
40000H - 47FFFH
38000H - 3FFFFH
30000H - 37FFFH
28000H - 2FFFFH
20000H - 27FFFH
18000H - 1FFFFH
10000H - 17FFFH
08000H - 0FFFFH
4-Kword
Parameter Block 4
4-Kword
Parameter Block 5
4-Kword
Parameter Block 6
4-Kword
Parameter Block 7
Parameter Blocks
4-Kword
Parameter Block 3
4-Kword
Parameter Block 2
4-Kword
Parameter Block 1
4-Kword
Parameter Block 0
EEPROM
Replacement
Lockable
Blocks
4-Kword
Parameter Block 4
4-Kword
Parameter Block 5
4-Kword
Parameter Block 6
4-Kword
Parameter Block 7
Parameter blocks
4-Kword
Parameter Block 3
4-Kword
Parameter Block 2
4-Kword
Parameter Block 1
4-Kword
Parameter Block 0
EEPROM
Replacement
Lockable
Blocks
07000H - 07FFFH
06000H - 06FFFH
05000H - 05FFFH
04000H - 04FFFH
03000H - 03FFFH
02000H - 02FFFH
01000H - 01FFFH
00000H - 00FFFH
Address RangeAddress Range
28F800F3 and 28F160F3
10
3.0 Principles of Operation
The 3 Volt Fast Boot Block Flash memory components include an on-chip Write State Machine
(WSM) to manage bl ock erase and pro gram. It all ows for C MOS-lev el contro l i np uts, fi xed po wer
supplies, and minimal processor overhead with RAM-like interface timings.
3.1 Bus Operations
The local CPU reads and writes flash memory in-system. All flash memory read and write cycles
conform to standard microprocessor bus cycles.
3.1.1 Read
The flash memory has three read modes available: read array, identifier codes, and status register.
These modes are accessible independent o f the VPP voltage. The appropriate read command (Read
Array, Read Identifier Codes, or Read Status Register) must be written to the CUI to enter the
requested read mode. Upon initial power-up or exit from reset, the device defaults to read array
mode.
When reading information from main blocks in read array mode, the device supports two high-
performance read configurations: synchronous burst mode and asynchronous page mode. Page
mode and synchronous burst-mode reads are enabled by writing the Set Read Configuration
Register command to any device address.
Synchronous burst mode is enabled by writing to the read configuration register. This sets the read
configuration, burst order, burst length, and frequency configuration. In synchronous burst mode,
the device latches the initial address then outputs a sequence of data with respect to the input CLK
and read config uration setting. Sy nchronous burst reads can b e termi nated aft e r one cycle in main
blocks. Asynchronous page mode is the default state and provides a high data transfer rate for non-
clocked me m ory subsys tems. In this state, data is internally read and stored in a high-sp eed page
buffer. A1:0 addresses data in the page buffer. The page size is four words.
Read operations from the parameter blocks, identifier codes and status register transpire as single-
synchronous or asynchronous read cycles. The read configuration register setting determines
whether or not read operations are synchronous or asynchronous.
For all read operations, CE# must be driven active to enab le the devices, ADV# must be driven low
to open the internal address latch, and OE# must be driven low to activate the outputs. In
asynchronous mode, the address is latched when ADV# is driven high. In synchronous mode, the
address is latched by ADV# going high or ADV# low in conjunction with a rising (falling) clock
edge, whichever occurs first. WE# must be at VIH. Figure 17 through Figure 22 illustrate the
different read cycles.
3.1.2 Output Disable
With OE# at a logic-hig h level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
28F800F3 and 28F160F3
11
3.1.3 St andby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption. In standby, outputs are placed in a
high-impedance state independent of OE#. If deselected during program or erase operation, the
device continues to consume activ e power until the program or erase operation is complete.
3.1.4 Write
Commands are written to the CUI using standard micropro cessor write timings when ADV#, WE#,
and CE# are active and OE# is inactive. The CUI does not occupy an add ressable memory location.
The address is latched on the rising edge of ADV#, WE#, or CE# (whichever occurs first) and data
needed to execute a command is latched on the rising edge of WE# or CE# (whichever goes high
first). Write operations are asynchronous. Therefore, CLK is ignored during write operations.
Figu re 23, “AC Waveform for Write Operations” on page 42 illustrates a write operation.
3.1.5 Reset
The device enters a reset mode when RST# is driven low. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After return from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWL or
tPHEL) is required before a write sequence can be initiated. After this wake-up interval, normal
operation is restored. The device defaults to read array mode, the status register is set to 80H, and
the read configuration register defaults to asynchronous page-mode reads.
If RST# is taken low during a bloc k erase or program operation, the operation will be aborted and
the memory contents at the aborted location are no longer valid. See Figure 24, “AC Waveform for
Reset Operation” on page 43 for detailed information regarding reset timings.
28F800F3 and 28F160F3
12
4.0 Command Definitions
Device operation s are selected by writing specific commands into the CUI. Table 3 defines these
commands.
NOTES:
1. R e fer to
DC Characteristics
. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control and address input pins and VPPLK or VPP1 or VPP2 for VPP. See
DC
Characteristics
for VPPLK and VPP1 or VPP2 voltages.
3. Command writes involving block erase or program are reliably executed when VPP = VPP1 or VPP2 and VCC =
VCC1 or VCC2 (see Section 8.0 for operating conditions at different temperatures).
4. R e fer to Table 3 for valid DIN during a write operation.
NOTES:
1. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
2. Bus operations are defined in Table 2.
3. X = Any valid address within the device.
IA = Identifier Code Address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
RCD = Data to be written to the read configuration register. This data is presented to the device on A15-0; set
all other address inputs to “0.” See Table 6, “Read Configuration Register Definition” on page 17 for a
description of the read configuration register bits.
Table 2. Bus Operations
Mode Notes RST# CE# ADV# OE# WE# Address VPP DQ0–15
Reset VIL XXX XXXHigh Z
Standby VIH VIH XXXXXHigh Z
Output Disable VIH VIL XV
IH VIH X X High Z
Read 1,2 VIH VIL VIL VIL VIH XXD
OUT
Read Identifier Codes VIH VIL VIL VIL VIH See
Table 4 XSee
Table 4
Write 3,4 VIH V
IL VIL VIH VIL XXD
IN
Table 3. Command Definitions(1)
Command Bus Cycles
Required Notes First Bus Cycle Second Bus Cycle
Oper(2) Addr(3) Data(4) Oper(2) Addr(3) Data(4)
Read Array/Reset 1 Write X FFH
Read Identifier Codes ≥ 2 5 Wri te X 90H Read IA ID
Read Status Register 2 Write X 70H Read X SRD
Clear Status Register 1 Write X 50H
Block Erase 2 6,7 Write X 20H Write BA D0H
Program 2 6,7,8 Write X 40H
or
10H Write WA WD
Block Erase and Program Sus pend 1 6 Write X B0H
Block Erase and Program Resume 1 6 Write X D0H
Set Read Configuration 2 Write RCD 60H Write RCD 03H
28F800F3 and 28F160F3
13
4. SRD = Data read from status register. See Table 5, “Status Register Definition” on page 15 for a description
of the status register bits.
WD = Data to be written at location WA. Dat a is latched on the rising edge of WE# or CE# (whichever goes
high first).
ID = Data read from identifier codes. See Table 4 for manufacturer and device codes.
5. Following the Read Identifier Codes command, read operations access manufacturer, device codes, and
read configuration register.
6. Following a block erase, program, and suspend operation, read operations access the status register .
7. To issue a block erase, program, or suspend operation to a lockable block, hold WP# at VIH.
8. Either 40H or 10H are recognized by the WSM as the program setup.
4.1 Read Array Command
Upon initial device power-up or exit from reset, the device defaults to read array mode. The read
configuration register defaults to asynchronous page mode. The Read Array command also causes
the device to enter read array mode. The device remains enabled for reads until another command
is written. Once the internal WSM has started a block erase or program, the device will n ot
recognize the Read Array com mand until th e WSM completes its operation or unless the W SM is
suspended via an Erase or Program Suspend command. The Read Array command functions
independently of the VPP voltage.
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writ ing the Read Identifier Codes co mmand. After
writing the command, read cycles retrieve the manufacturer and device codes (see Table 4 for
identifier code values). Page mode and burst reads are not supported in this read mode. To
terminate the operation, write another valid command, like the Read Array command. The Read
Identifier Codes comman d functions in dependently of the VPP voltag e .
NOTE: 1. Read Configuration Register = RCD.
Table 4. Identifier Codes
Code Address Data
Manufacturer Code 00000H 0089H
Device Code
8 Mbit -T 00001H 88F1H
-B 00001H 88F2H
16 Mbit -T 00001H 88F3H
-B 00001H 88F4H
Read Configuration Register 00005H RCD(1)
28F800F3 and 28F160F3
14
4.3 Read Status Register Command
The status register can be read at any time by writing the Read Status Register command to the
CUI. After writing this command, all subsequent read operations output statu s register data until
another valid command is written. Page mode and burst reads are not supported in this read mode.
The status register content is updated and latched on the rising edge of ADV# or rising (falling )
CLK edge when ADV# is low during synchronous burst mode or the falling edge of OE# or CE#,
whichever occurs first. The Read Status Register command functions independently of the VPP
voltage.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be cleared
by issuing the Clear Status Register command. These bits indicate various error conditions. By
allowing system software to reset th ese bits, several operation s m ay be performed (such as
cumulatively erasing or writing se veral bytes in sequence). The status register may be polled to
determine if a problem occurred during the sequence. The Clear Status Register command
functions independently of the applied VPP voltage. After executing this command, the device
returns to read array mode.
4.5 Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is
written first, followed by a block erase confirm. This command sequence requires appropriate
sequencing and address within the block to be erased (erase changes all block data to FFH). Block
preconditio ning, erase, and verify are handled internally by the WSM. After the two-cycle block
erase sequence is written, the device automat ically outputs status register data when read (see
Figure 10, “Autom ated Bloc k Eras e Fl owchart” on page 23). The CPU can detect block erase
completion by analyzing status register bit SR.7.
When the block erase completes, check status register bit SR.5 fo r an er ror flag (“1 ”). If an err or is
detected, check status register bits SR.4, SR.3, and SR.1 to understand what caused the failure.
After examining the status register, it should be cleared if an error was detected before issuing a
new command. The dev ice will rem a in in status register read mode until anoth e r comm a nd is
written to th e CUI.
28F800F3 and 28F160F3
15
4.6 Program Command
Program operation is ex ecuted by a two-cycle command sequence. Program setup ( standard 40H or
alternate 10H) is written, followed by a second write that specifies the address and data. The WSM
then takes over , controlling the internal program algorithm. After the program sequence is written,
the device automatically outputs status register data when read (see Figure 11, “Automated
Program Flowchar t” on page 24). The CPU can detect the completion of the program event by
analyzing status regi s ter bit SR.7.
When the program operation completes, check status register bit SR.4 for an error flag (“1”). If an
error is detected, check status register bits SR.5, SR.3, and SR.1 to understand what caused the
problem. After examining the status register, it should be cleared if an error was detected before
issuing a new command. The de vice will remain in statu s register read mode until another
command is written to the CUI.
Table 5. Status Register Definition
WSMS ESS ES PS VPPS PSS DPS R
76543210
NOTES:
SR.7 = WRITE STATE MACHI NE STAT US (WSMS)
1 = Ready
0 = Busy
Check SR.7 to determine block erase or program completion.
SR.6–0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUS PEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
When an Erase Suspend command is issued, the WSM halts
execution and sets both SR.7 and SR.6 to “1.” SR.6 remains
set until an Erase Resume command is written to the CUI.
SR.5 = ERASE STAT US (ES )
1 = Error in Block Erasure
0 = Successful Block Erase
If both SR.5 and SR.4 are “1”s after a block erase or program
attempt, an improper command sequence was entered.
SR.4 = PROGRA M STAT US (PS)
1 = Error in Program
0 = Successful Program
SR.3 = VPP STATUS (VP PS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
SR.3 does not provide a continuous VPP feedback. The WSM
interrogates and indicates the VPP level only after a block erase
or program operation. SR.3 is not guaranteed to report
accurate feedback when VPP ≠ VPPH1 or VPPH2 or VPPLK.
SR.2 = PROGRA M SUS PE ND STATUS (PS S)
1 = Program Suspended
0 = Program in Progress/Completed
When a Program Suspend command is issued, the WSM halts
execution and sets both SR.7 and SR.2 to “1.” SR.2 remains
set until a Program Resume command is written to the CUI.
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Erase or Program Attempted on a Locked Block,
Operation Abort
0 = Unlocked
If a block erase or program operation is attempted on a locked
block, SR.1 is set by the WSM and aborts the operation if
WP# = VIL.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.0 is reserved for future use and should be masked out
when polling the status register.
28F800F3 and 28F160F3
16
4.7 Block Erase Suspend/Resume Command
The Block Erase Suspend command allows block erase interruption to read or program data in
another block. Once the block erase process starts, writin g the Block Erase Suspend comm and
requests that the WSM suspend the block erase operation after a certain latency p eriod . The device
continues to output status register data when read after the Block Erase Suspend command is
issued. Status Register bits SR.7 and SR.6 indicate when the block erase operation has been
suspended (both will be set to “1”). Specification tWHRH2 defines the block erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspended. A Program command sequence can also be issued during erase suspend to program
data in other blocks. Using the Program Suspend command (see Secti on 4.8 ), a program operation
can be suspended during an erase suspend. The only other valid commands while block erase is
suspended are Read Status Register and Block Erase Resume.
During a block erase suspend, the chip can go into a pseudo-standby mode by taking CE# to VIH,
which reduces active current draw. VPP must remain at VPP1 or VPP2 while block erase is
suspended. WP# must also remain at VIL or VIH.
T o resume the block erase operation, write the Block Erase Resume command to the CUI. This will
automatically clear status register bits SR.6 and SR.7. After the Erase Resume command is written,
the device automatically outputs status register data when read (see Figure 12, “Block Erase
Sus pend /Resume Flowchart” on page 25). Block erase can not resume until prog ram o perations
initiated during block erase suspend have completed.
4.8 Program Suspend/Resume Command
The Program Suspend command allows program interruption to read data in other flash mem ory
locations. Once the program process starts, writing the Program Suspend command requests that
the WSM suspend the program operation after a certain latency period. The device continues to
output status register data when read after issuing the Program Suspend command. Status register
bits SR.7 and SR.2 indicate when the Program operation has been suspended (both will b e set to
“1”). Specification tWHRH1 defines the program suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which
is suspen ded. The onl y other valid comm ands while P rogram is suspended are Read S tatus Register
and Program Resume.
During a program suspend, the chip can go into a pseudo-standby mode by taking CE# to VIH,
which reduces active current draw. VPP must remain at VPP1 or VPP2 while program is suspended.
WP# must also remain at VIL or VIH.
To resume the program, write the Program Resu me command to the CUI. This will automatically
clear status register bits SR.7 and SR.2. After the Program Resume command is written, the device
automatically outputs status register data when read (see Figure 13, “Program Suspend/Resume
Flowchart” on page 26).
28F800F3 and 28F160F3
17
4.9 Set Read Configuration Command
The Set Read Conf iguration co mmand writes data to the read configuration register. This operation
is initiated by a standard two bus cycle command sequence. The Read Configuration Setup
command (60H) is wri tten and the data to be written to the read con figuration is presented, which
is then followed by a second write that confirms the operation and again presents the data to be
written to the read configuration register. The read configuration register data is placed on the
address bus, A15:0,during bo th bus cycles and is latched on the rising edge of ADV#, CE#, or WE#
(whichever occurs first). The read configuration register data sets the device’s read configuration,
burst order, frequency configuration, burst length and all other parameters. This command
functions indep e ndently of the applied VPP voltage. After executing this command, the device
returns to read array mode.
Table 6. Read Configuration Register Definition
RM R FC2 FC1 FC0 R DOC WC
15 14 13 12 11 10 9 8
BS CC R R R BL2 BL1 BL0
76543210
NOTES:
RCR.15 = READ MODE (RM)
0 = Synchronous Burst Reads Enabled
1 = page mode Reads Enabled (Default)
Read mode configuration affects reads from main blocks.
Parameter block, status register, and identifier reads support
single read cycles.
RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use. Set these bits to “0.”
RCR.13–11 = FREQUENCY CONFIGURATION (FC2-0)
001 = Code 1 reserved for future use
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6
See Section 4.9.2 for information about the frequency
configuration and its effect on the initial read.
Undocumented combinations of bits
RCR.14–11 are reserved by Intel Corporation for future
implementations and should not be used.
RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use. Set these bits to “0.”
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
0 = Hold Data for One Clock
1 = Hold Data for Two Clocks
Undocumented combinations of bits RCR.10–9 are reserved
by Intel Corporation for future implementations and should not
be used.
RCR.8 = WAIT CONFIG URATION (WC)
0 = WAIT# Asserted During Delay
1 = WAIT# Asserted One Data Cycle Before Delay
RCR.7 = BURST SEQUENCE (BS)
0 = Intel Burst Order
1 = Linear Burst Order
RCR.6 = CLOCK CONFIGURATION (CC)
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
RCR.5–3 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use. Set these bits to “0.”
RCR.2–0 = BURST LENGTH (BL2–0)
001 = 4 Word Burst
010 = 8 Word Burst
111 = Continuous Burst
In the asynchronous page mode, the burst length always
equals four words. Undocumented combinations of bits
RCR.2–0 are reserved by Intel Corporation for future
implementations and should not be used
28F800F3 and 28F160F3
18
4.9.1 Read Configuration – (RCR.15)
The device supports two high performance read configurations: Synchronous burst mode and
asynchronous page mod e. Bit RCR.15 in the read configuration regi ster sets the read configuration
to either synchronous burst or asynchronous page mode. Asynchronous page mode is the default
read configuration state.
Parameter blocks, status register, and identifier modes only support single-synchronous and
asynchronous read operations.
4.9.2 Frequency Configuration Code Setting (FCC) – (RCR.13-11)
The frequency configuration code setting inform s the device of the number of clocks that must
elapse after ADV# is driven active before data will be available. This value is determined by the
input clock frequency and the set up and hold requirements of the target system. See Table 7,
“Frequen cy Configurat ion Settin gs” on page 20 for the specific i nput CLK fr equency con figuratio n
codes. The frequency configuration codes in Table 7 are derived from equations (1), (2) and (3)
with assu med values for the tAVQV, tADD, tDATA parameters. Below is the example of the
calculation to obtain the frequency configuration code:
Flash performance can be determined by the following equations:
{1/Frequency (MHz)}1000 = CLK Period (ns) (1)
n(CLK Period) ≥ tAVQV (ns) + tADD(ns) + tDATA (ns) (2)
n-2 = Frequency Configuration Code (FCC)*(3)
n : # of Clock periods (rounded up to the next integer)
*Must use FCC = n - 1 when operating in the continous burst mode.
Parameters defined by CPU:
tADD = Clock to CE#, ADV#, or Address Valid whichever occurs last.
tDATA = Data set up to Clock
Parameters defined by f la sh:
tAVQV = Address to Output Delay
Example:
CPU Clock Speed = 50 MHz
tADD = 6 ns (typical speed from CPU) (max)
tDATA = 4 ns (typical speed from CPU) (min)
tAVQV = 90 ns (from Section 8.5 AC Characteristic - Read Only Operations Table)
From Eq. (1): {1/50 (MHz)}1000 = 20 ns
From Eq. (2) n(20 ns) ≥ 90 ns + 6 ns + 4 ns
n(20 ns) ≥ 100 ns
n ≥ 100/ 20 ≥ 5 (Integer)
Fr om Eq. (3) n - 2 = 5 - 2 = 3
Frequency Code Setting to the RCR is Code 3
The formula tAVQV (ns) + tADD(ns) + tDATA (ns) is also known as initial access time.
28F800F3 and 28F160F3
19
NOTE:
1. Figure 7 shows the data output available and valid after 4 latencies from ADV# going low in the 1st clock
period with the FCC setting at 3.
Figure 8 illustrates data output latency from ADV# going active for different frequency
configuration codes.
Figure 7. Data Output with FCC Setting at Code 3
A
15-0
Valid Address
DQ
15-0
(D/Q)
CLK (C)
CE#
ADV#
R13
Valid
Output Valid
Output
High Z
t
ADD
t
DATA
2nd1st 3rd 4th 5th
Figure 8. Frequency Configuration
ADV# (V)
A
19-0
(A)
Valid
Address
CLK (C)
DQ
15-0
(D/Q)
Valid
Output
DQ
15-0
(D/Q)
Valid
Output Valid
Output Valid
Output Valid
Output
DQ
15-0
(D/Q)
Valid
Output Valid
Output Valid
Output Valid
Output
DQ
15-0
(D/Q)
Valid
Output Valid
Output
DQ
15-0
(D/Q)
Valid
Output Valid
Output Valid
Output
Valid
Output
Code 2
Code 3
Code 4
Code 5
Code 6
28F800F3 and 28F160F3
20
NOTE: Table derived by using formulas (1), (2) and (3) in Section 4.9.2. Values of tADD, tDATA defined by CPU,
assumed to be 6 ns and 4 ns respectively; value of tAVQV per Section 8.5.
4.9.3 Dat a Output Configuration – (RCR.9)
The output configuration d etermines the number of clocks during w hich data will be held valid.
The data hold time is configurable as either one or two clocks.
Subsequent reads in burst mode with zero wait-states can be defined by:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (4)
In Table 7, consider the CPU clock at 50 MHz, and FCC is 3. The clock period is 20 ns. This data
applied to the formula above for the subsequent reads assuming the data output hold time is one
clock: 14 ns + 4 ns ≤ 20 ns
Data output will be available and valid at every clock period.
Consider the CPU frequency at 60 MHz, and FCC is 4. Clock period is 16.6 ns. The initial access
time is calculated to be 100 ns (4 latencies). This condition satisfies tAVQV (ns) + tADD(ns) + tDATA
(ns) = 90 ns + 6 ns + 4 ns = 100 ns. However, the data output hold time of one clock violates burst
data output zero wait-states:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period
14 ns + 4 ns = 18 ns is not less than one clock period. To satisfy the formula above the data output
hold time must b e set a 2 clocks to correctly allow for data ou tput setup time. This formula is also
satisfied if the CPU has tDATA (ns) ≤ 2 ns, which yields:
14 ns + 2 ns ≤ 16.6 ns
In page mode reads the initial access time can be determined by the formula:
tADD (ns) + tDATA (ns) + tAVQV (ns) (5)
and subsequent reads in page mode are defined by:
tAPA (ns) + tDATA (ns) (minimum time) (6)
Table 7. Frequency Configuration Settings
Frequency
Configurat ion Code
Input CLK Frequency
–95 –120
VCC = 3.0 V–3.6 V VCC = 2.7 V–3.6 V VCC = 2.7 V–3.6 V
1 Reserved Reserved Reserved
2 ≤ 40 MHz ≤ 38 MHz ≤ 30 MHz
3≤ 50 MHz ≤ 47 MHz ≤ 38 MHz
4≤ 60 MHz ≤ 57 MHz ≤ 46 MHz
5≤ 66 MHz ≤ 66 MHz ≤ 53 MHz
6——≤ 60 MHz
28F800F3 and 28F160F3
21
4.9.4 Wait # Configuration – (RCR.8)
The WAIT# confi g urati on bi t controls the behavior of the WAIT# outp ut s ig nal. Th is ou t put s ignal
can be set to be asserted during or one CLK cycle before an output delay when continuous burst
length is enab led. Its setting will dep end on the system and CPU characteristic.
4.9.5 Burst Sequence – (RCR.7)
The burst sequence specifi es the order in which d ata i s addres s ed i n sy nchr ono us burs t mode. Thi s
order is programmable as either linear or Intel burst order. The continuous burst length only
supports linear burst order. The order chosen will depend on the CPU characteristic. See Table 8
for more details.
Figure 9. Output Configuration
DQ
15-0
(D/Q)
Valid
Output
DQ
15-0
(D/Q)
Valid
Output Valid
Output Valid
Output
CLK (C)
1 CLK
Data Hold
2 CLK
Data hold
Table 8. Sequence and Burst Length
St arting
Addr.
(Dec.)
Burst Addressing Sequence (Dec.)
4-Word Burst Length 8-Word Burst Length Continuous Burst
Linear Intel Linear Intel Linear
0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-...
1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-...
3 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-...
3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-...
44-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-..
55-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-...
66-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-...
77-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-...
8NA 8-9-10-11-12-13-14-...
9NA ...
15 NA 15-16-17-18-19-20-21-...
28F800F3 and 28F160F3
22
4.9.6 Clock Configuration – (RCR.6)
The clock configuration config ures the dev ice to start a burst cy cle, output data, and assert WAIT#
on the risi ng or falling edg e of the clock. CLK flexib ility helps ease 3 Volt Fast Boot Block Flash
memory interface to a wide range of burst CPUs.
4.9.7 Burst Length – (RCR.2 — 0)
The burst length is the number of wo rds th at the device will output. The device supports burst
lengths of four and eight words. In four- or eight-word burst configuration the device will perform
a wrap around type burst access (See Table 8). It also supports a continuous burst mode. In
continuous burst mode, the device will linearly output data until the internal burst counter reaches
the end of the dev ice’s burstable address space. Bits RCR.2–0 in the r ead configu ration register set
the burst length.
4.9.8 Continuous Burst Length
When operating in the continuous burst mode, the flash memory may incur an output delay when
the burst sequence crosses the first 16-word boun dary. The starting addr ess dictates whether or n ot
a delay will occur. If the starting address is aligned to a four-word boundary, the delay will not be
seen. If the starting address is the end of a four-word boundary , the output delay will be equal to the
frequency configuration setting; this is the worst case d e lay. The delay will only take place once
during a continuous burst access, and if the burst sequence never crosses a 16-word boundary, the
delay will ne ver happen. Us ing the WAIT# output pin in the continuou s bu rst configuration , the
system is in form ed if this output del a y occurs.
28F800F3 and 28F160F3
23
Figure 10. Automated Block Erase Flowchart
Suspend
Blk. Erase
Loop
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus
Register command, in cases where multiple blocks are erased before
full status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
No
Yes
Suspend
Block Erase
1
0
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Comments
Check SR.3
1 = V
PP
Error Detect
Check SR.1
1 = Device Protect Detect
WP# = V
IL
Read Status Register
Data (See Above)
V
PP
Range Error
Device Protect Error
Block Erase
Successful
SR.3 =
SR.1 =
1
0
1
0
Command Sequence
Error
SR.4, 5 = 1
0
Block Erase ErrorSR.5 = 1
0
Status Register Data
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.5
1 = Block Erase Error
Bus Operation
Write
Write
Standby
Read
Command
Erase Setup
Erase Confirm
Bus Operation
Standby
Standby
Standby
Standby
Command
28F800F3 and 28F160F3
24
Figure 11. Auto mated Program Flowchart
Suspend
Program
Loop
Start
Write 40H,
Address
Write Data and
Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Program Complete
FULL STATUS CHECK PROCEDURE
Repeat for subsequent byte writes.
SR full status check can be done after each byte write or after a
sequence of program operations.
Write FFH after the last byte write operation to place device in read
array mode.
SR.4, SR.3 and SR.1 are only cleared by the Clear Staus Register
command, in cases where multiple locations are written before full
status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
No
Yes
Suspend
Program
1
0
Comments
Data = 40H
Addr = Location to Be
Written
Data = Data to Be Written
Addr = Location to Be
Written
Check SR.7
1 = WSM Ready
0 = WSM Busy
Comments
Check SR.3
1 = V
PP
Error Detect
Check SR.1
1 = Device Protect Detect
WP# = V
IL
Read Status Register
Data (See Above)
V
PP
Range Error
Device Protect Error
Program Successful
SR.3 =
SR.1 =
1
0
1
0
Program ErrorSR.4 = 1
0
Status Register Data
Check SR.4
1 = Data Write Error
Bus Operation
Write
Write
Standby
Read
Command
Program Setup
Data
Bus Operation
Standby
Standby
Standby
Command
28F800F3 and 28F160F3
25
Figure 12. Block Erase Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
Comments
Data = B0H
Addr = X
Data = D0H
Addr = X
SR.7 =
SR.6 = Block Erase
Completed
Write FFH
Read A rra y Da ta
0
1
0
Stat us Reg i s ter D at a
Addr = X
Check SR.7
1 = W SM Ready
0 = W SM Bu s y
Check SR.6
1 = Block Erase Suspended
0 = Block Erase Completed
Read or Byte
Write?
Command
Erase Suspend
Erase Resume
Bus Op er a ti on
Write
Write
Read
Standby
Standby
Yes
Program
Program
Loop
Done
Write D0H
Block Erase Resumed
Read
Read Array
Data No
1
Data = FFH
Addr = X
Read Array or
Program
Write
Read Arra y or Progra m Loop
28F800F3 and 28F160F3
26
Figure 13. Program Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
No
Comments
Data = B0H
Addr = X
Data = FFH
Addr = X
SR.7 =
SR.2 =
1
Write FFH
Read Array Data
Program Completed
Done
Reading
Yes
Write FFHWrite D0H
Program Resumed Read Array Data
0
1
0
Read array locations from
block other than that being
written
Status Register Data
Addr = X
Check SR.7
1 = WSM Ready
0 = WSM Busy
Check SR.2
1 = Program Suspended
0 = Program Completed
Data = D0H
Addr = X
Bus Operation
Write
Write
Read
Read
Standby
Standby
Write
Command
Program
Suspend
Read Array
Program Resume
28F800F3 and 28F160F3
27
5.0 Data Protection
The 3 Volt Fast Boot Block Flash memory architecture features two hardware-lockable parameter
blocks, so critica l code can be kept secur e while si x ot h er pa ramete r blocks can be progr ammed or
erased as necessary to facilitate EEPROM emulatio n.
5.1 VPP ≤ VPPLK for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the
flash device. When VPP is below VPPLK, any block erase or program operation will result in a
error, prompting the corresponding status register bit (SR.3) to be set.
5.2 WP# = VIL for Block Locking
The lockable blocks are locked when WP# = VIL; any block erase or program operation to a locked
block will result in an error, which will be reflected in the status register. For top configuration, the
top two parameter blocks (blocks #37, #38 for the 16 Mbit, blocks #21, #22 for the 8 Mbit) are
lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0, #1) are
lockable. Unlocked blocks can be programmed or erased normally (unless VPP is below VPPLK).
5.3 WP# = VIH for Block Unlocking
WP# controls all block locking and VPP provides protection against sp urious writes. Table 9
defines the write protection methods.
Table 9. Write Protection Truth Table
VPP WP# RST# Write Protection Pro v id ed
XXV
IL All Blocks Locked
VIL XV
IH All Blocks Locked
≥ VPPLK VIL VIH Lockable Blocks Locked
≥ VPPLK VIH VIH All Blocks Unlocked
28F800F3 and 28F160F3
28
6.0 VPP Voltages
Intel 3 Volt Fast Boot Block Flash memory provides in-system programming and erase at 2.7 V–
3.6 V (3.0 V–3.6 V for automotive tem perature) VPP. For customers req uiring fast pro gramming i n
their manufacturing environment , this family of products incl udes an additional high-performance
12 V pr ogramming feature.
The 12 V VPP mode enhances programming performance during short period of time typically
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to VPP during block erase and program operations for a maximum of 1000 cycles on the
main blocks an d 25 00 cy cles on th e param eter blocks. VPP may be conn ected to 12 V for a total of
80 hours maximum. Stressing the device beyond these limits may cause permanent damage.
7.0 Power Consumption
While in operation, the flash device consumes active power. However, Intel® Flash devices have
power savings that can significantly reduce overall system power consumption. The Automatic
Power Savings (APS) feature reduces power consumption when the device is idle. When CE# is
not asserted, the flash enters its standby mode, where current consumption is even lower. The
combination of these features minimizes overall memory power and system power consumption.
7.1 Act ive P o wer
With CE# at a logic-low level an d RST# at a logic-high level, the dev ice is in active mode. Active
power is the largest contributor to overall system power consumption. Minimizing active current
has a profound effect on system power consumption, especially for battery-operated devices.
7.2 Automatic Power Savings
Automatic Po wer Savings (APS) prov ides low-power operation during active mode, allowing the
flash to put itself into a low current state when not being accessed. After data is read from the
memory array, the device’s power consumption enters the APS mode where typical ICC current is
comparable to ICCS. The flash stays in this st atic state with outputs v a lid until a new locat ion is
read.
7.3 Standby Power
W i t h CE# at a logic-h igh level (VIH) and the CUI in read mode, the flash memory is in standby
mode, which disables much of the device’ s circuitry and substantially reduces power consumption.
Outputs (DQ0–DQ15) are placed in a high-impedance state independent of the status of the OE#
signal. If CE# transitions to a logic-high level during erase or prog ram o perations, the device will
continue to perform the operation and consume corresponding active power until the operation is
completed.
28F800F3 and 28F160F3
29
System engineers should analyze the breakdown of standby time versus active time and quantify
the respective power consumption in each mode for their specific application. This will provide a
more accurate measure of application-specific power and energy requirements.
7.4 Power-Up/Down Operation
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is no t required, since the device is indifferent as to which power supply,
VPP, VCC, or VCCQ, powers-up first.
7.4.1 RST# Connection
The use of RST# during system reset is important with automated program/erase devices since the
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. Intel recommends connecting RST# to
the system reset si gnal to allow prop er CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO and VPP
is active. Since b oth WE# and CE# mus t be lo w for a command write, driving either signal to VIH
will inhibit writes to the device. The CUI architecture provides additional protection since
alteration of memor y contents can only occur after successful comp letion of the two-step co mmand
sequences. The device is also disabled until RST# is brought to VIH, regardless of the state of its
control i nputs. By ho ldi ng th e devi ce in re set duri ng po wer -up/d own, invalid bus co nditi ons d uring
power-up can be masked, providing yet another level of memory protection.
7.4.2 VCC, VPP and RST# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from deep power-down
mode or after VCC transitions above VLKO (Lockout voltage), is read array mode.
After any block erase or program operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the
flash memory array is desired.
7.5 Power Supply Decoupling
Flash memory’s power switching characteristics require careful device de-coupling. System
designers should consider three supply current issues:
•Stand by curren t levels (ICCS)
•Active current levels (ICCR)
•Transient peaks produced by falling and rising edges of CE#.
28F800F3 and 28F160F3
30
T ransient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-
line control and proper de-coupling capacitor selection will suppress these transient voltage peaks.
Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND,
and between its V PP and GND. These high- frequency, inherently low-inductance capacitors should
be placed as close as possible to the package leads.
7.5.1 VPP Trace on Printed Circuit Boards
Designing for in-system writes to the flash memory requires special consideration of the VPP power
supply trace by the printed circuit board designer. The VPP pin supplies the flash memory cells
current for prog ramming and er asing. V PP trace wid ths and layout sh ould be similar to that of VCC.
Adequate V PP supply traces, and de-coupling capacitors placed adjacent to the component, will
decrease spikes and overshoots.
8.0 Electrical Specifications
8.1 Absolute Maximum Ratings
NOTES:
1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and
–0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns.
Maximum DC voltage on input/output pins is 5.5 V and VCC and VCCQ is VCC + 0.5 V which, during transitions,
may overshoot to VCC +2.0 V for periods <20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. VPP Program voltage is normally 2.7 V–3.6 V. Connection to supply of 11.4 V–12.6 V can only be done for
1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP may be
connected to 12 V for a total of 80 hours maximum.
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended
and extende d exposure beyond the “Operating Cond itions” may affect device reliability.
Parameter Maximum Rating
Temperature under Bias –40 °C to +125 °C
Storage Temperature –65 °C to +125 °C
Voltage On Any Pin (except VCC, V CCQ, and VPP) –0.5 V to +5.5 V(1)
VPP Voltage –0.5 V to +13.5 V(1, 2, 4)
VCC and VCCQ Voltage –0.2 V to +5.0 V(1)
Output Short Circuit Current 100 mA(3)
NOTICE: This datasheet contains information on products in full production. The specifications are subject to
change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a
design.
28F800F3 and 28F160F3
31
8.2 Extended Temperature Operating Conditions
NOTE:
1. See
DC Characteristics
tables for voltage range-specific specifications.
2. The voltage swing on the inputs, VIN is required to match VCCQ .
3. Applying VPP = 11.4 V–12.6 V during a program or erase can only be done for a maximum of 1000 cycles on
the main blocks and 2500 cycles on the parameter blocks. A hard connection to VPP = 11.4 V–12.6 V is not
allowed and can cause damage to the device.
4. VCC, VCCQ, and VPP1 must share the same supply when all three are between 2.7 V and 3.6 V.
8.3 Capacitance(1)
TA = +25 °C, f = 1 MHz
NOTE: 1. Sampled, not 100% tested.
Symbol Parameter Notes Min Max Unit
TAOperating Temperature –40 +85 °C
VCC1 VCC Supply Voltage 1 2.7 2.85 V
VCC2 VCC Supply Voltage 1 2.7 3.3 V
VCC3 VCC Supply Voltage 1,4 2.7 3.6 V
VCCQ1 I/O Voltage 1,2 1.65 2.5 V
VCCQ2 I/O Voltage 1,2 1.8 2.5 V
VCCQ3 I/O Voltage 1,2,4 2.7 3.6 V
VCCQ4 I/O Voltage 1 4.75 5.25 V
VPP1 VPP Supply Voltage 1 2.7 3.6 V
VPP2 VPP Supply Voltage 1,4 11.4 12.6 V
Cycling Block Erase Cycling 3 100,000 Cycles
Symbol Parameter Typ Max Unit Condition
CIN Input Capacit ance 6 8 pF VIN = 0.0 V
COUT Output Capacitance 8 12 pF VOUT = 0.0 V
28F800F3 and 28F160F3
32
8.4 DC Characteristics—Extended Temperature(1)
Sym Parameter
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Unit Test ConditionsVCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V
Note Typ Max Typ Max Typ Max
ILI Input Load Current 2 ± 1 ± 1 ± 1 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
ILO
Output Leakage
Current 2± 10 ± 10 ± 10 µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or GND
Output Leakage
Current for WAIT# ± 25 ± 25 ± 25
Iccs VCC Standby Current 3 30 75 20 75 150 250 µA VCC = VCCMax
CE# = RST # = VCC
ICCR VCC Read Current
3 456030454055mA
Asynchronous
tAVQV = Min
VIN = VIH or VIL
CE# = VIL
OE# = VIH
45 60 30 45 40 55 mA
Synchronous
CLK = 33 MHz
CE# = VIL
OE# = VIH
Burst length = 8 Word
ICCW VCC Program Current 3,4 8 20 8 20 8 20 mA VPP = VPP1 or VPP2
Program in Progress
ICCE VCC Erase Current 3,4 8 20 8 20 8 20 mA VPP = VPP1 or VPP2
Erase in Progress
IPPR VPP Read Current 2±15 2 ±15 2 ±15 µA VPP
≤ VCC
2,3 50 200 50 200 50 200 µA VPP > VCC
IPPW VPP Program Current
2,4,5103510351035mA
V
PP =VPP1
Program in Progress
210210210mA
V
PP = VPP2
Program in Progress
IPPE VPP Erase Current
2,4,5122513251325mA
V
PP = VPP1
Program in Progress
825825825mA
V
PP = VPP2
Program in Progress
IPPES
IPPWS
VPP Erase Suspend
Current 2,3 50 200 50 200 50 200 µA VPP = VPP1 or VPP2
Program or Erase
Suspend in Progress
ICCWS
ICCES
VCC Program Suspend
or Block Erase
Suspend Current 1,8 95 95 250 µA VCC = VCCMax
CE# = RST# = VCC
WP# = Vcc or GND
28F800F3 and 28F160F3
33
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at normal VCC, TA = +25 °C.
2. Applying VPP = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the
main blocks and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours
maximum.
3. The specification is the sum of VCC and VCCQ currents.
4. Erases and program operations are inhibited when VPP ≤ VPPLK, and not guaranteed outside the valid VPP
ranges of VPP1 and VPP2.
5. Sampled, not 100% tested.
6. ICCES is specified with device deselected. If device is read while in erase suspend, current draw is sum of
ICCES and ICCR.
7. Automatic Powe r Savings (AP S) reduces ICCR to approximate standby levels, in static operation.
8. ICCWS and ICCES are specified with the evice disabled. If the device is read or written while in suspend mode,
the device’s current draw is ICCR or ICCW.
DC Characteristics, Continued
VCC 2.7 V–3.6 V 2.7 V–2.85 V 2.7 V–3.3 V
Sym Parameter VCCQ 2.7 V–3.6 V 1.65 V–2.5 V 1.8 V–2.5 V Unit Test Conditions
Note Min Max Min Max Min Max
VIL Input Low Voltage –0.4 0.22
*
VCC
–0.2 0.2 –0.2 0.2 V
VIH Input High Voltage 2.0 5.5 VCCQ
–
0.2
VCCQ
+
0.2
VCCQ
–
0.2
VCCQ
+
0.2 V
VOL Output Low Voltage 0.10 -0.10 0.10 -0.10 0.10 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High Voltage VCCQ
–
0.1 VCCQ
–
0.1 VCCQ
–
0.1 V
V
CC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-Out Voltage 4 1.5 1.5 1.5 V Complete Write
Protection
VPP1
VPP during Program
and Erase Operations
62.73.6 V
V
PP2 6 2.7 2.85 V
VPP3 62.73.3V
V
PP4 6,7 11.4 12.6 11.4 12.6 11.4 12.6 V
VLKO VCC Prog/Erase Lock
Voltage 1.5 1.5 1.5 V
VLKO2 VCCQ Prog/Erase Lock
Voltage 1.2 1.2 1.2 V
28F800F3 and 28F160F3
34
NOTE: AC test inputs are driven at VCCQ min. for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed
conditions are when VCCQ = 2.7 V.
NOTE: See table for component values.
NOTE: CL includes jig capacitance.
Figure 14. AC Input/Output Reference Waveform for VCC = 2.7 V—3. 6 V
VCCQ
0V
VCCQ/2 VCCQ/2
Test P oints
Input Output
Figure 15. AC Equivalent Testing Load Circuit
Device
Under Test
V
CCQ
C
L
R
2
R
1
Out
Test Configuration CL (pF) R1 (Ω)R2 (Ω)
2.7 V Standard Test 50 25K 25K
1.65 V Standard Test 50 16.7K 16.7K
28F800F3 and 28F160F3
35
8.5 AC Characteristics—Read-Only Operations(1,2)—Extended
Temperature
NOTES:
1. See Figure 14, “AC Input/Output Reference Waveform for VCC = 2.7 V—3. 6 V” on page 34 for timing
measurements and maximum allowable input slew rate.
2. Data bus voltage must be less than or equal to VCCQ when a read operation is initiated to guarantee AC
specifications.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is defined as tCHAX or tVHAX, whichever timing specification is
satisfied first.
5. OE# may be delayed up to tELQV–tGLQV after the falling edge of CE# without impact on tELQV.
6. ADV# tied to ground, tEHEL (CE# High Pulse Width) must be held high for a minimum of 15 ns.
# Symbol Parameter
Product –95 –120
UnitVCC 3.0 V— 3.6 V 2.7 V— 3.6 V 2.7 V— 3.6 V
Notes Min Max Min Max Min Max
R1 tCLK CLK Period 15 15 15 ns
R2 tCH(tCL) CLK High (Low) Time 2.5 2.5 2.5 ns
R3 tCHCL CLK Fall (Rise) Ti me 5 5 5 ns
R4 tAVCH Address Valid Setup to CLK 7 7 7 ns
R5 tVLCH ADV# Low Setup to CLK 7 7 7 ns
R6 tELCH CE# Low Setup to CLK 11 11 11 ns
R7 tCHQV CLK to Output Delay 15 19 23 ns
R8 tCHQX Output Hold from CLK 3 3 3 3 ns
R9 tCHAX Address Hold from CLK 4 10 10 10 ns
R10 tCHTL CLK to WA IT# delay 14 16 23 ns
R11 tAVVH Address Setup to ADV# High 10 10 10 ns
R12 tELVH CE# Low to ADV# High 10 10 10 ns
R13 tAVQV Address to Output Delay 90 95 120 ns
R14 tELQV CE# Low to Output Delay 5 90 95 120 ns
R15 tVLQV ADV# Low to Output Delay 90 95 120 ns
R16 tVLVH A DV# Pulse W idth Low 10 10 10 ns
R17 tVHVL ADV# Pulse Width High 10 10 10 ns
R18 tVHAX Address Hold from ADV# High 3 3 3 ns
R19 tAPA Page Address Access Time 25 27 35 ns
R20 tGLQV OE# Low to Output Delay 25 25 30 ns
R21 tPHQV RST# High to Output Delay 600 600 600 ns
R22 tEHQZ
tGHQZ CE# or OE# High to Output in
High Z, Whichever Occurs First 3151515ns
R23 tOH Output Hold from Address, CE#,
or OE# Change, Whichever
Occurs First 3000ns
R24 tEHEL CE# High Pulse Width 6 0 0 0 ns
28F800F3 and 28F160F3
36
Figure 16. AC Waveform for CLK Input
Figure 17. AC Waveform for Single Asynchronous Read Operations from Parameter Blocks,
Status Register, Identifier Codes
R1
R2
R3
CLK (C)
R18
A
19-0
(A)
V
IH
V
IL
Valid
Address
R11
R13
R20 R23
DQ
15-0
(D/Q)
RST# (R)
R21
V
IH
V
IL
V
OH
V
OL
Valid
Output
High Z
OE# (G)
WE# (W)
V
IH
V
IL
V
IH
V
IL
WAIT# (T)
V
OH
V
OL
R15
R16
ADV# (V)
V
IH
V
IL
R17
R12
R14
R22
CE# (E)
V
IH
V
IL
28F800F3 and 28F160F3
37
Figure 18. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks
R18
R11
R15
R13
R22
A19-2 (A)
A1-0 (A)
ADV# (V)
CE# (E) VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Valid
Address Valid
Address Valid
Address
Valid
Address
Valid
Address
R14
OE# (G)
WE# (W)VIH
VIL
VIH
VIL
WAIT# (T)VOH
VOL
R20 R19 R23
DQ15-0 (D/Q)
RST# (R)
R21
VIH
VIL
VOH
VOL
Valid
Out
p
ut Valid
Out
p
ut Valid
Out
p
ut Valid
Out
p
ut
Hi
g
h Z
R17
28F800F3 and 28F160F3
38
NOTES:
1. 1.Depending upon the frequency configuration code value in the read configuration register, insert clock
cycles:
• Frequency Configuration 2 insert two clock cycles
• Frequency Configuration 3 insert three clock cycles
• Frequency Configuration 4 insert four clock cycles
• Frequency Configuration 5 insert five clock cycles
• Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 19. AC Waveform for Single Synchronous Read Operations from Parameter Blocks,
Status Register, Identifier Codes
V
IH
V
IL
CLK [C]
A
19-0
[A]
V
IH
V
IL
R4
R12
R18
R11
R16
R22
ADV# [V]
CE# [E]
V
IH
V
IL
V
IH
V
IL
R6
R5
OE# [G]
WE# [W]
V
IH
V
IL
V
IH
V
IL
WAIT# [T]
V
OH
V
OL
R20
R7
R23
DQ
15-0
[D/Q]
V
OH
V
OL
R9
R13
R15
R14
R8
Valid
Address
High Z Valid
Output
R17
Note 1
28F800F3 and 28F160F3
39
NOTES:
1. 1.Depending upon the frequency configuration code value in the read configuration register, insert clock
cycles:
• Frequency Configuration 2 insert two clock cycles
• Frequency Configuration 3 insert three clock cycles
• Frequency Configuration 4 insert four clock cycles
• Frequency Configuration 5 insert five clock cycles
• Frequency Configuration 6 insert six clock cycles
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 20. AC Waveform for Synchronous Burst Read Operations, Four-Word Burst Length,
from Main Blocks
V
IH
V
IL
CLK (C) Note 1
A
19-0
(A)
V
IH
V
IL
Valid
Address
R4
R18
R11
R9
R12
R16
R22
ADV# (V)
CE# (E)
V
IH
V
IL
V
IH
V
IL
R6
R5
OE# (G)
WE# (W)
V
IH
V
IL
V
IH
V
IL
WAIT# (T)
V
OH
V
OL
R20 R7
R8 R23
DQ
15-0
(D/Q)
V
OH
V
OL
Valid
Output Valid
Output Valid
Output Valid
Output
High Z
R17
28F800F3 and 28F160F3
40
NOTES:
1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further
information about burst length configuration.
2. WAIT# is configurable. It can be set to assert during or one CLK cycle before an output delay.
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
NOTES:
1. This delay will only occur when burst length is configured as continuous. See Section 4.9.7 for further
information about burst length configuration.
2. WA IT# is configurable. It can be set to assert during or two CLK cycles before an output delay.
See Section 4.9.2 for further information about the frequency configuration and its effect on the initial read.
Figure 21. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data
Output Configuration Set to One Clock
V
IH
V
IL
CLK (C) Note 1
A
19-0
(A)
ADV# (V)
CE# (E)
OE# (G)
WE# (W)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
WAIT# (T)
V
OH
V
OL
DQ
15-0
(D/Q)
V
OH
V
OL
Valid
Output Valid
Output Valid
Output
High Z
Valid
Output
Valid
Output
R7
R10 R10
Note 2
Figure 22. AC Waveform for Continuous Burst Read, Showing an Output Delay with Data
Output Configuration Set to Two Clocks
V
IH
V
IL
CLK (C) Note 1
A
19-0
(A)
ADV# (V)
CE# (E)
OE# (G)
WE# (W)
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
WAIT# (T)
V
OH
V
OL
DQ
15-0
(D/Q)
V
OH
V
OL
Valid
Output
High Z
Valid
Output
R7
R10
Note 2
R10
28F800F3 and 28F160F3
41
8.6 AC Characteristics—Write Operations(1, 2)—Extended
Temperature
NOTES:
1. See Figure 14, “AC Input/Output Reference Waveform for VCC = 2.7 V—3. 6 V” on page 34 for timing
measurements and maximum allowable input slew rate.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse wi dth (t WP) is defined from CE# or WE# going low (whichever goes low l ast) to CE# or WE# going
high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 3 for valid AIN and DIN for block erase or program.
6. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or
WE# going low (whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
7. tWHGL is 15 ns u nless resuming a program suspend or erase suspend command; then 30 ns is required
before read can be commenced.
8. VPP should be held at VPPH1 or VPPH2 until determination of block erase or program success.
# Sym Parameter
Valid for All Speed and
Voltage Combinations Unit
Notes Min Max
W1 tPHWL (tPHEL) RST# High Recovery to WE# (CE#) Going Low 3 600 ns
W2 tELWL (tWLEL) CE# (WE#) Setup to WE# (CE#) Going Low 4 0 ns
W3 tWP (tWLWH) Write Pulse Width 4 75 ns
W4 tVLVH ADV# Pulse Width 10 ns
W5 tDVWH (tDVEH) Data Setup to WE# (CE#) Going High 5 70 ns
W6 tAVWH (tAVEH) Address Setup to WE# (CE#) Going High 5 75 ns
W7 tVLEH (tVLWH) ADV# Setup to WE# (CE#) Going High 75 ns
W8 tAVVH Address Setup to ADV# Going High 10 ns
W9 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 ns
W10 tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 ns
W11 tWHAX (tEHAX) Address Hold from WE# (CE#) High 0 ns
W12 tVHAX Addr ess Hold from ADV# Going High 3 ns
W13 tWPH (tWHWL) Write Pulse Width High 6 20 ns
W14 tBHWH (tBHEH) WP# Setup to WE# (CE#) Going High 3 200 ns
W15 tVPWH (tVPEH)V
PP Setup to WE# (CE#) Going High 3 200 ns
W16 tWHGL (tEHGL) Write Recovery before Read 7 15 ns
W17 tQVBL WP# Hold from Valid SRD 3,8 0 ns
W18 tQVVL VPP Hold from Valid SRD 3,8 0 ns
28F800F3 and 28F160F3
42
NOTES:
1. VCC power-up and standby.
2. Write block erase or program setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. For read operations, OE# and CE# must be driven active, and WE# de-asserted.
Figure 23. AC Waveform for Write Operations
Valid Address Valid Address
W6
W11W12
W3
W5
W10
W9W2
W1 W13
Data InData In Valid
SRD
W4
W7
W8
W16
A
20-0
(A)
V
IH
V
IL
ADV# (V)
V
IH
V
IL
CE# (WE#) [E(W)]
V
IH
V
IL
OE# [G]
V
IH
V
IL
WE# (CE#) [W(E)]
V
IH
V
IL
DATA [D/Q]
V
IH
V
IL
Note 6
Note 6
Note 1 Note 2 Note 3 Note 4 Note 5
RST# [P]
V
IH
V
IL
W15 W18
V
PP
[V]
V
PPH1/2
V
PPLK
V
IL
WP# [B]
V
IH
V
IL
W14 W17
W19
28F800F3 and 28F160F3
43
8.7 AC Characteristics—Reset Operation—Extended
Temperature
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
3. Sampled, but not 100% tested.
4. If RST# is asserted while a block erase or word program operation is not executing, the reset will complete
within 100 ns.
Figure 24. AC Waveform for Reset Operation
Table 10. Reset Specifications(1)
Number Symbol Parameter Notes Min Max Unit
P1 tPLPH RST# Low to Reset during Read
(If RST# is tied to VCC, this specification is not applicable) 2,3 100 ns
P2 tPLRH RST# Low to Reset during Block Erase or Program 3,4 22 µs
(A) Reset while device is in read mode
RST# (R)
V
IH
V
IL
P1
R20
RST# (R)
V
IH
V
IL
P1
P2 R20
RST# (R)
V
IH
V
IL
P1
P2 R20
(B) Reset during program or block erase, P1
≤
P2
(C) Reset during program or block erase, P1
≥
P2
Abort
Complete
Abort
Complete
28F800F3 and 28F160F3
44
8.8 Extended Te mperature Block Erase and Program
Performance(1,2,3)
NOTES:
1. These performance numbers are valid for all speed versions.
2. Sampled, but not 100% tested.
3. Reference the Figure 23, “AC Waveform for Write Operations” on page 42.
4. Typical values measured at TA = +25 °C and nominal voltages. Subject to change based on device
characterization.
5. Excludes system-level overhead.
# Sym Parameter Notes 2.7 V-3.6 V VPP 11.4 V-12.6 V VPP Unit
Typ(4) Max Typ(4) Max
W19
tWHRH1, tEHRH1
Program Time 5 23.5 200 8 185 µs
Block Program Time (Parameter) 5 0.10 0. 30 0. 0 3 0.10 sec
Block Program Time (Main) 5 0.8 2.4 0.24 0.8 s ec
tWHRH2, tEHRH2
Block Erase Time (Parameter) 5 1 4 0.8 4 sec
Block Erase T ime (Main) 5 1.8 5 1.1 5 sec
tWHRH5, tEHRH5 Program Suspend Latency 6 10 5 10 µs
tWHRH6, tEHRH6 Erase Suspe nd Time 13 20 10 12 µs
28F800F3 and 28F160F3
45
9.0 Ordering Information
NOTE: 1. The 56-ball µBGA package topside mark reads F160F3. All product shipping boxes or trays provide
the correct information regarding bus architecture.
Valid Combinations
56-Lead SSOP 56-Lead TSOP 8 x 8 Easy BGA 56-Ball µBGA CSP(1)
Extended 16 M
DT28F160F3T120 TE28F160F3T120 RC28F160F3T120 GT28F160F3T120
DT28F160F3B120 TE28F160F3B120 RC28F160F3B120 GT28F160F3B120
DT28F160F3T95 TE28F160F3T95 RC28F160F3T95 GT28F160F3T95
DT28F160F3B95 TE28F800F3B95 RC28F800F3B95 GT28F800F3B95
Extended 8 M
DT28F800F3T120 TE28F800F3T120 RC28F800F3T120
DT28F800F3B120 TE28F800F3B120 RC28F800F3B120
DT28F800F3T95 TE28F800F3T95 RC28F800F3T95
DT28F800F3B95 TE28F800F3B95 RC28F800F3B95
D T 2 8 F 1 6 0 F 3 T 1 2 0
Package
DT = Extende d tem p. ,
56-Lead SSOP
GT = Extend ed tem p .,
56-Ball µBGA* CSP
TE = Extended temp.,
56-Lead TSOP
RC = Extended temp.,
Easy BGA
Product line designator
for a ll Intel
®
Flash products
Access S pe ed (ns)
(120,150)
Product Family
F3 = 3 Volt Fas t Boot Block
V
CC
= 2.7 V - 3.6 V
V
PP
= 2.7 V - 3.6 V or
11.4 V - 12.6 V
De vice Density
160 = x16 (16-Mb it )
800 = x16 (8-Mbi t)
T =
Top Blocking
B =
Bottom Blocki ng
28F800F3 and 28F160F3
46
10.0 Additional Information
NOTES:
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International
customers should contact their local Intel or distribution sales office.
Visit Intel’s World Wide Web home page at http://www.intel.com or http://developer.intel.com for technical
documentation and tools.
Order Number Document/Tool
297939
3 Volt Fast Boot Block Flash Memory Specification Update
210830
Flash Memory Databoo
k
292213
AP-655 3 Volt Fast Boot Block Design Guide
298161
Intel® Flash Memory Chip Scale Package User’s Guide
Contact your Intel
Representative
Intel® Flash Data Integrator (IFDI) Software Developer’s Kit
297874
IFDI Interactive: Play with Intel® Flash Data Integrator on Your PC
