SPI Interface, Octal SPST Switches,
13.5 Ω RON, ±20 V/+36 V, Mux
Data Sheet ADGS5414
Rev. 0 Document Feedback
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FEATURES
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst and daisy-chain mode
Industry-standard SPI Mode 0 and Mode 3 interface-
compatible
Guaranteed break-before-make switching, allowing external
wiring of switches to deliver multiplexer configurations
VSS to VDD analog signal range
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
9 V to 40 V single-supply operation (VDD)
±9 V to ±22 V dual-supply operation (VDD/VSS)
8 kV HBM ESD rating
Low on resistance
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
APPLICATIONS
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The ADGS5414 contains eight independent single-pole/single-
throw (SPST) switches. An SPI interface controls the switches
and has robust error detection features, including cyclic
redundancy check (CRC) error detection, invalid read/write
address error detection, and SCLK count error detection.
It is possible to daisy-chain multiple ADGS5414 devices together.
This enables the configuration of multiple devices with a minimal
amount of digital lines. The ADGS5414 can also operate in burst
mode to decrease the time between SPI commands.
Each switch conducts equally well in both directions when on, and
each switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
The on-resistance profile is flat over the full analog input range,
ensuring ideal linearity and low distortion when switching
audio signals. The ADGS5414 exhibits break-before-make
switching action, allowing the use of the device in multiplexer
applications with external wiring.
PRODUCT HIGHLIGHTS
1. The SPI interface removes the need for parallel conversion,
logic traces, and reduces the general-purpose input/output
(GPIO) channel count.
2. Daisy-chain mode removes the need for additional logic
traces when using multiple devices.
3. CRC error detection, invalid read/write address error
detenction, and SCLK count error detection ensures a
robust digital interface.
4. CRC and error detection capabilities allow the use of the
ADGS5414 in safety critical systems.
5. Break-before-make switching allows external wiring of the
switches to deliver multiplexer configurations.
6. The trench isolation analog switch section guards against
latch-up. A dielectric trench separates the positive and
negative channel transistors, preventing latch-up even under
severe overvoltage conditions.
SCLK SDI CS RESET/V
L
ADGS5414
SPI
INTERFACE
S1 D1
S2 D2
S3 D3
S4 D4
S5 D5
S6 D6
S7 D7
S8 D8
SDO
15902-001
ADGS5414 Data Sheet
Rev. 0 | Page 2 of 30
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 1
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 5
12 V Single Supply ........................................................................ 7
36 V Single Supply ........................................................................ 9
Continuous Current per Channel, Sx or Dx Pins .................. 11
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings .......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution ................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 15
Test Circuits ..................................................................................... 19
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Address Mode ............................................................................. 22
Error Detection Features ........................................................... 22
Clearing the Error Flags Register ............................................. 23
Burst Mode .................................................................................. 23
Software Reset ............................................................................. 23
Daisy-Chain Mode ..................................................................... 23
Power-On Reset .......................................................................... 24
Break-Before-Make Switching .................................................. 25
Trench Isolation .......................................................................... 25
Applications Information .............................................................. 26
Power Supply Rails ..................................................................... 26
Power Supply Recommendations ............................................. 26
Register Summary .......................................................................... 27
Register Details ............................................................................... 28
Switch Data Register .................................................................. 28
Error Configuration Register .................................................... 28
Error Flags Register .................................................................... 29
Burst Enable Register ................................................................. 29
Software Reset Register ............................................................. 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
10/2017—Revision 0: Initial Version
Data Sheet ADGS5414
Rev. 0 | Page 3 of 30
SPECIFICATIONS
±15 V DUAL SUPPLY
Digital logic voltage (VDD) = +15 V ± 10%, negative supply voltage (VSS) = −15 V ± 10%, positive supply voltage (VL) = 2.7 V to 5.5 V,
GND = 0 V, unless otherwise noted.
Table 1.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 13.5 Ω typ Source voltage (VS) = ±10 V,
IS = −10 mA; see Figure 29
15 18 22 Ω max VDD = +13.5 V, VSS = −13.5 V
On-Resistance Match Between Channels,
∆RON
0.3 Ω typ VS = ±10 V, source current
(IS) = −10 mA
0.8 1.3 1.4 Ω max
On-Resistance Flatness, RFLAT (ON) 1.8 Ω typ VS = ±10 V, IS = −10 mA
2.2 2.6 3 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = ±10 V, VD = ±10 V;
see Figure 32
±0.25 ±1 ±7 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = ±10 V, VD = ±10 V;
see Figure 32
±0.25 ±1 ±7 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = ±10 V; see Figure 28
±0.4 ±2 ±14 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max Sink current (ISINK) = 5 mA
0.2 V max ISINK = 1 mA
Output Current, Low (IOL) or High (IOH) 0.001 μA typ Output voltage (VOUT) =
ground voltage (VGND)or VL
±0.1 μA max
Digital Output Capacitance, COUT 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, Low (IINL) or High (IINH) 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS
tON 410 ns typ Load resistance (RL) = 300 Ω,
load capacitance (CL) = 35 pF
420 515 515 ns max VS = 10 V; see Figure 37
tOFF 135 ns typ RL = 300 Ω, CL = 35 pF
140 185 195 ns max VS = 10 V; see Figure 37
Break-Before-Make Time Delay, tD 260 ns typ RL = 300 Ω, CL = 35 pF
250 210 ns min VS1 = VS2 = 10 V; see Figure 36
Charge Injection, QINJ 125 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
ADGS5414 Data Sheet
Rev. 0 | Page 4 of 30
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF,
frequency (f) = 1 MHz; see
Figure 32
Channel to Channel Crosstalk −75 dB typ RL = 50 Ω, CL = 5 pF, f =
1 MHz; see Figure 30
Total Harmonic Distortion + Noise
(THD + N)
0.01 % typ RL = 1 kΩ, 15 V p-p, f = 20
Hz to 20 kHz; see Figure 33
−3 dB Bandwidth 200 MHz typ RL = 50 Ω, CL = 5 pF; see
Figure 34
Insertion Loss −0.9 dB typ RL = 50 Ω, CL = 5 pF, f =
1 MHz; see Figure 34
Source Capacitance (CS) (Off) 11 pF typ VS = 0 V, f = 1 MHz
Drain Capacitance(CD) (Off) 11 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 30 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V
Positive Supply Current (IDD) 45 μA typ All switches open
70 μA max All switches open
45 μA typ All switches closed, VL = 5.5 V
70 μA max All switches closed, VL = 5.5 V
310 μA typ All switches closed, VL = 2.7 V
430 μA max All switches closed, VL = 2.7 V
IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max
SCLK = 1 MHz 14 μA typ CS and SDI = 0 V or VL, VL = 5
V
7 μA typ
CS and SDI = 0 V or VL, VL =
3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL,
VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL
= 5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL
= 3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL
= 5 V
120 μA typ
CS and SCLK = 0 V or VL, VL
= 3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle
between 0 V and VL, VL =
5.5 V
2 2.1 mA max
0.7 mA typ
Digital inputs toggle
between 0 V and VL, VL = 2.7 V
1.0 mA max
Negative Supply Current (ISS) 0.05 μA typ Digital inputs = 0 V or VL
1.0 μA max
Dual-Supply Operation (VDD/VSS) ±9 V min GND = 0 V
±22 V max GND = 0 V
Data Sheet ADGS5414
Rev. 0 | Page 5 of 30
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VDD to VSS V
On Resistance, RON 12.5 Ω typ
VS = ±15 V, IS = −10 mA;
see Figure 29
14 17 21 Ω max VDD = +18 V, VSS = −18 V
On-Resistance Match Between
Channels, ∆RON
0.3 Ω typ VS = ±15 V, IS = −10 mA
0.8 1.3 1.4 Ω max
On-Resistance Flatness, RFLAT (ON) 2.3 Ω typ VS = ±15 V, IS = −10 mA
2.7 3.1 3.5 Ω max
LEAKAGE CURRENTS VDD = +22 V, VSS = −22 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = ±15 V, VD = ±15 V;
see Figure 32
±0.25 ±1 ±7 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = ±15 V, VD = ±15 V;
see Figure 32
±0.25 ±1 ±7 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = ±15 V; see Figure 28
±0.4 ±2 ±14 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
Output Current, IOL or IOH 0.001 μA typ VOUT = VGND or VL
±0.1 μA max
Digital Output Capacitance, COUT 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS
tON 410 ns typ RL = 300 Ω, CL = 35 pF
418 485 495 ns max VS = 10 V; see Figure 37
tOFF 135 ns typ RL = 300 Ω, CL = 35 pF
144 185 195 ns max VS = 10 V; see Figure 37
Break-Before-Make Time Delay, tD 255 ns typ RL = 300 Ω, CL = 35 pF
245 205 ns min VS1 = VS2 = 10 V; see Figure 36
Charge Injection, QINJ 160 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 34
Channel to Channel Crosstalk −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
(THD + N) 0.012 % typ RL = 1 kΩ, 20 V p-p, f = 20 Hz to
20 kHz; see Figure 33
ADGS5414 Data Sheet
Rev. 0 | Page 6 of 30
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
−3 dB Bandwidth 200 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 34
Insertion Loss −0.8 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 34
CS (Off) 11 pF typ VS = 0 V, f = 1 MHz
CD (Off) 11 pF typ VS = 0 V, f = 1 MHz
CD (On), CS (On) 30 pF typ VS = 0 V, f = 1 MHz
POWER REQUIREMENTS VDD = +22 V, VSS = −22 V
IDD 50 μA typ All switches open
110 μA max All switches open
50 μA typ All switches closed, VL = 5.5 V
110 μA max All switches closed, VL = 5.5 V
320 μA typ All switches closed, VL = 2.7 V
450 μA max All switches closed, VL = 2.7 V
IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max
SCLK = 1 MHz 14 μA typ CS and SDI = 0 V or VL, VL = 5 V
7 μA typ
CS and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL,
VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL = 5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL = 5 V
120 μA typ
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle between
0 V and VL, VL = 5.5 V
2 2.1 mA max
0.7 mA typ
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0 mA max
ISS 0.05 μA typ Digital inputs = 0 V or VL
1.0 μA max
Dual-Supply Operation (VDD/VSS) ±9 V min GND = 0 V
±22 V max GND = 0 V
Data Sheet ADGS5414
Rev. 0 | Page 7 of 30
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 26 Ω typ
VS = 0 V to 10 V, IS = −10 mA;
see Figure 29
30 36 42 Ω max VDD = 10.8 V, VSS = 0 V
On-Resistance Match Between Channels,
∆RON
0.3 Ω typ VS = 0 V to 10 V, IS = −10 mA
1 1.5 1.6 Ω max
On-Resistance Flatness, RFLAT (ON) 5.5 Ω typ VS = 0 V to 10 V, IS = −10 mA
6.5 8 12 Ω max
LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 32
±0.25 ±1 ±7 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 32
±0.25 ±1 ±7 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = 1 V/10 V; see
Figure 28
±0.4 ±2 ±14 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
Output Current, IOL or IOH 0.001 μA typ VOUT = VGND or VL
±0.1 μA max
Digital Output Capacitance, COUT 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS
tON 450 ns typ RL = 300 Ω, CL = 35 pF
455 555 575 ns max VS = 8 V; see Figure 37
tOFF 135 ns typ RL = 300 Ω, CL = 35 pF
141 195 205 ns max VS = 8 V; see Figure 37
Break-Before-Make Time Delay, tD 285 ns typ RL = 300 Ω, CL = 35 pF
275 225 ns min VS1 = VS2 = 8 V; see Figure 36
Charge Injection, QINJ 55 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
Channel to Channel Crosstalk −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
ADGS5414 Data Sheet
Rev. 0 | Page 8 of 30
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
THD +N 0.1 % typ RL = 1 kΩ, 6 V p-p, f = 20 Hz
to 20 kHz; see Figure 33
−3 dB Bandwidth 220 MHz typ RL = 50 Ω, CL = 5 pF; see
Figure 34
Insertion Loss −1.55 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 34
CS (Off) 12 pF typ VS = 6 V, f = 1 MHz
CD (Off) 12 pF typ VS = 6 V, f = 1 MHz
CD (On), CS (On) 30 pF typ VS = 6 V, f = 1 MHz
POWER REQUIREMENTS VDD = 13.2 V
IDD 40 μA typ All switches open
65 μA max All switches open
40 μA typ All switches closed, VL = 5.5 V
65 μA max All switches closed, VL = 5.5 V
300 μA typ All switches closed, VL = 2.7 V
420 μA max All switches closed, VL = 2.7 V
IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max
SCLK = 1 MHz 14 μA typ CS and SDI = 0 V or VL, VL = 5 V
7 μA typ
CS and SDI = 0 V or VL, VL = 3 V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL,
VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL =
5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL =
3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL =
5 V
120 μA typ
CS and SCLK = 0 V or VL, VL =
3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle
between 0 V and VL, VL =
5.5 V
2 2.1 mA max
0.7 mA typ
Digital inputs toggle
between 0 V and VL, VL =
2.7 V
1.0 mA max
Single-Supply Operation (VDD) 9 V min GND = 0 V, VSS = 0 V
40 V max GND = 0 V, VSS = 0 V
Data Sheet ADGS5414
Rev. 0 | Page 9 of 30
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V
On Resistance, RON 14.5 Ω typ
VS = 0 V to 30 V, IS = −10 mA;
see Figure 29
16 19 23 Ω max VDD = 32.4 V, VSS = 0 V
On-Resistance Match Between Channels,
∆RON
0.3 Ω typ VS = 0 V to 30 V, IS = −10 mA
0.8 1.3 1.4 Ω max
On-Resistance Flatness, RFLAT(ON) 3.5 Ω typ VS = 0 V to 30 V, IS = −10 mA
4.3 5.5 6.5 Ω max
LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off) ±0.1 nA typ VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 32
±0.25 ±1 ±7 nA max
Drain Off Leakage, ID (Off) ±0.1 nA typ VS = 1 V/30 V, VD = 30 V/1 V;
see Figure 32
±0.25 ±1 ±7 nA max
Channel On Leakage, ID (On), IS (On) ±0.15 nA typ VS = VD = 1 V/30 V; see
Figure 28
±0.4 ±2 ±14 nA max
DIGITAL OUTPUT
Output Voltage
Low, VOL 0.4 V max ISINK = 5 mA
0.2 V max ISINK = 1 mA
Output Current, IOL or IOH 0.001 μA typ VOUT = VGND or VL
±0.1 μA max
Digital Output Capacitance, COUT 4 pF typ
DIGITAL INPUTS
Input Voltage
High, VINH 2 V min 3.3 V < VL ≤ 5.5 V
1.35 V min 2.7 V ≤ VL ≤ 3.3 V
Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V
0.8 V max 2.7 V ≤ VL ≤ 3.3 V
Input Current, IINL or IINH 0.001 μA typ VIN = VGND or VL
±0.1 μA max
Digital Input Capacitance, CIN 4 pF typ
DYNAMIC CHARACTERISTICS
tON 425 ns typ RL = 300 Ω, CL = 35 pF
435 515 515 ns max VS = 18 V; see Figure 37
tOFF 145 ns typ RL = 300 Ω, CL = 35 pF
151 195 195 ns max VS = 18 V; see Figure 37
Break-Before-Make Time Delay, tD 260 ns typ RL = 300 Ω, CL = 35 pF
245 205 ns min
VS1 = VS2 = 18 V; see Figure
36
Charge Injection, QINJ 145 pC typ
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 38
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
Channel to Channel Crosstalk −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1
MHz; Figure 30
ADGS5414 Data Sheet
Rev. 0 | Page 10 of 30
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
THD + N 0.04 % typ RL = 1 kΩ, 18 V p-p, f = 20 Hz
to 20 kHz; see Figure 33
−3 dB Bandwidth 200 MHz typ RL = 50 Ω, CL = 5 pF; see
Figure 34
Insertion Loss −0.85 dB typ RL = 50 Ω, CL = 5 pF, f = 1
MHz;
see Figure 34
CS (Off) 11 pF typ VS = 18 V, f = 1 MHz
CD (Off) 11 pF typ VS = 18 V, f = 1 MHz
CD (On), CS (On) 26 pF typ VS = 18 V, f = 1 MHz
POWER REQUIREMENTS VDD = 39.6 V
IDD 80 μA typ All switches open
130 μA max All switches open
80 μA typ All switches closed, VL = 5.5 V
130 μA max All switches closed, VL = 5.5 V
330 μA typ All switches closed, VL = 2.7 V
490 μA max All switches closed, VL = 2.7 V
IL
Inactive 6.3 μA typ Digital inputs = 0 V or VL
8.0 μA max
SCLK = 1 MHz 14 μA typ CS and SDI = 0 V or VL, VL = 5
V
7 μA typ
CS and SDI = 0 V or VL, VL = 3
V
SCLK = 50 MHz 390 μA typ CS = VL and SDI = 0 V or VL,
VL = 5 V
210 μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
SDI = 1 MHz 15 μA typ CS and SCLK = 0 V or VL, VL =
5 V
7.5 μA typ
CS and SCLK = 0 V or VL, VL =
3 V
SDI = 25 MHz 230 μA typ CS and SCLK = 0 V or VL, VL =
5 V
120 μA typ
CS and SCLK = 0 V or VL, VL =
3 V
Active at 50 MHz 1.8 mA typ Digital inputs toggle
between 0 V and VL, VL = 5.5 V
2 2.1 mA max
0.7 mA typ
Digital inputs toggle
between 0 V and VL, VL = 2.7 V
1.0 mA max
Single-Supply Operation (VDD) 9 V min GND = 0 V, VSS = 0 V
40 V max GND = 0 V, VSS = 0 V
Data Sheet ADGS5414
Rev. 0 | Page 11 of 30
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx Pins
Table 5. Eight Channels On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx PINS
VDD = +15 V, VSS = −15 V (θJA = 50°C/W) 82 61 38 mA maximum
VDD = +20 V, VSS = −20 V (θJA = 50°C/W) 86 63 41 mA maximum
VDD = 12 V, VSS = 0 V (θJA = 50°C/W) 63 47 29 mA maximum
VDD = 36 V, VSS = 0 V (θJA = 50°C/W) 85 62 40 mA maximum
Table 6. One Channel On
Parameter 25°C 85°C 125°C Unit
CONTINUOUS CURRENT, Sx OR Dx PINS
VDD = +15 V, VSS = −15 V (θJA = 50°C/W) 199 124 75 mA maximum
VDD = +20 V, VSS = −20 V (θJA = 50°C/W) 210 129 77 mA maximum
VDD = 12 V, VSS = 0 V (θJA = 50°C/W) 157 104 68 mA maximum
VDD = 36 V, VSS = 0 V (θJA = 50°C/W) 206 127 76 mA maximum
TIMING SPECIFICATIONS
VL = 2.7 V to 5.5 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter Limit Unit Test Conditions/Comments
TIMING CHARACTRISTICS
t1 20 ns min SCLK period
t2 8 ns min SCLK high pulse width
t3 8 ns min SCLK low pulse width
t4 10 ns min CS falling edge to SCLK active edge
t5 6 ns min Data setup time
t6 8 ns min Data hold time
t7 10 ns min SCLK active edge to CS rising edge
t8 20 ns max
CS falling edge to SDO data available
t91 20 ns max SCLK falling edge to SDO data available
t10 20 ns max
CS rising edge to SDO returns to high impedance
t11 20 ns min
CS high time between SPI commands
t12 8 ns min
CS falling edge to SCLK becomes stable
t13 8 ns min
CS rising edge to SCLK becomes stable
1 Measured with the 1 kΩ pull-up resistor to VL and a 20 pF load. t9 determines the maximum SCLK frequency when using SDO.
ADGS5414 Data Sheet
Rev. 0 | Page 12 of 30
Timing Diagrams
Figure 2. Addressable Mode Timing Diagram
Figure 3. Daisy Chain Timing Diagram
Figure 4. SCLK/CS Timing Diagram
t
1
t
2
t
3
t
4
t
5
t
8
t
9
t
10
t
6
t
7
R/W
CS
SCLK
SDI
SDO
A6 A5 D2 D1 D0
001 D2D1D0
15902-002
t
1
t
2
t
3
t
4
t
5
t
8
t
9
t
10
t
6
t
7
CS
SCLK
SDI
SDO
INPUT BYTE FOR DEVICE N INPUT BYTE FOR DEVICE N + 1
ZERO BYTE INPUT BYTE FOR DEVICE N
D7 D6 D0 D7 D6 D1 D0
00 0D7D6 D1D0
15902-003
t
13
t
11
t
12
CS
SCLK
15902-004
Data Sheet ADGS5414
Rev. 0 | Page 13 of 30
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 8.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND +0.3 V to −48 V
VL to GND −0.3 V to +5.75 V
Analog Inputs1 VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Digital Inputs1 −0.3 V to +5.75 V
Peak Current, Sx or Dx Pins 422 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx or Dx
Pins2
Data (see Table 5 and Table 6) +
15%
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Reflow Soldering Peak
Temperature, Pb Free
260(+0 or −5)°C
Human Body Model (HBM)
Electrostatic Discharge (ESD)
8 kV
1 Overvoltages at the Sx and Dx pins are clamped by internal diodes. Limit
current to the maximum ratings given.
2 See Table 5 and Table 6.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 9. Thermal Resistance
Package Type θJA θ
JC2 Unit
CP-24-171 50 3.28 °C/W
1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51.
2 θJCB is the junction to the bottom of the case value.
ESD CAUTION
ADGS5414 Data Sheet
Rev. 0 | Page 14 of 30
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 VDD Most Positive Power Supply Potential.
2 S1 Source Terminal 1. This pin can be an input or output.
3 D1 Drain Terminal 1. This pin can be an input or output.
4 S2 Source Terminal 2. This pin can be an input or output.
5 D2 Drain Terminal 2. This pin can be an input or output.
6 S3 Source Terminal 3. This pin can be an input or output.
7 D3 Drain Terminal 3. This pin can be an input or output.
8 S4 Source Terminal 4. This pin can be an input or output.
9 D4 Drain Terminal 4. This pin can be an input or output.
10 D5 Drain Terminal 5. This pin can be an input or output.
11 S5 Source Terminal 5. This pin can be an input or output.
12 D6 Drain Terminal 6. This pin can be an input or output.
13 S6 Source Terminal 6. This pin can be an input or output.
14 D7 Drain Terminal 7. This pin can be an input or output.
15 S7 Source Terminal 7. This pin can be an input or output.
16 D8 Drain Terminal 8. This pin can be an input or output.
17 S8 Source Terminal 8. This pin can be an input or output.
18 VSS Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
19 SDO Serial Data Output. This pin can daisy-chain a numeral ADGS5414 devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the
falling edge of SCLK. Pull this open-drain output to VL with an external resistor.
20 RESET/VL RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V
to 5.5 V supply. Pull the pin low to complete a hardware reset. All switches are opened, and the
appropriate registers are set to their default.
21 CS Active Low Control Input. This is the frame synchronization signal for the input data. When CS goes
low, it powers on the SCLK buffers and enables the input shift register. Data is transferred in on the
falling edges of the following clocks. Taking CS high updates the switch condition.
22 SCLK Serial Clock Input. Data is captured on the positive edge of SCLK . Data can be transferred at rates
of up to 50 MHz.
23 GND Ground (0 V) Reference.
24 SDI Serial Data Input. Data is captured on the positive edge of the serial clock input.
Exposed Pad
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
2
1
3
4
5
6
18
17
16
15
14
13
S3
D2
S2
D1
S1
V
DD
S6
D7
S7
D8
S8
V
SS
8
9
10
11
7
S4
D4
D5
S5
12
D6
D3
20
19
21
RESET/V
L
SDO
CS
22 SCLK
23 GND
24 SDI
ADGS5414
TOP VIEW
(Not to Scale)
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY,
IT IS RECOMMENDED THAT THE EXPOSED PAD BE
SOLDERED TO THE SUBSTRATE, V
SS
.
15902-005
Data Sheet ADGS5414
Rev. 0 | Page 15 of 30
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. RON as a Function of VS and VD (Dual Supply)
Figure 7. RON as a Function of VS and VD (Dual Supply)
Figure 8. RON as a Function of VS and VD (Single Supply)
Figure 9. RON as a Function of VS and VD (Single Supply)
Figure 10. RON as a Function of VS and VD for Different Temperatures, ±15 V Dual
Supply
Figure 11. RON as a Function of VS and VD for Different Temperatures, ±20 V Dual
Supply
0
5
10
15
20
25
–18 –14 –10 –6 –2 2 6 10 14 18
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= +9V
V
SS
= –9V
V
DD
= +10V
V
SS
= –10V
V
DD
= +11V
V
SS
= –11V
V
DD
= +13.5V
V
SS
= –13.5V V
DD
= +15V
V
SS
= –15V
V
DD
= +16.5V
V
SS
= –16.5V
15902-106
0
2
4
6
8
10
12
14
16
–25 –20 –15 –10 –5 0 5 10 15 20 25
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= +22V
V
SS
= –22V
V
DD
= +20V
V
SS
= –20V
V
DD
= +18V
V
SS
= –18V
15902-107
0
–5
–10
–15
–20
–25
–30
–
35
0 –2–4–6–8–10–12–14
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= 9V
V
SS
= 0V
V
DD
= 10V
V
SS
= 0V V
DD
= 10.8V
V
SS
= 0V
V
DD
= 11V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
V
DD
= 13.2V
V
SS
= 0V
15902-108
0
2
4
6
8
10
12
14
16
0 5 10 15 20 25 30 35 40 45
ON RESISTANCE ()
V
S
, V
D
(V)
T
A
= 25°C
V
DD
= 39.6V
V
SS
= 0V
V
DD
= 36V
V
SS
= 0V
V
DD
= 32.4V
V
SS
= 0V
15902-109
0
5
10
15
20
25
–15 –10 –5 0 5 10 15
ON RESISTANCE ()
V
S
, V
D
(V)
V
DD
= +15V
V
SS
= –15V
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
15902-110
0
5
10
15
20
25
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE ()
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
V
S
, V
D
(V)
V
DD
= +20V
V
SS
= –20V
15902-111
ADGS5414 Data Sheet
Rev. 0 | Page 16 of 30
Figure 12. RON as a Function of VS and VD for Different Temperatures, 12 V Single
Supply
Figure 13. RON as a Function of VS and VD for Different Temperatures, 36 V Single
Supply
Figure 14. Leakage Currents vs. Temperature, ±15 V Dual Supply
Figure 15. Leakage Currents vs. Temperature, ±20 V Dual Supply
Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply
Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply
0
5
10
15
20
25
30
35
40
024681012
V
S
, V
D
(V)
ON RESISTANCE ()
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
V
DD
= 12V
V
SS
= 0V
15902-112
0
5
10
15
20
25
0 5 10 15 20 25 30 35 40
ON RESISTANCE ()
T
A
= +125°C
T
A
= +85°C
T
A
= +25°C
T
A
= –40°C
V
S
, V
D
(V)
V
DD
= 36V
V
SS
= 0V
15902-113
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
012010080604020
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
I
S
(OFF) +, –
I
D
(OFF) –, +
I
D
(OFF) +, –
I
S
, I
D
(ON) +, +
I
S
(OFF) –, +
I
S
, I
D
(ON) –, –
V
DD
= +15V
V
SS
= –15V
V
BIAS
= +10V, –10V
15902-114
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
012010080604020
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
I
S
(OFF) +, –
I
D
(OFF) –, +
I
D
(OFF) +, –
I
S
, I
D
(ON) +, +
I
S
(OFF) –, +
I
S
, I
D
(ON) –, –
V
DD
= +20V
V
SS
= –20V
V
BIAS
= +10V, –10V
15902-115
0.20
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
012010080604020
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
I
S
(OFF) +, –
I
D
(OFF) –, +
I
D
(OFF) +, –
I
S
, I
D
(ON) +, +
I
S
(OFF) –, +
I
S
, I
D
(ON) –, –
V
DD
= +12V
V
SS
= 0V
V
BIAS
= +1V, –1V
15902-116
0.3
–0.3
–0.2
–0.1
0
0.1
0.2
012010080604020
LEAKAGE CURRENT (nA)
TEMPERATURE (°C)
I
S
(OFF) +, –
I
D
(OFF) –, +
I
D
(OFF) +, –
I
S
, I
D
(ON) +, +
I
S
(OFF) –, +
I
S
, I
D
(ON) –, –
V
DD
= 36V
V
SS
= 0V
V
BIAS
= 1V, 30V
15902-117
Data Sheet ADGS5414
Rev. 0 | Page 17 of 30
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
Figure 20. Charge Injection vs. VS
Figure 21. ACPSRR vs. Frequency, ±15 V Dual Supply
Figure 22. THD + N vs. Frequency, Dual Supply
Figure 23. Bandwidth vs. Frequency
0
–140
–120
–100
–80
–60
–40
–20
100 1k 10k 100k 1M 10M 100M 1G 10G
OFF ISOLATION (dB)
FREQUENCY (Hz)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
15902-118
0
–140
–120
–100
–80
–60
–40
–20
10k 100k 1M 10M 100M 1G
CROSSTALK (dB)
FREQUENCY (Hz)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
15902-119
300
0
50
100
150
200
250
–20 –10 403020100
CHARGE INJECTION (pC)
VS (V)
TA = 25°C
VDD = +20V, VSS = –20V
VDD = +15V, VSS = –15V
VDD = +12V, VSS = 0V
VDD = +36V, VSS = 0V
15902-120
10
–130
–110
–90
–70
–50
–30
–10
100 1k 10k 100k 1M 10M
ACPSRR (dB)
FREQUENCY (Hz)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
100nF DECOUPLING CAP
10µF + 100nF DECOUPLIG CAP
NO DECOUPLING
15902-121
0
0.02
0.04
0.06
0.08
0.10
0.12
0 5 10 15 20
THD + N (%)
FREQUENCY (kHz)
V
DD
= 12V, V
SS
= 0V, V
S
= 6V p-p
V
DD
= 36V, V
SS
= 0V, V
S
= 18V p-p
V
DD
= 15V, V
SS
= 15V, V
S
= 15V p-p
V
DD
= 20V, V
SS
= 20V, V
S
= 20V p-p
LOAD = 1k
T
A
= 25°C
15902-122
0
–5
–4
–3
–2
–1
10k 100k 1M 10M 100M 1G
BANDWIDTH (dB)
FREQUENCY (Hz)
T
A
= 25°C
V
DD
= +15V
V
SS
= –15V
15902-123
ADGS5414 Data Sheet
Rev. 0 | Page 18 of 30
Figure 24. tON and tOFF Times vs. Temperature
Figure 25. IDD vs. VL
Figure 26. Digital Feedthrough
Figure 27. IL vs. SCLK Frequency when CS is High
500
0
100
200
300
400
50
150
250
350
450
–40 –20 0 20 40 60 80 100 120
t
ON
AND
t
OFF
(ns)
TEMPE RAT URE (°C)
15V DS,
t
ON
15V DS,
t
OFF
20V DS,
t
ON
20V DS,
t
OFF
12V SS,
t
ON
12V SS,
t
OFF
36V SS,
t
ON
36V SS,
t
OFF
15902-124
120
100
80
60
40
20
0
2.7 5.55.04.54.03.53.0
I
DD
(µA)
V
L
(V)
T
A
= 25°C
I
DD
WI TH ONE SWI TCH CL O SE D V
L
+12V
±15V
±20V
+36V
15902-125
0.5
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
02468
V
OUT
(mV)
TIME (µs)
SCLK = 2.5MHz
SCLK IDLE
15902-126
0
50
100
150
200
250
300
350
400
450
01020304050
I
L
(uA)
SCL K FREQUE NCY (MHz )
V
L
= 5V
V
L
= 3V
T
A
= 25°C
15902-127
Data Sheet ADGS5414
Rev. 0 | Page 19 of 30
TEST CIRCUITS
Figure 28. On Leakage
Figure 29. On Resistance
Figure 30. Channel to Channel Crosstalk
Figure 31. Off Isolation
Figure 32. Off Leakage
Figure 33. THD + Noise
Figure 34. Bandwidth
Figure 35. ACPSRR
VD
Sx Dx
VS
A
ID (ON)
15902-026
Sx Dx
VS
V1
IDS
RON = V1/IDS
15902-027
CHANNEL TO CHANNEL CROSSTALK = 20 log V
OUT
GND
S1
D2
D1
S2
V
OUT
NETWORK
ANALYZER
R
L
50
R
L
50
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
NC
15902-028
OFF ISOLATION = 20 log V
OUT
GND
Sx
Dx
V
OUT
NETWORK
ANALYZER
R
L
50
50
50
V
S
V
S
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
15902-029
V
D
Sx Dx
V
S
A
I
D
(ON)
15902-030
GND
Sx
Dx
VOUT
AUDIO PRECISION
RL
1k
RS
VS
V p-p
VDD VSS
0.1µF
V
DD
0.1µF
VSS
15902-031
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
GND
Sx
Dx
V
OUT
NETWORK
ANALYZER
R
L
50
50
V
S
V
S
WITHOUT SWITCH
V
DD
V
SS
0.1µF
V
DD
0.1µF
V
SS
15902-032
ACPSRR = 20 log V
OUT
V
S
GND D1S1
V
OUT
NETWORK
ANALYZER
R
L
50
V
DD
V
SS
V
SS
NC
INTERNAL
BIAS
V
S
R
L
50
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE ACPSRR MEASUREMENT.
15902-033
ADGS5414 Data Sheet
Rev. 0 | Page 20 of 30
Figure 36. Break-Before-Make Time Delay, tD
Figure 37. Switching Times
Figure 38. Charge Injection
V
DD
V
SS
V
DD
V
SS
0.1µF 0.1µF
GND
INPUT LOGIC
V
S1
S1 D1 V
OUT1
R
L2
300
C
L2
35pF
R
L1
300
C
L1
35pF
V
S2
S2 D2 V
OUT2
V
OUT1
V
OUT2
SCLK 50%
80% 80%
80% 80%
50%
0V
0V
0V
t
D
t
D
15902-034
V
DD
V
SS
V
DD
V
SS
0.1µF 0.1µF
GND
R
L
300
C
L
35pF
V
S
INPUT LOGIC
Sx Dx V
OUT
SCLK
V
OUT
50% 50%
90%
10%
t
ON
t
OFF
15902-035
V
DD
V
SS
V
DD
V
SS
GND
INPUT LOGIC
C
L
1nF
Sx Dx V
OUT
R
S
V
S
SCLK
3V
V
OUT
V
OUT
Q
INJ
= C
L
× V
OUT
SWITCH OFF SWITCH ON
15902-036
Data Sheet ADGS5414
Rev. 0 | Page 21 of 30
TERMINOLOGY
IDD
IDD is the positive supply current.
ISS
ISS is the negative supply current.
VD, VS
VD and VS are the analog voltages on Terminal D and Terminal
S, respectively.
RON
RON represents the ohmic resistance between Terminal D and
Terminal S.
ΔRON
ΔRON is the difference between the RON of any two channels.
RFLAT(ON)
RFLAT(ON) is defined as the difference between the maximum and
minimum value of on resistance measured over the specified
analog signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) are the channel leakage currents with the
switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH are the low and high input currents of the digital
inputs.
CD (Off)
CD (Off) is the off switch drain capacitance, which is measured
with reference to GND.
CS (Off)
CS (Off) is the off switch source capacitance, which is measured
with reference to GND.
CD (On), CS (On)
CD (On) and CS (On) are the on switch capacitances, which are
measured with reference to GND.
CIN
CIN is the digital input capacitance.
tON
tON is the delay between applying the digital control input and
the output switching on.
tOFF
tOFF is the delay between applying the digital control input and
the output switching off.
tD
tD is the off time measured between the 80% point of both
switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
On Response
On response is the frequency response of the on switch.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. ACPSRR is a measure of the ability of
the device to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 V p-p.
ADGS5414 Data Sheet
Rev. 0 | Page 22 of 30
THEORY OF OPERATION
The ADGS5414 is a set of SPI controlled, octal SPST switches with
error detection features. SPI Mode 0 and Mode 3 can be used
with the device, and it operates with SCLK frequencies up to 50
MHz. The default mode for the ADGS5414 is address mode in
which the registers of the device are accessed by a 16-bit SPI
command that is bounded by CS. The SPI command becomes
24 bits long if the user enables CRC error detection. Other error
detection features include SCLK count error detection and invalid
read/write error detection. If any of these SPI interface errors occur,
they are detectable by reading the error flags register. The
ADGS5414 can also operate in two other modes: burst mode
and daisy-chain mode.
The interface pins of the ADGS5414 are CS, SCLK, SDI, and SDO.
Hold CS low when using the SPI interface. Data is captured on
SDI on the rising edge of SCLK, and data is propagated out on SDO
on the falling edge of SCLK. SDO has an open-drain output;
thus, connect a pull-up to this output. When not pulled low by
the ADGS5414, SDO is in a high impedance state.
ADDRESS MODE
Address mode is the default mode for the ADGS5414 upon
power-up. A single SPI frame in address mode is bounded by
a CS falling edge and the succeeding CS rising edge. The SPI frame
is comprised of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 39. The first SDI bit indicates if the SPI
command is a read or write command. When the first bit is set
to 0, a write command is issued, and if the first bit is set to 1, a
read command is issued. The next seven bits determine the target
register address. The remaining eight bits provide the data to the
addressed register. The last eight bits are ignored during a read
command, because, during these clock cycles, SDO propagates
out the data contained in the addressed register.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the ninth to the 16th SCLK falling edge during SPI
reads.
A register write occurs on the 16th SCLK rising edge during SPI
writes.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each of these errors has a corresponding
enable bit in the error configuration register. In addition, there
is an error flag bit for each of these errors in the error flags
register.
CRC Error Detection
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles send the CRC byte for
that SPI frame. The CRC byte is calculated by the SPI block using
the 16-bit payload: the R/W bit, a selected register address,
Bits[6:0], and selected Register Data Bits[7:0]. The CRC
polynomial used in the SPI block is x8 + x2 + x1 + 1 with a seed
value of 0. For a timing diagram with CRC enabled, see Figure 40.
Register writes occur at the 24th SCLK rising edge with CRC
error checking enabled.
During an SPI write, the microcontroller or computer processing
unit (CPU) provides the CRC byte through SDI. The SPI block
checks the CRC byte just before the 24th SCLK rising edge. On this
same edge, the register write is prevented if an incorrect CRC byte
is received by the SPI interface. The CRC error flag is asserted
in the error flags register in the case of the incorrect CRC byte
being detected.
During an SPI read, the CRC byte is provided to the
microcontroller through SDO.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
00100101D7 D6 D5 D4 D3 D2 D1 D0SDO
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
12345678910111213141516
SDI
SCLK
CS
15902-037
Figure 39. Address Mode Timing Diagram
Data Sheet ADGS5414
Rev. 0 | Page 23 of 30
0 0 1 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0SDO
R/W A6 A0 D7 D6 D0 C7 C6 C5 C4 C3 C2 C1 C0
1 2 8 9 10 16 17 18 19 20 21 22 23 24
SDI
SCLK
CS
15902-038
Figure 40. Timing Diagram with CRC Enabled
SCLK Count Error Detection
SCLK count error detection allows the user to detect if an incorrect
number of SCLK cycles are sent by the microcontroller or CPU.
When in address mode, with CRC disabled, 16 SCLK cycles are
expected. If 16 SCLK cycles are not detected, the SCLK count
error flag asserts in the error flags register. When less than 16 SCLK
cycles are received by the device, a write to the register map does
not occur. When the ADGS5414 receives more than 16 SCLK
cycles, a write to the memory map still occurs at the 16th SCLK
rising edge, and the flag asserts in the error flags register. With
CRC enabled, the expected number of SCLK cycles becomes 24.
SCLK count error detection is enabled by default and can be
configured by the user through the error configuration register.
Invalid Read/Write Address Error
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register does not
occur when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be disabled
by the user through the error configuration register.
CLEARING THE ERROR FLAGS REGISTER
To clear the error flags register, write the 16-bit SPI frame (not
included in the register map), 0x6CA9, to the device. This SPI
command does not trigger the invalid R/W address error. When
CRC is enabled, the user must send the correct CRC byte for a
successful error clear command. At the 16th or 24th SCLK rising
edge, the error flags register resets to zero.
BURST MODE
The SPI interface can accept consecutive SPI commands
without the need to deassert the CS line, which is called burst
mode. Burst mode is enabled through the burst enable register
(Address 0x05). This mode uses the same 16-bit command to
communicate with the device. In addition, the response of
the device at SDO is still aligned with the corresponding SPI
command. Figure 41 shows an example of SDI and SDO during
burst mode.
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
within a given CS frame is counted, and if the total is not a
multiple of 16, or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
SDO
COMMAND0[15:0]
RESPONSE0[15:0]
COMMAND1[15:0]
RESPONSE1[15:0]
COMMAND2[15:0]
RESPONSE2[15:0]
COMMAND3[15:0]
RESPONSE3[15:0]
SDI
CS
15902-039
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset.
To do so, write two consecutive SPI commands, namely 0xA3
followed by 0x05, to Register 0x0B. After a software reset, all
register values are set to default.
DAISY-CHAIN MODE
The connection of several ADGS5414 devices in a daisy-chain
configuration is possible, and Figure 42 shows this setup. All
devices share the same CS and SCLK line, whereas the SDO of a
device forms a connection to the SDI of the next device, creating a
shift register. In daisy-chain mode, SDO is an eight cycle delayed
version of SDI. When in daisy-chain mode, all commands target
the switch data register (SW_DATA). Therefore, it is not
possible to make configuration changes while in daisy-chain mode.
ADGS5414 Data Sheet
Rev. 0 | Page 24 of 30
SCLK
SDI
CS
V
L
ADGS5414
DEVICE 2
SPI
INTERFACE
S1 D1
S2 D2
S3 D3
S4 D4
S5 D5
S6 D6
S7 D7
S8 D8
SDO
V
L
ADGS5414
DEVICE 1
SPI
INTERFACE
S1 D1
S2 D2
S3 D3
S4 D4
S5 D5
S6 D6
S7 D7
S8 D8
SDO
15902-040
Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration
0010010100000000SDO
0010010100000000
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SDI
SCLK
CS
15902-041
Figure 43. SPI Command to Enter Daisy-Chain Mode
SDO
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
COMMAND1[7:0]
COMMAND2[7:0]
COMMAND0[7:0]
COMMAND1[7:0]
SDI
SDO3
8’h00
8’h00
8’h00
8’h00
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
SDO2
DEVICE 2
DEVICE 1
DEVICE 4
DEVICE 3
CS
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
15902-042
Figure 44. Example of an SPI Frame when Four ADGS5414 Devices are Connected in Daisy-Chain Mode
The ADGS5414 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 43). When the ADGS5414 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 44. For example, when CS goes high, Device 1 writes
Command 0, SW_DATA, Bits[7:0] to its switch data register,
Device 2 writes Command 1, SW_DATA, Bits[7:0] to its
switches. The SPI block uses the last eight bits it receives
through SDI to update the switches. After entering daisy-chain
mode, the first eight bits sent out by SDO on each device in the
chain are 0x00. When CS goes high, the internal shift register
value does not reset back to zero.
An SCLK rising edge reads in data on SDI while data is
propagated out on SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high. If this is not the case, the SPI interface sends the last
eight bits received to the switch data register.
POWER-ON RESET
The digital section of the ADGS5414 goes through an initialization
phase during VL power-up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
a minimum of 120 μs from the time of power-up or reset before
any SPI command is issued. Ensure VL does not drop out during
the 120 μs initialization phase because it can result in the
incorrect operation of the ADGS5414.
Data Sheet ADGS5414
Rev. 0 | Page 25 of 30
BREAK-BEFORE-MAKE SWITCHING
The ADGS5414 exhibits break-before-make switching action,
which allows the use of the device in multiplexer applications. A
multiplexer function can be achieved by externally hardwiring the
device in the required mux configuration, as shown in Figure 45.
S1
S4
S2
S3
Dx
SCLK SDI CS RESET/V
L
SPI
INTERFACE
4:1 M UX
4 × SPST
15902-043
Figure 45. An SPI Controlled Switch Configured in a 4:1 Mux
TRENCH ISOLATION
In the analog switch section of the ADGS5414, an insulating oxide
layer (trench) is placed between the N-type metal-oxide semi-
conductor (NMOS) and the P-type metal-oxide semiconductor
(PMOS) transistors of each complementary metal-oxide semi-
conductor CMOS switch. Parasitic junctions, which occur between
the transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
In junction isolation, the P-well and N-well of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed, and the result is a latch-
up proof switch.
The Analog Devices, Inc., high voltage latch-up proof family of
switches and multiplexers provides a robust olution for
instrumentation, industrial, aerospace, and other harsh
environments that are prone to latch-up, which is an
undesirable high current state that can lead to device failure and
persists until the power supply is turned off. The ADGS5414
high voltage switches allow single-supply operation from 9 V to
40 V and dual-supply operation from ±9 V to ±22 V.
NMOS PMOS
P-WELL N-WELL
BURIE D O X IDE LAY ER
HANDL E WAFER
TRENCH
15902-044
Figure 46. Trench Isolation
ADGS5414 Data Sheet
Rev. 0 | Page 26 of 30
APPLICATIONS INFORMATION
POWER SUPPLY RAILS
To guarantee correct operation of the ADGS5414, 0.1 μF
decoupling capacitors are required.
The ADGS5414 can operate with bipolar supplies between ±9 V
and ±22 V. The supplies on VDD and VSS do not need to be
symmetrical; however, the VDD to VSS range must not exceed 44 V.
The ADGS5414 can also operate with single supplies between
9 V and 40 V with VSS connected to GND.
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
The device is fully specified at ±15 V, ±20 V, +12 V, and +36 V,
analog supply voltage ranges.
POWER SUPPLY RECOMMENDATIONS
Analog Devices has a wide range of power management
products that meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 47.
The ADP5070 dual switching regulator generates a positive and
negative supply rail for the ADGS5414, an amplifier, and/or a
precision converter in a typical signal chain.
Figure 47 also shows two optional low dropout regulators
(LDOs), ADP7118 and ADP7182, positive and negative LDOs
respectively, that can reduce the output ripple of the ADP5070
in ultralow noise sensitive applications.
The ADM7160 can be used to generate the VL voltage that is
required to power the digital circuitry within the ADGS5414.
ADM7160
LDO
+3.3V
ADP7118
LDO
+15V
ADP7182
LDO
–15V
+16.5V
–16.5V
ADP5070
+5V
INPUT
15902-045
Figure 47. Bipolar Power Solution
Table 10. Recommended Power Management Devices
Product Description
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, LDO linear regulator
Data Sheet ADGS5414
Rev. 0 | Page 27 of 30
REGISTER SUMMARY
Table 11. Register Summary
Reg. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default RW
0x01 SW_DATA SW8_EN SW7_EN SW6_EN SW5_EN SW4_EN SW3_EN SW2_EN SW1_EN 0x00 R/W
0x02 ERR_CONFIG Reserved RW_ERR_EN SCLK_ERR_EN CRC_ERR_EN 0x06 R/W
0x03 ERR_FLAGS Reserved RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG 0x00 R
0x05 BURST_EN Reserved BURST_MODE_EN 0x00 R/W
0x0B SOFT_RESETB SOFT_RESETB 0x00 R/W
ADGS5414 Data Sheet
Rev. 0 | Page 28 of 30
REGISTER DETAILS
SWITCH DATA REGISTER
SW_DATA, Address 0x01, Reset: 0x00
The switch data register controls the status of the eight switches of the ADGS5414.
Table 12. Bit Descriptions for SW_DATA
Bit Bit Name Setting Description Default Access
7 SW8_EN Enable bit for Switch 8. 0x0 R/W
0 Switch 8 open.
1 Switch 8 closed.
6 SW7_EN Enable bit for Switch 7. 0x0 R/W
0 Switch 7 open.
1 Switch 7 closed.
5 SW6_EN Enable bit for Switch 6. 0x0 R/W
0 Switch 6 open.
1 Switch 6 closed.
4 SW5_EN Enable bit for Switch 5. 0x0 R/W
0 Switch 5 open.
1 Switch 5 closed.
3 SW4_EN Enable bit for Switch 4. 0x0 R/W
0 Switch 4 open.
1 Switch 4 closed.
2 SW3_EN Enable bit for Switch 3. 0x0 R/W
0 Switch 3 open.
1 Switch 3 closed.
1 SW2_EN Enable bit for Switch 2. 0x0 R/W
0 Switch 2 open.
1 Switch 2 closed.
0 SW1_EN Enable bit for Switch 1. 0x0 R/W
0 Switch 1 open.
1 Switch 1 closed.
ERROR CONFIGURATION REGISTER
ERR_CONFIG, Address 0x02, Reset: 0x06
The error configuration register allows the user to enable or disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bit Bit Name Setting Description Default Access
[7:3] Reserved These bits are reserved; set these bits to 0. 0x0 R
2 RW_ERR_EN Enable bit for detecting an invalid read/write address. 0x1 R/W
0 Disabled.
1 Enabled.
1 SCLK_ERR_EN Enable bit for detecting the correct number of SCLK cycles in an SPI frame.
16 SCLK cycles are expected when CRC is disabled and burst mode is
disabled. 24 SCLK cycles are expected when CRC is enabled and burst
mode is disabled. A multiple of 16 SCLK cycles is expected when CRC is
disabled and burst mode is enabled. A multiple of 24 SCLK cycles is
expected when CRC is enabled and burst mode is enabled.
0x1 R/W
0 Disabled.
1 Enabled.
0 CRC_ERR_EN Enable bit for CRC error detection. SPI frames must be 24 bits wide when
enabled.
0x0 R/W
0 Disabled.
1 Enabled.
Data Sheet ADGS5414
Rev. 0 | Page 29 of 30
ERROR FLAGS REGISTER
ERR_FLAGS, Address 0x03, Reset: 0x00,
The error flags register allows the user to determine if an error occurs. To clear the error flags register, write the special 16-bit SPI
command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user
must include the correct CRC byte during the SPI write for the clear Error Flags Register command to be successful.
Table 14. Bit Descriptions for ERR_FLAGS
Bit Bit Name Setting Description Default Access
[7:3] RESERVED These bits are reserved and are set to 0. 0x0 R
2 RW_ERR_FLAG Error flag for invalid read/write address. The error flag asserts during an
SPI read if the target address does not exist. The error flag also asserts
when the target address of a SPI write is does not exist or is read only.
0x0 R
0 No Error.
1 Error.
1 SCLK_ERR_FLAG Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
0x0 R
0 No Error.
1 Error.
0 CRC_ERR_FLAG Error Flag that determines if a CRC error occurs during a register write. 0x0 R
0 No Error.
1 Error.
BURST ENABLE REGISTER
BURST_EN, Address 0x05, Reset: 0x00
The burst enable register allows the user to enable/disable the burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 15. Bit Descriptions for BURST_EN
Bits Bit Name Settings Description Default Access
[7:1] Reserved These bits are reserved; set these bits to 0. 0x0 R
0 BURST_MODE_EN Burst mode enable bit. 0x0 R/W
0 Disabled.
1 Enabled.
SOFTWARE RESET REGISTER
SOFT_RESETB, Address 0x0B, Reset: 0x00
This register performs a software reset. Consecutively, write 0xA3 and 0x05 to this register and to reset the device registers to their default
state.
Table 15. Bit Descriptions for SOFT_RESETB
Bits Bit Name Settings Description Default Access
[7:0] SOFT_RESETB To Perform a Software Reset, consecutively write 0xA3 followed by 0x05
to this register.
0x0 R
ADGS5414 Data Sheet
Rev. 0 | Page 30 of 30
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC ST AND ARDS MO-220- V GGD-8.
BOT TOM VIEW
TOP VIEW
4.10
4.00 S Q
3.90
1.00
0.95
0.90 0.05 M AX
0.02 NOM
0.20 REF
COPLANARITY
0.08
PIN 1
INDICATOR
1
24
712
13
18
19
6
02-09-2017-A
0.30
0.25
0.18
0.20 MI N
2.70
2.60 SQ
2.50
EXPOSED
PAD
PKG-004677
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PR OPE R CONNE C TI ON OF
THE EXPOSED PAD, REFER TO
THE P I N CONF I GURAT IO N AND
FUNCTION DESCRIPT IONS
SECTION O F THIS DATA SHEET.
Figure 48. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADGS5414BCPZ −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-17
ADGS5414BCPZ-RL7 −40°C to +125°C 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-17
EVAL-ADGS5414SDZ Evaluation Board
1 Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15902-0-10/17(0)
