CY8C20110, CY8C20180
CY8C20160, CY8C20140
CY8C20142
CapSense® Express™ Button
Capacitive Controllers
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-54606 Rev. *E Revised November 19, 2010
CapSense® Express™ Button Capacitive Controllers
Features
■10/8/6/4 capacitive button input
❐Robust sensing algorithm
❐High sensitivity, low noise
❐Immunity to RF and AC noise
❐Low radiated EMC noise
❐Supports wide range of input capacitance, sensor shapes,
and sizes
■Target applications
❐Printers
❐Cellular handsets
❐LCD monitors
❐Portable DVD players
■Low operating current
❐Active current: continuous sensor scan: 1.5 mA
❐Deep sleep current: 4 µA
■Industry's best configurability
❐Custom sensor tuning, one optional capacitor
❐Output supports strong drive for LED
❐Output state can be controlled through I2C or directly from
CapSense® input state
❐Run time reconfigurable over I2C
■Advanced features
❐All GPIOs support LED dimming with configurable delay
option in CY8C20110
❐Interrupt outputs
❐User defined inputs
❐Wake on interrupt input
❐Sleep control pin
❐Nonvolatile storage of custom settings
❐Easy integration into existing products – configure output to
match system
❐No external components required
❐World class free configuration tool
■Wide range of operating voltages
❐2.4 V to 2.9 V
❐3.10 V to 3.6 V
❐4.75 V to 5.25 V
■I2C communication
❐Supported from 1.8 V
❐Internal pull-up resistor support option
❐Data rate up to 400 kbps
❐Configurable I2C addressing
■Industrial temperature range: –40 °C to +85 °C.
■Available in 16-pin QFN, 8-pin, and 16-pin SOIC packages
Overview
These CapSense Express™ controllers support four to ten
capacitive sensing (CapSense) buttons. The device functionality
is configured through an I2C port and can be store d in onboard
nonvolatile memory for automatic loading at power-on. The
CY8C201 10 is optimized for dimming LEDs in 15 selectable duty
cycles for back light applications. The device can be configured
to have up to 10 GPIOs connected to the PWM output. The PWM
duty cycle is programmable for variable LED intensities.
The four key blocks that make up these devices are: a robust
capacitive sensing core with high immunity against radiated and
conductive noise, control registers with nonvolatile storage,
configurable outputs, and I2C communications. The user can
configure registers with parameters neede d to adjust the
operation and sensitivity of the CapSense buttons and outputs
and permanently store the settings. The standard I2C serial
communication interface enables the host to configure the
device and read sensor information in real time. The I2C address
is fully configurable withou t any external hardware strapping.
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Contents
Pinouts ..............................................................................3
Typical Circuits .................................................................6
I2C Interface ......................................................................8
I2C Device Addressing ................................................8
I2C Clock Stretching ....................................................8
Format for Register Write and Read ...........................9
Operating Modes of I2C Commands ...................... .......10
Normal Mode .............................................................10
Setup Mode .............. .............. ... .............. ... .............. .10
Device Operation Modes ................................................10
Active Mode ...............................................................10
Periodic Sleep Mode .................................................10
Deep Sleep Mode ......................................................10
Sleep Control Pin ............................................................10
Interrupt Pin to Master ...................................................10
LED Dimming ..................................................................10
LED Dimming Mode 1: Change Intensity on
ON/OFF Button Status ..............................................11
LED Dimming Mode 2: Flash Intensity on
ON Button Status ......................................................11
LED Dimming Mode 3: Hold Intensity
After ON/OFF Button Transition ................................12
LED Dimming Mode 4: Toggle Intensity on
ON/OFF or OFF/ON Button Transitions ....................12
Register Map ............ ............... .. .............. ... ... .............. ... .13
CapSense Express Commands ................... .. ... ... ....17
Register Conventions ................................................17
Layout Guidelines and Best Practices .........................18
CapSense Button Shapes ............... .. ........................18
Button Layout Design ................................................18
Recommended via Hole Placement ..........................18
Example PCB Layout Design with Two CapSense Buttons
and Two LEDs ...........................................................20
Operating Voltages ............................ ... .............. .. ..........21
CapSense Constraints ............. ... .............. ... ... ...............21
Electrical Specifications ................................................22
Absolute Maximum Ratings .......................................22
Operating Temperature .............................................22
DC Electrical Characteristics ............ ... ... ................. .. ...23
DC Chip Level Specifications ....................................23
DC GPIO Specifications ................... .........................23
DC POR and LVD Specifications ........... .. ... ... ...........24
DC Flash Write Specifications ............. ... .. ... ..............25
DC I2C Specifications ...............................................25
CapSense Electrical Characteristics .........................25
AC Electrical Specifications ........ ... ... ............................26
AC Chip-Level Specifications ...................... ... ... ... .....26
AC GPIO Specifications ..... .......................................26
AC I2C Specifications ....................... .........................27
Appendix – Examples of Frequently
Used I2C Commands .................. .. ... ............................ ...28
Ordering Information ......................................................29
Ordering Code Definitions .............................................29
Package Diagrams ..........................................................30
Acronyms ........................................................................ 32
Acronyms Used .........................................................32
Reference Documents ...................................... ... ... ........32
Document Conventions .................. ... ... .............. ... ........32
Units of Measure ................... .. ... ............................ ...32
Numeric Conventions ................................................32
Glossary ..........................................................................33
Document History Page .......... ... .............. ... .............. .. ...38
Sales, Solutions, and Legal Information ......................39
Worldwide Sales and Design Support .......................39
Products .................................................................... 39
PSoC Solutions .... ... .. .............. ... ... ............................39
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Pinouts
Figure 1. 16-pin QFN (no e-pad)[1]
Table 1. 16-pin QFN (no e-pad)[1, 2]
Pin No. Pin Name Description
1 GP0[0] Configurable as CapSense or GPIO
2 GP0[1] Configurable as CapSense or GPIO
3I
2C SCL I2C clock
4I
2C SDA I2C data
5 GP1[0] Configurable as CapSense or GPIO
6GP1[1]
[3] Configurable as CapSense or GPIO
7V
SS Ground connection
8GP1[2]
[3] Configurable as CapSense or GPIO
9 GP1[3] Configurable as CapSense or GPIO
10 GP1[4] Configurable as CapSense or GPIO
11 XRES Active high external reset with internal pull-up
12 GP0[2] Configurable as CapSense or GPIO
13 VDD Supply voltage
14 GP0[3] Configurable as CapSense or GPIO
15 CSInt Integrating capacitor Input. The external capacitance is required only
if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF
16 GP0[4] Configurable as CapSense or GPIO
QFN
Notes
1. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
2. 8/6/4 available configurab le IOs can be configured to any o f the 10 IOs of the p ackage. Af ter any of the 8/6 /4 IOs are chosen , the remaining 2/4/6 IOs of the package
are not available for any functionality.
3. Avoid using GP1 [1] and GP1[2] for driving LEDs. These t wo pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
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Figure 2. 16-pin SOIC[4]
Table 2. 16-pin SOIC[4, 5]
Pin No Name Description
1 GP0[3] Configurable as CapSense or GPIO
2 CSint Integrating capacitor input. The external capacitance is required only if 5:1 SNR
cannot be achieved. Typical range is 1 nF to 4.7 nF
3 GP0[4] Configurable as CapSense or GPIO
4 GP0[0] Configurable as CapSense or GPIO
5 GP0[1] Configurable as CapSense or GPIO
6I
2C SCL I2C clock
7I
2C SDA I2C data
8 GP1[0] Configurable as CapSense or GPIO
9GP1[1]
[6] Configurable as CapSense or GPIO
10 VSS Ground connection
11 GP1[2][6] Configurable as CapSense or GPIO
12 GP1[3] Configurable as CapSense or GPIO
13 GP1[4] Configurable as CapSense or GPIO
14 XRES Active high external reset with internal pull-up
15 GP0[2] Configurable as CapSense or GPIO
16 VDD Supply voltage
Notes
4. CY8C20110 (10 Buttons) / CY8C20180 (8 Buttons) / CY8C20160 (6 Buttons) / CY8C20140 (4 Buttons)
5. 8/6/4 available configurab le IOs can be configured to any o f the 10 IOs of the p ackage. Af ter any of the 8/6 /4 IOs are chosen , the remaining 2/4/6 IOs of the package
are not available for any functionality.
6. Avoid using GP1 [1] and GP1[2] for driving LEDs. These t wo pins have special functions during power-up which is used at factory. LEDs connected to these two pins
blink during the power-up of the device.
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Figure 3. Pin Diagram – 8-pin SOIC – CY8C20142 (4 Button)
Table 3. Pin Definitions – 8-pin SOIC – CY8C2 0142 (4 Button)
Important Note For information on the preferred dimensions for mounting QFN packages, see the "Application Note s for Surface
Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages" available at http://www.amkor.com.
Pin No Name Description
1V
SS Ground
2I
2C SCL I2C Clock
3I
2C SDA I2C Data
4GP1[0]
[7] Configurable as CapSense or GPIO
5GP1[1]
[7] Configurable as CapSense or GPIO
6 GP0[0] Configurable as CapSense or GPIO
7 GP0[1] Configurable as CapSense or GPIO
8V
DD Supply voltage
Note
7. Avoid using GP1 [0] and GP1[1] f or driving LED. These t wo pins have special function s duri ng power up wh ich is used at fact ory. LEDs connected to these t wo pins
will blink during power up of the device.
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Typical Circuits
Figure 4. Circuit 1 – Five Buttons and Five LEDs wi th I2C Interface
Figure 5. Circuit 2 – Two Buttons and Two LEDs with I2C Interface
C2
0.1uF
VDD_CE
VDD_CE
R5 560E
D1 LED
R7 560E
D2 LED
VDD_CE B1
R13
560E
R14
560E
B0
C1
1.2nF
VDD_CE
U1
CY8C20110
GPO[0]
1
GPO[1]
2
I2C_SCL
3
I2C_SDA
4
GP1[2]
8
VSS
7
GP1[1]
6
GP1[0]
5
GP1[3] 9
GP1[4] 10
XRE S 11
GPO[2] 12
VDD 13
GP0[3] 14
CSint 15
GPO[4] 16
I2C COMM
R10 330E
INTERFACE
R8 330E
R3
4.7K
VDD_CE
R4
4.7K
Capsense
sensor
B2
R1
560E
B3
R2
560E
B4R6 560E
R9 560E D3 LED
VDD_CE
R11 560E D4 LED
R12
560E
D5
LED
Capsense
sen so r
Capsense
sensor
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Figure 6. Circuit 3 – Compatibility with 1.8 V I2C Signaling
Note 1.8 V ≤ VDD_I2C ≤ VDD_CE and 2.4 V ≤ VDD_CE ≤ 5.25 V
Figure 7. Circuit 4 – Powering Down CapSense Exp ress Device for Low Power Requirements
For low power requirements, if VDD is to be turned off, this concept can be used. The requirement is that the VDDs of CapSense
Express, I2C pull-ups, and LEDs should be from the same source such that turning off the VDD ensures that no signal is applied to
the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port
pins of the master can cater to the power supply requirements of the circuit, the LDO can be avoided.
Master
Or
Host
LDO
CapSense Express
I2C Pull
UPs
LED
I2C
BUS
SDA
SCL
VDDOutput
Output
enable
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I2C Interface
The CapSense Express devices support the industry standard I2C protocol, which can be used for:
■Configuring the device
■Reading the status and data registers of the device
■Controlling device operation
■Executing commands
The I2C address can be modified durin g configuration.
I2C Device Addressing
The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending a one byte address:
the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction
from master and one indicates read transfer by the master. The following table shows examples for different I2C addresses.
I2C Clock Stretching
‘Clock stretching’ or ‘bus stalling’ in I2C communication protocol
is a state in which the slave holds the SCL line low to indicate
that it is busy . In this condition, the master is expected to wait till
the SCL is released by the slave.
When an I2C master communicates with the CapSense Express
device, the CapSense Express stalls the I2C bus after the
reception of each byte (that is, just before the ACK/NAK bit) until
processing of the byte is complete and critical internal functions
are executed. Use a fully I2C compliant master to communicate
with the CapSense Express device.
If the I2C master does not support clock stretching (a bit banged
software I2C Master), the master must wait for a specific amount
of time (as specified in “Format for Register Write and Read” on
page 9) for each register write and read operation before the next
bit is transmitted. The I2C master must check the SCL status (it
should be high) before the I2C master initiates any data transfer
with CapSense Express. If the master fails to do so and
continues to communicate, the communication is erroneous.
The following diagrams represent the ACK time delays shown in
“Format for Register Write and Read” on page 9 for write and
read.
Table 4. I2C Address Examples
7-bit Slave
Address D7 D6 D5 D4 D3 D2 D1 D0 8-bit Slave Address
1 00000 0 10(W) 02
1 00000 0 11(R) 03
75 10010 1 10(W) 96
75 10010 1 11(W) 97
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Figure 8. Write ACK Time Representation[8]
Figure 9. Read ACK Time Representation[9]
Format for Register Write and Read
Register write format
Register read format
Legends:
Notes
8. Time to process the received data.
9. Time ta ken for the device to send next byte.
Start Slave Addr + W AReg AddrADataADataA . . . . . Data AStop
Start Slave Addr + W AReg AddrAStop
Start Slave Addr + R AData AData A. . . . . Data NStop
Master A - ACK
Slave N- NAK
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Operating Modes of I2C Commands
Normal Mode
In normal mode of operation, the acknowledgment time is
optimized. The ti mi ng s remain approximately the same for
different configurations of the slave. To reduce the
acknowledgment times in normal mode, the registers
0x06–0x09, 0x0C, 0x0D, 0x10–0x17, 0x50, 0x51, 0x57–0x60,
0x7E are given only read access. Write to these registers can be
done only in setup mode.
Setup Mode
All registers have read and write access (except those which are
read only) in this mode. The acknowledgment times are longer
compared to normal mode. When CapSense scanning is
disabled (command code 0x0A in command register 0xA0), the
acknowledgment times can be improved to values similar to the
normal mode of operation.
Device Operation Modes
CapSense Express devices are configured to operate in any of
the following three modes to meet different power consumption
requirements:
■Active Mode
■Periodic Sleep Mode
■Deep Sleep Mode
Active Mode
In the active mode, all the device blocks including the CapSense
sub system are powered. Typical active current consumption of
the device across the operating voltage range is 1.5 mA.
Periodic Sleep Mode
Sleep mode provides an intermediate power operation mode. It
is enabled by configuring th e corresponding device registers
(0x7E, 0x7F). The device goes into sleep after there is no event
for stay awake counter (Reg 0x80) number of sleep intervals.
The device wakes up on sleep interval and It scans the
capacitive sensors before going back to sleep again. If any
sensor is active, then the device wakes up. The device can also
wake up from sleep mode with a GPIO interrupt. The following
sleep intervals are supported in CapSense Express. The sleep
interval is configured thro ugh registers.
■1.95 ms (512 Hz)
■15.6 ms (64 Hz)
■125 ms (8 Hz)
■1 s (1 Hz)
Deep Sleep Mode
Deep sleep mode provides the lowest power consumption
because there is no operation running. All CapSense scanning
is disabled during this mode. In this mode, the device wakes up
only using an external GPIO interrupt. A sleep timer interrupt
cannot wake up a device from deep sleep mode. This is treated
as a continuous sleep mode without periodic wakeups. Refer to
the application note “CapSense Express Power and Sleep
Considerations” - AN44209 for details on differen t sleep modes.
To get the lowest power during this mode the sl eep timer
frequency should be set to 1 Hz.
Sleep Control Pin
The devices require a dedicated sleep control pin to enable
reliable I2C communication in case any sleep mode is enabled.
This is achieved by pulling the sleep control pin low to wake up
the device and start I2C communication. The sleep control pin
can be configured on any GPIO.
Interrupt Pin to Master
To inform the master of any button press a GPIO can be
configured as interrupt output and all CapSense buttons can be
connected to this GPIO with an OR logic operator. This can be
configured using the software tool.
LED Dimming
To change the brightness and intensity of the LEDs, the host
master (MCU, MPU, DSP, and so on) must send I2C commands
and program the PWM registers to enable output pins, set duty
cycle, and mode configuration. The single PWM source is
connected to all GPIO pins and has a common user defined duty
cycle. Each PWM enabled pin has two possible outputs: PWM
and 0/1 (depending on the configuration). Four different modes
of LED dimming are possible, as shown in “LED Dimming Mode
1: Change Intensity on ON/OFF Button Status” on page 11 to
“LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON
Button Transitions” on page 12. The operation mode and duty
cycle of the PWM enabled pins is common. This means that one
pin cannot behave as in Mode 1 and another pin as in Mode 2.
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Register Map
Name Register
Address
(in Hex) Access Writable Only
in SETUP
Mode[10]
Factory Default
Va lues of Regist er s
(in Hex)
I2C Max ACK Time
in Normal Mode
(ms)
I2C Max ACK
Time in Setup
Mode (ms)
INPUT_PORT0 00 R – 00 0.1 –
INPUT_PORT1 01 R – 00 0.1 –
STATUS_POR0 02 R – 00 0.1 –
STATUS_POR1 03 R – 00 0.1 –
OUTPUT_PORT0 04 W – 00 0.1 –
OUTPUT_PORT1 05 W – 00 0.1 –
CS_ENABL0 06 RW YES 00 – 11
CS_ENABLE 07 RW YES 00 – 11
GPIO_ENABLE0 08 RW YES 00 – 11
GPIO_ENABLE1 09 RW YES 00 – 11
INVERSION_MASK0 0A RW – 00 0.11 –
INVERSION_MASK1 0B RW – 00 0.11 –
INT_MASK0 0C RW YES 00 – 11
INT_MASK1 0D R W YES 00 – 11
STATUS_HOLD_MSK0 0E RW – 03/1F[11] 0.11 –
STATUS_HOLD_MSK1 0F RW – 03/1F[11] 0.11 –
DM_PULL_UP0 10 RW YES 00 – 11
DM_STRONG0 11 RW YES 00 – 11
DM_HIGHZ0 12 RW YES 00 – 11
DM_OD_LOW0 13 RW YES 00 – 11
DM_PULL_UP1 14 RW YES 00 – 11
DM_STRONG1 15 RW YES 00 – 11
DM_HIGHZ1 16 RW YES 00 – 11
DM_OD_LOW1 17 RW YES 00 – 11
PWM_ENABLE0[12] 18 RW – 00 0.1 –
PWM_ENABLE1[12] 19 RW – 00 0.1 –
PWM_MODE_DC[12] 1A RW – 00 0.1 –
PWM_DELAY[12] 1B RW – 00 0.1 –
OP_SEL_00 1C RW – 00 0.12 11
OPR1_PRT0_00 1D RW – 00 0.12 11
OPR1_PRT1_00 1E RW – 00 0.12 11
OPR2_PRT0_00 1F RW – 00 0.12 11
OPR2_PRT1_00 20 RW – 00 0.12 11
OP_SEL_01 21 RW – 00 0.12 11
OPR1_PRT0_01 22 RW – 00 0.12 11
OPR1_PRT1_01 23 RW – 00 0.12 11
OPR2_PRT0_01 24 RW – 00 0.12 11
OPR2_PRT1_01 25 RW – 00 0.12 11
OP_SEL_02 26 RW – 00 0.12 11
OPR1_PRT0_02 27 RW – 00 0.12 11
OPR1_PRT1_02 28 RW – 00 0.12 11
Notes
10.These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
11. The factory defaults of Reg 0x0E and 0x0F is 0x03 for 20142 device an d 0x1F for 20140/60/80/10 devices.
12.These registers are available only in CY8C20110.
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Name Register
Address
(in Hex) Access Writable Only
in SETUP
Mode[13]
Factory Default
Va lues of Regist er s
(in Hex)
I2C Max ACK Time
in Normal Mode
(ms)
I2C Max ACK
Time in Setup
Mode (ms)
OPR2_PRT0_02 29 RW – 00 0.12 11
OPR2_PRT1_02 2A RW – 00 0.12 11
OP_SEL_03 2B RW – 00 0.12 11
OPR1_PRT0_03 2C RW – 00 0.12 11
OPR1_PRT1_03 2D RW – 00 0.12 11
OPR2_PRT0_03 2E RW – 00 0.12 11
OPR2_PRT1_03 2F RW – 00 0.12 11
OP_SEL_04 30 RW – 00 0.12 11
OPR1_PRT0_04 31 RW – 00 0.12 11
OPR1_PRT1_04 32 RW – 00 0.12 11
OPR2_PRT0_04 33 RW – 00 0.12 11
OPR2_PRT1_04 34 RW – 00 0.12 11
OP_SEL_10 35 RW – 00 0.12 11
OPR1_PRT0_10 36 RW – 00 0.12 11
OPR1_PRT1_10 37 RW – 00 0.12 11
OPR2_PRT0_10 38 RW – 00 0.12 11
OPR2_PRT1_10 39 RW – 00 0.12 11
OP_SEL_11 3A RW – 00 0.12 11
OPR1_PRT0_11 3B RW – 00 0.12 11
OPR1_PRT1_11 3 C RW – 00 0.12 11
OPR2_PRT0_11 3D RW – 00 0.12 11
OPR2_PRT1_11 3E RW – 00 0.12 11
OP_SEL_12 3F RW – 00 0.12 11
OPR1_PRT0_12 40 RW – 00 0.12 11
OPR1_PRT1_12 41 RW – 00 0.12 11
OPR2_PRT0_12 42 RW – 00 0.12 11
OPR2_PRT1_12 43 RW – 00 0.12 11
OP_SEL_13 44 RW – 00 0.12 11
OPR1_PRT0_13 45 RW – 00 0.12 11
OPR1_PRT1_13 46 RW – 00 0.12 11
OPR2_PRT0_13 47 RW – 00 0.12 11
OPR2_PRT1_13 48 RW – 00 0.12 11
OP_SEL_14 49 RW – 00 0.12 11
OPR1_PRT0_14 4A RW – 00 0.12 11
OPR1_PRT1_14 4B RW – 00 0.12 11
OPR2_PRT0_14 4C RW – 00 0.12 11
OPR2_PRT1_14 4D RW – 00 0.12 11
CS_NOISE_TH 4E RW – 28 0.11 11
CS_BL_UPD_TH 4F RW – 64 0.11 11
CS_SETL_TIME 50 RW YES A0 – 35
CS_OTH_SET 51 RW YES 00 – 35
CS_HYSTERISIS 52 RW – 0A 0.11 11
Note
13.These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
Register Map (continued)
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Name Register
Address
(in Hex) Access Writable Only
in SETUP
Mode[14]
Factory Default
Va lues of Regist er s
(in Hex)
I2C Max ACK Time
in Normal Mode
(ms)
I2C Max ACK
Time in Setup
Mode (ms)
CS_DEBOUNCE 53 RW – 03 0.11 11
CS_NEG_NOISE_TH 54 RW – 14 0.11 11
CS_LOW_BL_RST 55 RW – 14 0.11 11
CS_FILTERING 56 RW – 20 0.11 11
CS_SCAN_POS_00 57 RW YES FF – 11
CS_SCAN_POS_01 58 RW YES FF – 11
CS_SCAN_POS_02 59 RW YES FF – 11
CS_SCAN_POS_03 5A RW YES FF – 11
CS_SCAN_POS_04 5B RW YES FF – 11
CS_SCAN_POS_10 5C RW YES FF – 11
CS_SCAN_POS_11 5D RW YES FF – 11
CS_SCAN_POS_12 5E RW YES FF – 11
CS_SCAN_POS_13 5F RW YES FF – 11
CS_SCAN_POS_14 60 RW YES FF – 11
CS_FINGER_TH_00 61 RW – 64 0.14 11
CS_FINGER_TH_01 62 RW – 64 0.14 11
CS_FINGER_TH_02 63 RW – 64 0.14 11
CS_FINGER_TH_03 64 RW – 64 0.14 11
CS_FINGER_TH_04 65 RW – 64 0.14 11
CS_FINGER_TH_10 66 RW – 64 0.14 11
CS_FINGER_TH_11 67 RW – 64 0.14 11
CS_FINGER_TH_12 68 RW – 64 0.14 11
CS_FINGER_TH_13 69 RW – 64 0.14 11
CS_FINGER_TH_14 6A RW – 64 0.14 11
CS_IDAC_00 6B RW – 0A 0.14 11
CS_IDAC_01 6C RW – 0A 0.14 11
CS_IDAC_02 6D RW – 0A 0.14 11
CS_IDAC_03 6E RW – 0A 0.14 11
CS_IDAC_04 6F RW – 0A 0.14 11
CS_IDAC_10 70 RW – 0A 0.14 11
CS_IDAC_11 71 RW – 0A 0.14 11
CS_IDAC_12 72 RW – 0A 0.14 11
CS_IDAC_13 73 RW – 0A 0.14 11
CS_IDAC_14 74 RW – 0A 0.14 11
75[15]
76[15]
77[15]
78[15]
I2C_ADDR_LOCK 79 RW – 01 0.11 11
DEVICE_ID 7A R – 42/40/60/80/10[16] 0.11 11
DEVICE_STATUS 7B R – 03 0.11 11
I2C_ADDR_DM 7C RW – 00 0.11 11
Notes
14.These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
15.The register 0x75–0x78, 0x7D and 0x8A–0x8D are reserved.
16.The Device ID for different devices are tabulated in Table 5.
Register Map (continued)
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Note All the Ack times specified are maximu m values with all buttons enabled and filer enabled with maximum order.
Name Register
Address
(in Hex) Access Writable Only
in SETUP
Mode[17]
Factory Default
Va lues of Regist er s
(in Hex)
I2C Max ACK Time
in Normal Mode
(ms)
I2C Max ACK
Time in Setup
Mode (ms)
7D[18]
SLEEP_PIN 7E RW YES 00 0.1 11
SLEEP_CTRL 7F RW – 00 0.1 11
SLEEP_SA_CNTR 80 RW – 00 0.1 11
CS_READ_BUTTON 81 RW – 00 0.12 11
CS_READ_BLM 82 R – 00 0.12 11
CS_READ_BLL 83 R – 00 0.12 11
CS_READ_DIFFM 84 R – 00 0.12 11
CS_READ_DIFFL 85 R – 00 0.12 11
CS_READ_RAWM 86 R – 00 0.12 11
CS_READ_RAWL 87 R – 00 0.12 11
CS_READ_STATUSM 88 R – 00 0.12 11
CS_READ_STATUSL 89 R – 00 0.12 11
8A[18]
8B[18]
8C[18]
8D[18]
COMMAND_REG A0 W – 00 0.1 11
Table 5. Device IDs
Part Number Device ID
CY8C 20142 42
CY8C 20140 40
CY8C 20160 60
CY8C 20180 80
CY8C 20110 10
Register Map (continued)
Notes
17.These registers are writable only after entering int o setup mode. All the other registers available for read and write in Normal as well as in Setup mode.
18.The register 0x75–0x78, 0x7D and 0x8A–0x8D are rese rved.
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CapSense Express Commands
Register Conventions
This table lists the register conventions that are specific to this section.
Command[19] Description Executable
Mode Duration the Device is not
accessible after ACK (in ms)
W 00 A0 00 Get firmware revision Setup/Normal 0
W 00 A0 01 Store current configuration to NVM Setup/Normal 120
W 00 A0 02 Restore factory configuration Setup/Normal 120
W 00 A0 03 Write NVM POR defaults Setup/Normal 120
W 00 A0 04 Read NVM POR defaults Setup/Normal 5
W 00 A0 05 Read current configurations (RAM) Setup/Normal 5
W 00 A0 06 Reconfigure device (POR) Setup 5
W 00 A0 07 Set normal mode of operation Setup/Normal 0
W 00 A0 08 Set setup mode of operation Setup/Normal 0
W 00 A0 09 Start scan Setup/Normal 10
W 00 A0 0A Stop scan Setup/Normal 5
W 00 A0 0B Get CapSense scan status Setup/Normal 0
Note
19.The ‘W’ indicates the write transfer. The next byte of data represents the 7-bit I2C address.
Convention Description
RW Register has both read and write access
R Register has only read access
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Layout Guidelines and Best Practices
CapSense Button Shapes
Button Layout Design
X: Button to ground clearance (Refer to Table 6 on page 18)
Y: Button to button clearance (Refer to Table 6 on page 18)
Recommended via Hole Placement
Table 6. Recommended Layout Guidelines and Best Practices
Sl Category Min Max Recommendations/Remarks
1 Button shape – – Solid round pattern, round with LED hole, rectangle with
round corners
2 Button size 5 mm 15 mm 10 mm
3 Button-button spacing Equal to
button
ground
clearance
– 8 mm [X]
4 Button ground clearance 0.5 mm 2 mm Button ground clearance = Overlay thickness [Y]
5 Ground flood-top laye r – – Hatched ground 7-mil trace and 45-mil grid (15% filling)
6 Ground flood-bottom layer – – Hatched ground 7 -mil trace and 70-mil grid (10% filling)
7 Trace length from sensor to
PSoC-buttons – 200 mm < 100 mm
8 Trace width 0.17 mm 0.20 mm 0.17 mm (7-mil)
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9 Trace routing – – Traces should be routed on the non sensor side. If any non
CapSense trace crosses CapSense trace, ensure that
intersection is orthogonal.
10 Via position for the sensors – – Via should be placed near the edge of the button/slider to
reduce trace length thereby increasing sensitivity.
11 Via hole size for sensor traces – – 10-mil
12 Number of vias on sensor trace 1 2 1
13 CapSense series resistor
placement – 10 mm Place CapSense series resistors close to PSoC for noise
suppression. CapSense resistors have highest priority place
them first.
14 Distance between any
CapSense trace to ground flood 10-mil 20-mil 20-mil
15 Device placement – – Mount the device on the layer opposite to sensor. The
CapSense trace length between the device and sensors
should be minimum
16 Placement of components in
2-layer PCB – – Top layer – sensor pads and bottom layer – PSoC, other
components, and traces.
17 Placement of components in
4-layer PCB – – Top layer – sensor pads, second layer – CapSense traces,
third layer – hatched ground, bottom layer – PSoC, other
components, and non CapSense traces
18 Overlay thickness-buttons 0 mm 2 mm 1 mm
19 Overlay material – – Should to be non conductive material. Glass, ABS plastic,
Formica
20 Overlay adhesives – – Adhesive should be non conductive and dielectrically
homogenous. 467MP and 468MP adhesives made by 3M are
recommended.
21 LED back lighting – – Cut a hole in the sensor pad and use rear mountable LEDs.
Refer the PCB layout below.
22 Board thickness – – S tandard board thickness for CapSense FR4 based designs
is 1.6 mm.
Table 6. Recommended Layout Guidelines and Best Practices (continued)
Sl Category Min Max Recommendations/Remarks
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Operating Voltages
For details on I2C 1x ACK time, refer to “Register Map” on page 13 and “CapSense Express Commands” on page 17. I2C 4x ACK
time is approximately four times the values mentioned in thes e tables.
CapSense Constraints
Parameter Min Typ Max Units Notes
Parasitic capacitance (CP) of the
CapSense sensor – – 30 pF
Overlay thickness 0 1 2 mm All layout best practices followed, properly
tuned, and noise free condition.
Supply voltage variation (VDD)––± 5%–
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Electrical Specifications
Absolute Maximum Ratings
Parameter Description Min Typ Max Unit Notes
TSTG Storage temperature –55 25 +100 °C Higher storage temperatures reduce data
retention time. Recommended storage
temperature is +25 °C ± 25 °C (0 °C to
50 °C). Extended duration storage
temperatures above 65 °C degrade
reliability
TBAKETEMP Bake temperature –125 See
Package
label
oC
tBAKETIME Bake time See
package
label
–72 Hours
TAAmbient temperature wi th po w er
applied –40 – +85 °C
VDD Supply voltage on VDD relative to VSS –0.5 – +6.0 V
VIO DC input voltage VSS – 0.5 – VDD + 0.5 V
VIOZ DC voltage applied to tristate VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any GPIO pin –25 – +50 mA
ESD Electro static discharge voltage 2000 – – V Human body model ESD
LU Latch-up current – – 200 mA
Operating Temperature
Parameter Description Min Typ Max Unit Notes
TAAmbient temperature –40 – + 85 °C
TJJunction temperature –40 – +100 °C
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DC Electrical Characteristics
DC GPIO Specifications
DC Chip Level Specifications
Parameter Description Min Typ Max Unit Notes
VDD Supply voltage 2.40 – 5.25 V
IDD Supply current – 1.5 2.5 mA Conditions are VDD = 3.10 V, TA = 25 °C
ISB Deep sleep mode current with POR
and LVD active –2.64 µAV
DD = 2.55 V, 0 °C < TA < 40 °C
ISB Deep sleep mode current with POR
and LVD active –2.85 µAV
DD = 3.3 V, –40 °C < TA < 85 °C
ISB Deep sleep mode current with POR
and LVD active –5.26.4µAV
DD = 5.25 V, –40 °C < TA < 85 °C
Table 7. 5-V and 3.3-V DC GPIO Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design
guidance only.
Parameter Description Min Typ Max Unit Notes
VOH1 High output voltage on Port 0 pins VDD – 0.2 – – V IOH < 10 µA, VDD > 3.10 V, maximum of
20 mA source current in all I/Os.
VOH2 High output voltage on Port 0 pins VDD – 0.9 – – V IOH = 1 mA, VDD > 3.10 V, maximum of
20 mA source current in all I/Os.
VOH3 High output voltage on Port 1 pins VDD – 0.2 – – V IOH < 10 µA, VDD > 3.10 V, maximum of
20 mA source current in all I/Os.
VOH4 High output voltage on Port 1 pins VDD – 0.9 – – V IOH = 5 mA, VDD > 3.10 V, maximum of
20 mA source current in all I/Os.
VOL Low output voltage – – 0.75 V IOL = 20 mA/pin, VDD > 3.10, maximum of
40/60 mA sink current on even port pins and
of 40/60 mA sink current on odd port
pins.[20]
IOH1 High output current on Port 0 pins 0.01 – 1 mA VDD ≥ 3.1 V, maximum of 20 mA source
current in all IOs
IOH2 High output current on Port 1 pins 0.01 – 5 mA VDD ≥ 3.1 V, maximum of 20 mA source
current in all IOs
IOL Low output current – – 20 mA VDD ≥ 3.1 V , maximum of 60 mA sink current
on pins P0_2, P1_2, P1_3, P1_4 and 60 mA
sink current on pins P0_0, P0_1, P0_3,
P0_4, P1_0, P1_1
VIL Input low voltage – – 0.75 V VDD = 3.10 V to 3.6 V.
VIH Input high voltage 1.6 – – V VDD = 3.10 V to 3.6 V.
VIL Input low voltage – – 0.8 V VDD = 4.75 V to 5.25 V.
VIH Input high voltage 2.0 – – V VDD = 4.75 V to 5.25 V.
VHInput hysteresis voltage – 140 – mV –
IIL Input leakage – 1 – nA Gross tested to 1 µA.
CIN Capacitive load on pins as input 0.5 1.7 5 pF Package and pin dependent.
Temp = 25 °C.
COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pin dependent.
Temp = 25 °C.
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Notes
20.The maximum sink current is 40 mA for 20140 and 20142 devices and for all other devices t he maximum sink current is 60 mA
21.The maximum sink current per port is 20 mA for 20140 and 20142 devices and for all other devices the maximum sink current is 30 mA.
Table 8. 2.7-V DC GPIO Specifications
Parameter Description Min Typ Max Unit Notes
VOH1 High output voltage on Port 0 pins VDD – 0.2 – – V IOH <10 µA, maximum of 10 mA source
current in all IOs.
VOH2 High output voltage on Port 0 pins VDD – 0.5 – – V IOH = 0.2 mA, maximum of 10 mA
source current in all IOs.
VOH3 High output voltage on Port 1 pins VDD – 0.2 – – V IOH <10 µA, maximum of 10 mA source
current in all IOs.
VOH4 High output voltage on Port 1 pins VDD – 0.5 – – V IOH = 2 mA, maximum of 10 mA
source current in all IOs.
VOL1 Low output voltage – – 0.75 V IOL = 10 mA/pin, VDD > 3.10, maximum of
20/30 mA sink current on even port pins and
of 20/30 mA sink current on odd port
pins.[21]
IOH High output current 0.01 – 2 mA VDD < 2.9 V, maximum of 10 mA source
current in all IOs
IOL1 Low output current on Port 0 pins – – 10 mA VDD < 2.9 V, maximum of 30 mA sink
current on pins P0_2, P1_2, P1_3, P1_4
and 30 mA sink current on pins P0_0, P0_1,
P0_3, P0_4, P1_0, P1_1
IOL2 Low output current – – 20 mA VDD < 2.9 V, maximum of 50 mA sink
current on pins P0_2, P1_2, P1_3, P1_4
and 50 mA sink current on pins P0_0, P0_1,
P0_3, P0_4, P1_0, P1_1
VIL Input low voltage – – 0.75 V VDD = 2.4 to 2.90 V and 3.10 V to 3.6 V.
VIH1 Input high voltage 1.4 – – V VDD = 2.4 to 2.7 V.
VIH2 Input high voltage 1.6 – – V VDD = 2.7 to 2.90 V and 3.10 V to 3.6 V.
VHInput hysteresis voltage – 60 – mV
IIL Input leakage – 1 – nA Gross tested to 1 µA.
CIN Capacitive load on pins as input 0.5 1 .7 5 pF Package and pin dependent.
Temp = 25 °C.
COUT Capacitive load on pins as output 0.5 1.7 5 pF Package and pi n dependent.
Temp = 25 °C
DC POR and LVD Specifications
Parameter Description Min Typ Max Unit Notes
VPPOR0
VPPOR1
VDD value for PPOR trip
VDD = 2.7 V
VDD = 3.3 V, 5 V –
–2.36
2.60 2.40
2.65 V
V
VDD must be greater than or equal to 2.5 V
during startup or internal reset.
VLVD0
VLVD2
VLVD6
VDD value for LVD trip
VDD = 2.7 V
VDD = 3.3 V
VDD = 5 V
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
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DC Flash Write Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical
parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications
are valid only within the range: 25 °C ± 20 °C during the flash write operation. It is at the user’s own risk to operate out of this
temperature range. If flash writing is do ne out of this temperature range, the endurance and data retention reduces.
DC I2C Specifications
This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design
guidance only.
CapSense Electrical Chara cteristics
Symbol Description Min Typ Max Units Notes
VDDIWRITE Supply volt age for flash write operations 2.7 – – V
IDDP Supply current for flash write operations – 5 25 mA
FlashENPB Flash end urance 50,000[23] – – – Erase/write cycles
FlashDR Flash data retention 10 – – Years
Table 9. DC I2C Specifications[22]
Symbol Description Min Typ Max Units Notes
VILI2C Input low level – – 0.3 × VDD V 2.4 V ≤ VDD ≤ 2.9 V
3.1 V ≤ VDD ≤ 3.6 V
– – 0.25 × VDD V4.75 V ≤ VDD ≤ 5.25 V
VIHI2C Input high level 0.7 × VDD – – V 2.4 V ≤ VDD ≤ 5.25 V
VOLP Low output voltage – – 0.4 V IOL = 5 mA/pin
CI2C Capacitive load on I2C pins 0.5 1.7 5 pF Package and pin
dependent. T emp = 25 °C.
RPU Pull-up resistor 4 5.6 8 kΩ–
Max (V) Typ (V) Min (V) Conditions for
Supply Voltage Result
3.6 3.3 3.1 <2.9 The device automatically reconfigures itself to work in 2.7 V mode of
operation.
>2.9 or <3.10 This range is not recommended for CapSense usage.
2.90 2.7 2.45 <2.45 V The scanning for CapSense parameters shuts down until the voltage
returns to over 2.45 V.
>3.10 The device automatically reconfigures itself to work in 3.3 V mode of
operation.
<2.4 V The device goes into reset.
5.25 5.0 4.75 <4.73 V The scanning for CapSense parameters shuts down until the voltage
returns to over 4.73 V.
Notes
22.All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
23.Commands involving flash writes ( 0x01, 0x02, 0x03) and flash read (0x04) must be exec uted only within the same VCC volt ag e range det ected at POR (power on, or
command 0x06) and above 2.7 V.
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AC Electrical Specifications
AC Chip-Level Specifications
AC GPIO Specifications
Table 10. 5-V and 3.3-V AC Chip -Level Specifications
Parameter Description Min Typ Max Units Notes
F32K1 Internal low-speed oscillator (ILO)
frequency 15 32 64 kHz Calculations during sleep operations
are done based on ILO frequency.
tXRST External reset pulse width 10 – – Us
tPOWERUP Time from end of POR to CPU executing
code – 150 – ms
SRPOWER_
UP Power supply slew rate – – 250 V/ms
Table 11. 2.7-V AC Chip-Level Specifications
Parameter Description Min Typ Max Units Notes
F32K1 Internal low-speed oscillator (ILO)
frequency 8 32 96 kHz Calculations during sleep operations
are done based on ILO frequency.
tXRST External reset pulse width 10 – – Us
tPOWERUP Time from end of POR to CPU executing
code – 600 – ms
SRPOWER_
UP Power supply slew rate – – 250 V/ms
Table 12. 5-V and 3.3-V AC General Purp ose I/O Specifications
Parameter Description Min Max Unit Notes
tRise0 Rise time, strong mode,
Cload = 50 pF, Port 0 15 80 ns VDD = 3.10 V to 3.6 V and 4.75 V to
5.25 V, 10% to 90%
tRise1 Rise time, strong mode,
Cload = 50 pF, Port 1 15 50 ns VDD = 3.10 V to 3.6 V, 10% to 90%
tFall Fall time, strong mode,
Cload = 50 pF, all ports 10 50 ns VDD = 3.10 V to 3.6 V and 4.75 V to
5.25 V, 10% to 90%
Table 13. 2.7-V AC GPIO Specifications
Parameter Description Min Max Unit Notes
tRise0 Rise time, strong mode,
Cload = 50 pF, Port 0 15 100 ns VDD = 2.4 V to 2.90 V, 10% to 90%
tRise1 Rise time, strong mode,
Cload = 50 pF, Port 1 15 70 ns VDD = 2.4 V to 2.90 V, 10% to 90%
tFall Fall time, strong mode,
Cload = 50 pF 10 70 ns VDD = 2.4 V to 2.90 V, 10% to 90%
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Figure 12. Definition of Timing for Fast/Standard Mode on the I2C Bu s
AC I2C Specifications
Parameter Description Standard
Mode Fast Mode Units Notes
Min Max Min Max
FSCLI2C SCL clock frequency 0 100 0 400 kbps Fast mode not supported for
VDD < 3.0 V.
tHDSTAI2C Hold time (repeated) START condition.
After this period, the first clock pulse is
generated
4.0 – 0.6 – µs
tLOWI2C LOW period of the SCL clock 4.7 – 1.3 – µs
tHIGHI2C HIGH period of the SCL clock 4.0 – 0.6 – µs
tSUSTAI2C Setup time for a repeated START condition 4.7 – 0.6 – µs
tHDDATI2C Data hold time 0 – 0 – µs
tSUDATI2C Data setup time 250 – 100 – ns
tSUSTOI2C Setup time for STOP condition 4.0 – 0.6 – µs
tBUFI2C BUS free time between a STOP and START
condition 4.7 – 1.3 – µs
tSPI2C Pulse width of spikes suppressed by the
input filter ––050 ns
I2C_SDA
I2C_SCL
SSr SP
TBUFI2C
TSPI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
START Condition Repeated START Condition STOP Condition
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Appendix – Examples of Frequently Used I2C Commands
Sl
No. Requirement I2C commands[24] Comment
1 Enter into setup mode W 00 A0 08
2 Enter into normal mode W 00 A0 07
3 Loa d factory defaults to RAM
registers W 00 A0 02
4 Do a software reset W 00 A0 08
W 00 A0 06 Enter into setup mode
Do software reset
5 Save current configu ration to flash W 00 A0 01
6 Loa d factory defaults to RAM
registers and save as user
configuration
W 00 A0 08
W 00 A0 02
W 00 A0 01
W 00 A0 06
Enter into setup mode
Load factory defaults to SRAM
Save the configuration to flash. Wait for time specified in
“CapSense Express Commands” on page 17.
Do software reset
7 Enable GP00 as CapSense button W 00 A0 08
W 00 06 01
W 00 A0 01
W 00 A0 06
Enter into setup mode
Configuring CapSense buttons
Save the configuration to flash. Wait for time specified in
“CapSense Express Commands” on page 17.
Do software reset
8 Read CapSense button(GP00)
scan results W 00 81 01
W 00 82
R 00 RD. RD. RD.
Select CapSense button for reading scan result
Set the read point to 82h
Consecutive 6 reads get baseline, difference count and raw
count (all two byte each)
9 Rea d C apSense button status
register W 00 88
R 00 RD Set the read pointer to 88
Reading a byte gets status CapSense inputs
Note
24.The ‘W’ indica tes the writ e transfer and the next byte of d ata represent s the 7-bit I2C address. The I2C address is assumed to be ‘0’ in th e above examp les.
Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations.
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Ordering Information
Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
Table 14.Key Features and Ordering Information
Ordering Code Package
Diagram Package Type Operating
Temperature CapSense
Block GPIOs XRES Pin
CY8C20110-LDX2I 001-09116 16 QFN [25] Industrial Yes 10 Yes
CY8C20110-SX2I 51-85068 16 SOIC Industrial Yes 10 Yes
CY8C20180-LDX2I 001-09116 16 QFN [25] Industrial Yes 08 Yes
CY8C20180-SX2I 51-85068 16 SOIC Industrial Yes 08 Yes
CY8C20160-LDX2I 001-09116 16 QFN [25] Industrial Yes 06 Yes
CY8C20160-SX2I 51-85068 16 SOIC Industrial Yes 06 Yes
CY8C20140-LDX2I 001-09116 16 QFN [25] Industrial Yes 04 Yes
CY8C20140-SX2I 51-85068 16 SOIC Industrial Yes 04 Yes
CY8C20142-SX1I 51-85066 8 SOIC Industrial Yes 04 No
Table 15. Thermal Impedances by Pack age
Package Typical θJA[26]
16 QFN[1] 46 °C/W
16 SOIC 79.96 °C/W
8 SOIC 127.22 °C/W
Table 16. Solde r Reflo w Peak Temperature
Package Maximum Peak Temperature Time at Maximum Peak Temperature
16 QFN[1] 260 °C 20 s
16 SOIC 260 °C 20 s
8 SOIC 260 °C 20 s
Notes
25.Earlier termed as QFN package.
26.TJ = TA + Power × θJA.
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Acronyms
Acronyms Used
Table 17 lists the acronyms that are used in this document.
Reference Document s
CapSense Express Power and Sleep Considerations – AN44209 (001-44209)
Application Notes for Surface Mount Assembly of Amkor's MicroLe adFrame (MLF) Packages – available at http://www.amkor.com.
Document Conventions
Units of Measure
Table 18 lists the unit sof measures.
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’ ). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Table 17. Acro nyms Used in this Datasheet
Acronym Description Acronym Description
AC alternating current LV D low voltage detect
CMOS complementary metal oxide semiconductor MCU microcontroller unit
DC direct current PCB printed circuit board
EEPROM electrically erasable programmable read-only
memory POR power on reset
EMC electromagnetic compatibility PPOR precision powe r on reset
GPIO general-purpose I/O PSoC®Programmable System-on-Chip
I/O input/output PWM pulse width modulator
IDAC current DAC QFN quad flat no leads
ILO internal low speed oscillator RF radio frequency
LCD liquid crystal display SOIC small-outline integrated circuit
LDO low dropout regulator SRAM static random access memory
LED light-emitting diode XRES external reset
LSB least-significant bit
Table 18. Units of Measure
Symbol Unit of Measure Symbol Unit of Measu re
°C degree Celsius mm millimeter
Hz hertz ms millisecond
kbps kilo bits per second mV millivolts
kHz kilohertz nA nanoampere
kΩkilohm ns nanosecond
LSB least significant bit % percent
µA microampere pF picofarad
µF microfarad V volts
µs microsecond W watt
mA milliampere
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Glossary
active high 1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous
time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) conver ter performs
the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference A stable voltage reference desi gn that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth 1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias 1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other fo rce (field) applied to a device to establish a
reference level to operate the device.
block 1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, su ch as a digital
PSoC block or an analog PSoC block.
buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for I/O operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typi cally represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
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compiler A program that translates a high level language, such as C, into machine language.
configuration
space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy
check (CRC) A calculation used to detect errors in data communications, typically performed using a linear
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger A hardware and software system that allows you to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band A period of time when neither of two or more signals are in their active state or in transition.
digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC) A device that chan ges a digital signal to an analog signal of corresponding magni tude. The analog-
to-digital (ADC) converter performs the reverse operation.
duty cycle The relationship of a clock period high time to its low time, expressed as a percent.
emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
External Reset
(XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
Flash An el ectrically programmable and erasable, non-volatile technology that pr ovides you the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is OFF.
Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest
amount of Flash space that may be protected. A Flash block holds 64 bytes.
frequency The number of cycles or events per unit of time, for a periodic function.
gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semicondu ctors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed periphera ls in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
Glossary (continued)
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ICE The in-circuit emulator that allows you to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resume d.
interrupt service
routine (ISR) A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variatio ns of one or more signal characteristic s, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect
(LVD) A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold.
M8C An 8-bit Harvard-architecture microproce ssor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the Flash, SRAM, and register space.
master device A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controll ed device is called the
slave device.
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible minia tu r ization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal T he reference to a circuit containing both analog and digital techniques and componen ts.
modulator A device that imposes a signal on a carrier.
noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.
parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
Glossary (continued)
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port A group of pins, usually eight.
Power on reset
(POR) A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of
hardware reset.
PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-
Chip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM) An output in the form of duty cycle which varies as a function of the app lied measurand
RAM An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register A storage device with a specific capacity, such as a bit or byte.
reset A means of bringing a system back to a know state. See hardware reset and software reset.
ROM An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register A memory storage device that sequentiall y shifts a word either left or right to output a stream of
serial data.
slave device A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM An acronym for static random access memory. A me mory device where you can store and
retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell,
it remains unchanged until it is explicitly altered or until power is removed from the device.
SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform Flash operations. The functi ons of the SROM may be
accessed in normal user code, operating from Flash.
stop bit A signal following a character or block that prepares the receiving device to recei v e the next
character or block.
synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
Glossary (continued)
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tri-state A functi on whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART A UART or universal asynchronous receiver-transmitte r translates between parallel bits of data
and serial bits.
user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide hig h
level API (Application Programming Interface) for the peripheral function.
user space The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD A name for a power net meaning "voltage drain." The most po sitive power supply signal. Usually
5 V or 3.3 V.
VSS A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified
period of time.
Glossary (continued)
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Document History Page
Document Title: CY8C20110, CY8C20180, CY8C20160, CY8C20140, CY8C20142 CapSense® Express™ –
Button Cap a citive Controllers
Document Number: 001-54606
Revision ECN Orig. of
Change Submission
Date Description of Change
** 2741726 SLAN/FSU 07/21/2009 New Datasheet
*A 2821828 SSHH/FSU 12/4/2009 - Add Contents
- Added new electrical specs including F32k u, Tpowerup, and several
output current specs.
- Noted that the flash reads must also be done at POR voltage (previously
only specified flash writes).
*B 2892629 NJF 03/15/2010 Added TBAKETEMP and TBAKETIME parameters in Absolute Maxim um
Ratings.
Changed 16 COL to 16 QFN.
Added Note on page 5.
*C 3002214 SLAN 07/29/2010 Changed the part number from CY8C21110 to CY8C20110 in Features.
Minor edits.
*D 3042142 ARVM 09/30/10 Included footnote for all GP1[1] and GP1[2] pins for all parts under Pinouts
section.
Removed F32ku and tpowerup rows from Absolute Maximum Ratings table.
Included “AC Chip-Level Specifications” section under
“AC Electrical Specifications” section.
Under section "Typical Circuits" schematic for "Circuit 1 - Five Buttons
and Five LEDs with I2C Interface" has been replaced .
Styles update.
*E 3085081 NJF 11/12/10 Removed section “2.7-V DC Spec for I2C Line with 1.8 V External
Pull-up”.
Added DC I2C Specifications table..
Updated Units of Measure, Acronyms, Glossary, and References
sections.
Updated solder reflow specifications.
No specific changed were made to I2C Timing Diagram. Updated for
clearer understanding.
Template and styles update.
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© Cypress Semicondu ctor Corpor ation, 2009-2010. The informatio n contai ned herei n is subject to chan ge without no tice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress produc ts are n ot warranted no r inte nd ed to be us ed fo r
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