PE4272-52 - Peregrine Semiconductor Corp.

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RFC

RF1 RF2

CMOS

Control

Driver

CTRLV

DD

The PE4272 RF Switch is designed for the TV tuner, PCTV, set

top box, DTV, DVR and general broadband applications. This

device offers industry leading broadband linearity, 1.5 kV ESD

tolerance and a simple CMOS interface. The device offers a

simple alternative solution to pin diode and mechanical relay

switches.

The PE4272 SPDT High Power RF Switch is manu factured on

Peregrine’s UltraCMOS™ process, a patented variation of

silicon -on-insulator (SOI ) technology on a sapphire substrate,

off eri ng th e per formance of GaAs wi th th e economy and

integration of conventional CMOS.

Pro duct Specificat ion

SPDT Broadband UltraCMOS™

DC – 3 GHz RF Switch

Product Description

Figure 1. Functional Diagram

PE4272

Features

• High ESD tolerance of 1.5 kV

• Single-pin CMOS logic control

• Low i nser ti o n l oss : 0.5 dB at 10 00 MHz ,

0.6 dB at 2000 MHz

• Isolation of 43 dB at 1000 MHz, 33 .5 dB

at 2000 MH z

• Typical input 1 dB compression point of

+32 dBm

• Small 8-lead MSOP package

Notes: 1. Device linearity will begin to degrade below 5 MHz.

2. Me as ur ed wit h a 1 ns ris et i m e, 0/3 V puls e and 50 0 MH z ban dw i dt h.

3. Measured in a 50  system.

Fig ur e 2. Pac kage Typ e

Table 1. Electrical Specifications @ +25 °C, VDD = 3 V (ZS = ZL = 75  )

8-lead MSOP

Parameter Conditions Min Typ Max Units

Operation Frequency1 DC – 3000 MH z

Insertion Loss 1000 MH z

2000 MH z 0.5

0.6 0.6

0.7 dB

Isolation – RFC to RF1/RF2 1000 MH z

2000 MHz 41

31.5 43

33.5 dB

Isolati on – R F1 t o RF2 1000 MH z

2000 MH z 41

32 43

34 dB

Return Loss 1000 MH z

2000 MH z 19.5

16 dB

‘ON’ Switching Time3 50% CTRL to 0.1 dB final value, 2 GHz 500 1000 ns

‘OFF’ Switching Time3 50% CTRL to 25 dB isolation, 2 GHz 500 1000 ns

Video Feedth rough2,3 <3 mVpp

Input 1 dB Co mpr ess io n3 1000 MHz 30 32 dBm

Input IP3 3 1000 MHz, 20 dBm input power 52 dBm

Product Specification

PE4272

Page 2 of 11

Table 2 . Pin Descriptions

Table 4. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When hand ling this UltraCMOS ™ devi ce, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rating specified in Table 4.

Latc h-Up Avoidance

Unlike conventional CMO S device s, UltraCMOS™

devices are immune to latch-up.

Table 3. Operating Ranges

Note: 4. All RF pins must be DC blocked with an external

series capacitor or held at 0 VDC.

Figure 3. Pin Configuration (Top View)

4272

1

2

3

4

8

7

6

5

V

DD

CTRL

GND

RFC

RF1

GND

RF2

No. Pin

Name Description

1 VDD Nominal +3 V supply connection.

2 CTRL

CMOS lo gic level:

High = RFC to RF 1 signal path

Low = RFC to RF2 signal path

3 GND

Ground connection. Traces should be

physically short and connected to ground

plane for best performance.

4 RFC RF Common port.4

5 RF2 RF2 port.4

6 GND

Ground Connection. Traces should be

physically short and connected to ground

plane for best performance.

7 GND

Ground Connection. Traces should be

physically short and connected to ground

plane for best performance.

8 RF1 RF1 port.4

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any input -0.3 VDD+

0.3 V

TST Storage temperature range -65 150 °C

PIN Input po wer ( 5 0 ) 34 dBm

VESD ESD voltage (HBM, ML_STD

883 Method 30 15 . 7) 1500 V

Parameter Min Typ Max Units

VDD Power Supply Voltage 2.7 3.0 3.3 V

IDD Power Su pply Cu rrent

(VDD = 3 V, CTRL = 3 V) 8 20 µA

Control Voltage High 0.7xVDD V

Control Voltage Low 0.3xVDD V

Operating temperature

range -40 85 °C

Absolute Maximum Ratings are those values

listed in the above table. Exceeding these values

may c aus e permanent dev i ce damag e.

Functional operation should be restricted to the

limits in the Operating Ranges table. Exposure to

absolute maximum ratings for exte nded periods

may a ffect device reliability.

Product Specification

PE4272

Page 3 of 11

Control Voltages Signal Path

Pin 1 (VDD) = VDD

Pin 2 (CTRL) = High RFC to RF1

Pin 1 (VDD) = VDD

Pin 2 (CTRL) = Low RFC to RF2

Table 5. Single-pin Control Logic Truth Table

Table 6. Complementary-pin Control Logic

Truth Table

Control Voltages Signal Path

Pin 1 (VDD) = Low

Pin 2 (CTRL) = High RFC to RF1

Pin 1 (VDD) = H i gh

Pin 2 (CTRL) = Low RFC to RF2

Control Logic Input

The PE4272 is a versatile RF CMOS switch that

supports two operatin g control modes; single-pin

control mode and complementary-pin control

mode.

Single-pin c o ntr ol m od e enables the switch to

operate with a single control pin (pin 2) supporting

a +3-volt CMOS logic input, and requires a

dedicated +3-volt power supply connection (pin 1).

Thi s mo de of op er ation red uce s the number of

control lines required an d simplifies the switch

control interface typically de rived from a CMOS

µProcessor I/O port.

Complementary-pin control mode allo ws the

switch to operate using complementary control

pins CTRL and VDD (pins 2 & 1), that can be

directly driven by +3-volt CMOS logic or a suitab le

µProcessor I/O port. This enables the PE4272 to

operate in positive control voltage mode within the

PE4272 operating limi ts .

Product Specification

PE4272

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Evaluation Kit

The SPDT Switch Evaluation Kit board was

designed to ease customer evaluation of the

PE4272 SPDT switch. The RF common port is

connected through a 75  transmission line to the

bottom F connector, J2. Port 1 and Port 2 are

connected through 75  transmission lines to two F

connectors on either side of the board, J1 and J3. A

through transmission line connects F connectors J4

and J5. This transmission line can be used to

estimate the loss of the PCB over the environmental

conditions being evaluated.

The board is constructed of a two metal layer FR4

material with a total thickness of 0.031”. The bottom

layer provides ground for the RF transmission lines.

The transmission lines were designed using a

coplanar waveguide with ground plane model using

a trace width of 0.021”, trace gaps of 0.030”,

dielectric thickness of 0.028”, copper thickness of

0.0021” and r of 4.3.

J6 provides a means for controlling the DC inputs to

the device. The lower right pin (J6-2) is connected

to the device CTRL input. The upper right pin (J6-1)

is connected to the device VDD input. Footprints for

decoupling capacitors are provided on both CTRL

and VDD traces . It is th e respon s ibility of the

customer to determine proper supply decoupling for

their design application. Removing these

components from the evaluation board has not been

shown to degrade RF performance.

Figure 4. Evaluation Board Layouts

Figure 5. Evaluation Board Schematic

Peregr ine s pec ificat ion 102/0309

Peregr ine s pec ificat ion 101/0243

Product Specification

PE4272

Page 5 of 11

Figure 7. Insertion Loss: RFC-RF1 @ 3 V Figure 6. Insertion Loss: RFC-RF1 @ 25 °C

Typical Performance Data

Figure 8. Insertion Loss: RFC-RF2 @ 25 °C Figure 9. Insertion Loss: RFC-RF2 @ 3 V

Product Specification

PE4272

Page 6 of 11

Figure 11. Isolation: RFC-RF1 @ 3 V Figure 10. Isolation: RFC-RF1 @ 25 °C

Typical Performance Data

Figure 12. Isolation: RFC-RF2 @ 25 °C Figure 13. Isolation: RFC-RF2 @ 3 V

Product Specification

PE4272

Page 7 of 11

Figure 16. Return Loss: RFC-RF1 @ 25 °C Figure 17. Return Loss: RFC-RF1 @ 3 V

Typical Performance Data

Figure 14. Isolation: RF1-RF2 @ 25 °C Figure 15. Isolation: RF1-RF2 @ 3 V

Product Specification

PE4272

Page 8 of 11

Typical Performance Data

Figure 18. Return Loss: RFC-RF2 @ 25 °C Figure 19. Return Loss RFC-RF2 @ 3 V

Figure 20. Re tur n Loss: RFC-RF1/ RF2 @ 25 °C Figure 21. Re tur n Loss: RFC-RF1/ RF2 @ 3 V

Product Specification

PE4272

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8-lead MSOP

Figure 22. Package Drawing

FRONT VIEW

2.95±0.10

0.08 ABC

0.33 +0.07

-0.08

0.10 A0.10±0.05

3.00±0.10

0.86±0.08

1.10 MAX

- C -

- A -

1

0.65BSC

0.51±0.13

2.45±0.10

0.51±0.13

2X

8

3.00±0.10

.25 A B C

234

- B -

.525BSC

TOP VIEW

567

4.90±0.15

3.00±0.10

SIDE VIEW

2.95±0.10

R 0.90 MIN

0.95 BSC

0.55 ±0.15

R 0.90 MIN

0

o

6

o

12

o

REF

12

o

REF

0.25

GAGE

PLANE

Product Specification

PE4272

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8-lead MSOP

Table 7. Ordering Information

Figure 23. Tape and Reel Specifications

Or der Code Part Marking Description Package Shipping Method

4272-01 4272 P E4 27 2- 0 8 MSO P - 50A 8-l ea d MS OP 50 unit s / Tube

4272-02 4272 PE4 272-08 MSO P - 20 00C 8-l ea d MS OP 2000 units / T&R

4272-00 PE4272-EK PE4272-08MSOP-EK Evaluation Kit 1 / Box

4272-51 4272 PE4272G-08MSOP-50A Green 8-lead MSOP 50 units / Tube

4272-52 4272 PE4272G-08MSOP-2000C Green 8-lead MSOP 2000 units / T&R

Pin1

Product Specification

PE4272

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Sales Offices

The Americas

Peregrine Semiconductor Corporation

9450 Carr oll Park Drive

San Diego, CA 92121

Tel 858-731-9400

Fax 858-731-9499

North Asia Pacific

Peregrine Semiconductor K.K.

5A-5, 5F Imperial Tower

1-1-1 Uchisaiwaicho, Chiyoda-ku

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3-3502-5213

Peregrine Semiconductor, Korea

#B-2402, Kolon Tripolis, #210

Geumgok-dong, Bundang- gu, Seongnam-si

Gyeonggi-do, 463-480 S. Korea

Tel: +82-31-728-4300

Fax: +82-31-728-4305

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Q uatre Vent s

F- 92380 Garches, France

Tel: +33-1-47-41-91-73

Fax : +33-1 -47 -41-91-7 3

For a list of representat ives in your area, please r efer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data

sheet contains design target specificat ions for product

development. Spec ifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in or der

to supply t he best possible product.

Product Specification

The data sheet contains final data . In the event Peregrine

dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify

cust omers of the intended changes by issuing a DCN

(Document Change Notice).

The information in this dat a sheet is believed to be reliable.

Howeve r, Peregrine assum es no liability f or th e use of this

information. Use shall be entir ely at the user’s own risk.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third party.

Peregrine’s pr oducts are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death m ight occur.

Peregr ine assumes no liability for damages, including

consequential or incident al dam ages, arising out of the use of

its products in such applications.

The Peregr ine nam e, logo, and UTSi are register ed tr ademarks

and UltraCMOS and HaRP are trademarks of Peregrine

Semiconductor Corp.

South As ia Pa cific

Peregrine Semiconductor, China

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Spa ce and Defense Products

Americas :

Tel: 505-881-0438

Fax: 505-881-0443

Europe, Asia Pacific:

180 Rue Jean de Guiramand

13852 Aix-En-Provence cedex 3, France

Tel: +33(0) 4 4239 3361

Fax: +33(0) 4 4239 7227