IRFF110 - Intersil Corporation

File Number 1562.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

IRFF110

3.5A, 100V, 0.600 Ohm, N-Channel

Power MOSFET

This N-Channel enhancement mode silicon gate power ﬁeld

effect transistor is an advanced power MOSFET designed,

tested, and guaranteed to withstand a speciﬁed level of

energy in the breakdown avalanche mode of operation. All of

these power MOSFETs are designed for applications such

as switching regulators, switching convertors, motor drivers,

relay drivers, and drivers for high power bipolar switching

transistors requiring high speed and low gate drive power.

These types can be operated directly from integrated

circuits.

Formerly developmental type TA17441.

Features

• 3.5A, 100V

•r

DS(ON) = 0.600Ω

• Single Pulse Avalanche Energy Rated

• SOA is Power Dissipation Limited

• Nanosecond Switching Speeds

• Linear Transfer Characteristics

• High Input Impedance

• Related Literature

- TB334 “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-205AF

Ordering Information

PART NUMBER PACKAGE BRAND

IRFF110 TO-205AF IRFF110

NOTE: When ordering, use the entire part number.

DRAIN

(CASE) SOURCE

GATE

Data Sheet March 1999

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Speciﬁed

IRFF110 UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 100 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V

Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID3.5 A

Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 14 A

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS ±20 V

Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD15 W

Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.12 W/oC

Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 19 mJ

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ= 25oC to 125oC

Electrical Speciﬁcations TC = 25oC, Unless Otherwise Speciﬁed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 100 - - V

Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V

Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA

VDS = 100V, VGS = 0V, TJ = 125oC - - 250 µA

On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 3.5 - - A

Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA

Drain to Source On Resistance (Note 2) rDS(ON) VGS = 10V, ID = 1.5A (Figures 8, 9) - 0.5 0.600 Ω

Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = 1.5A (Figure 12) 1.0 1.5 - S

Turn-On Delay Time td(ON) VDD ≅ 0.5 x Rated BVDSS, ID≈ 3.5A, RG = 9.1Ω

VGS = 10V, RL = 13Ω(Figures 17, 18),

RL = 14Ω for VDS = 50V, RL = 23Ω for VDS = 80V,

MOSFET Switching Times are Essentially

Independent of Operating Temperature

-1020ns

Rise Time tr-1525ns

Turn-Off Delay Time td(OFF) -1525ns

Fall Time tf-1020ns

Total Gate Charge

(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 3.5A, VDS = 0.8 x Rated BVDSS,

IG(REF) = 1.5mA(Figures 14, 19,20), Gate Charge is

Essentially Independent of Operating Temperature

- 5.0 7.5 nC

Gate to Source Charge Qgs - 2.0 - nC

Gate to Drain “Miller” Charge Qgd - 3.0 - nC

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 135 - pF

Output Capacitance COSS -80-pF

Reverse Transfer Capacitance CRSS -20-pF

Internal Drain Inductance LDMeasured from the Drain

Lead, 5.0mm (0.2in) from

Header to Center of Die

Modified MOSFET

Symbol Showing the

Internal Device

Inductances

- 5.0 - nH

Internal Source Inductance LSMeasured from the Source

Lead, 5.0mm (0.2in) from

Header to Source Bonding

Pad

-15-nH

Thermal Resistance, Junction to Case RθJC - - 8.33 oC/W

Thermal Resistance, Junction to Ambient RθJA Free Air Operation - - 175 oC/W

IRFF110

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Continuous Source to Drain Current ISD Modified MOSFET Symbol

Showing the Integral

Reverse P-N Junction

Rectifier

- - 3.5 A

Pulse Source to Drain Current (Note 3) ISM - - 14 A

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 3.5A, VGS = 0V (Figure 13) - - 2.5 V

Reverse Recovery Time trr TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/µs - 200 - ns

Reverse Recovery Charge QRR TJ = 150oC, ISD = 3.5A, dISD/dt = 100A/µs - 1.0 - µC

Forward Turn-On Time tON Intrinsic Turn-On Time is Negligible. Turn-On

Speed is Substantially Controlled by LS + LD--- -

NOTES:

2. Pulse test: pulse width ≤300µs, duty cycle ≤2%.

3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).

4. VDD = 5V, starting TJ= 25oC, L = 2.3mH, RG= 25Ω, peak IAS = 3.5A. See Figures 15, 16.

Typical Performance Curves Unless Otherwise Speciﬁed

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

0 50 100 150

TC, CASE TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

0.2

0.4

0.6

0.8

1.0

1.2

025 50 75 100 125 150

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

t1, RECTANGULAR PULSE DURATION (s)

ZθJC, NORMALIZED

THERMAL IMPEDENCE

10-3 10-2 10-1 1

10-5 10-4

0.01

0.1

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

0.1

0.02

0.2

0.5

0.01

0.05

SINGLE PULSE

IRFF110

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

Typical Performance Curves Unless Otherwise Speciﬁed (Continued)

1 10 100 200

VDS, DRAIN SOURCE VOLTAGE (V)

30.0

10.0

1.0

0.1

ID, DRAIN CURRENT (A)

OPERATION IN THIS

AREA LIMITED

BY rDS(ON)

10µs

100µs

1ms

10ms

100ms

01020304050

VDS, DRAIN TO SOURCE VOLTAGE (V)

8.0

6.4

4.8

3.2

1.6

ID, DRAIN CURRENT (A)

VGS = 10V

VGS = 9V VGS = 8V

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4V

80µs PULSE TEST

1.6

01.0 2.0 3.0 5.0

3.2

4.8

ID, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

6.4

4.0

8.0 80µs PULSE TEST

VGS = 9V

VGS = 10V

VGS = 8V

VGS = 7V

VGS = 6V

VGS = 5V

VGS = 4V

02 6

1.6

4.8

ID(ON), ON-STATE DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

8.0

3.2

6.4

4810

-55oC

VDS > ID(ON) x rDS(ON)MAX

80µs PULSE TEST

25oC

125oC

1.0

1.5

2.0

510 15 20

rDS(ON), DRAIN TO SOURCE

ID, DRAIN CURRENT (A)

0.5

VGS = 10V

VGS = 20V

2µs PULSE TEST

ON RESISTANCE (Ω)

2.50

1.50

1.00

0.50

0-40 0 40

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

ON RESISTANCE

120

2.00

VGS = 10V

ID = 1.5A

IRFF110

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

Typical Performance Curves Unless Otherwise Speciﬁed (Continued)

1.25

1.05

0.95

0.85

0.75 -40 0 40

TJ, JUNCTION TEMPERATURE (oC)

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE

120

1.15

ID = 250µA500

100

010 20

C, CAPACITANCE (pF)

300

VDS, DRAIN TO SOURCE VOLTAGE (V)

400

200 CISS

COSS CRSS

30 40 501

VGS = 0V, f = 1MHz

CRSS = CGD

COSS ≈ CDS + CGD

CISS = CGS + CGD

ID, DRAIN CURRENT (A)

gfs, TRANSCONDUCTANCE (S)

00 1.6 3.2 4.8 6.4

0.8

1.6

2.4

3.2

4.0

8.0

125oC

25oC

-55oC

VDS > ID(ON) x rDS(ON)MAX

80µs PULSE TEST

0 0.4 0.6 0.80.2

0.1

1.0

ISD, SOURCE TO DRAIN CURRENT (A)

VSD, SOURCE TO DRAIN VOLTAGE (V)

150oC

1.0 1.4 1.6 1.81.2 2.0

25oC

Qg(TOT), TOTAL GATE CHARGE (nC)

VGS, GATE TO SOURCE (V)

002468

VDS = 20V

VDS = 50V

VDS = 80V

ID = 3.5A

IRFF110

Test Circuits and Waveforms

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VGS

VDD

VDS

BVDSS

IAS

tAV

VGS

DUT

-VDD

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

0.3µF

12V

BATTERY 50kΩ

VDS

DUT

IG(REF)

(ISOLATED

VDS

0.2µF

CURRENT

REGULATOR

ID CURRENT

SAMPLING

IG CURRENT

SAMPLING

SUPPLY)

RESISTOR RESISTOR

SAME TYPE

AS DUT Qg(TOT)

Qgd

Qgs

VDS

VGS

VDD

IG(REF)

IRFF110

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

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IRFF110