SMSC LAN91C110 Rev. B Page 1 Revision 1.0 (11-04-08)
DATASHEET
LAN91C110 REV. B
FEAST Fast Ethernet
Controller for
PCMCIA and Generic
16-Bit Applications
Product Features
Dual Speed CSMA/CD Engine (10 Mbps and 100
Mbps)
Compliant with IEEE 802.3 100BASE-T
Specification
Supports 100BASE-TX, 100BASE-T4
16 Bit Wide Data Path (into Packet Buffer Memory)
Generic 16-bit System Level Interface Easily
Adaptable to ISA, PCMCIA (16-bit CardBus), and
Various CPU System Interfaces
Support for 16 and 8 Bit CPU Accesses
Asynchronous Bus Interface
128 Kbyte External Memory
Built-in Transparent Arbitration for Slave Se quential
Access Architecture
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
IEEE-802.3 MII (Media Independent Interface)
Compliant MAC-PHY Interface Running at Nibble
Rate
MII Management Serial Interface
IEEE-802.3u Full Duplex Capability
144 Pin TQFP lead-free RoHS Compliant package
(1.0 Millimeter Height)
ORDER NUMBER(S):
LAN91C110-PU for 144 pin TQFP lead-free Ro HS Compliant package
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 2 Revision 1.0 (11-04-08)
DATASHEET
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Copyright © 2008 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
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responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does
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FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 3 Revision 1.0 (11-04-08)
DATASHEET
Table Of Contents
Chapter 1 General Description............................................................................................................................5
Chapter 2 Pin Configuration...............................................................................................................................6
Chapter 3 Description of Pin Functions..............................................................................................................7
Chapter 4 Functional Description.....................................................................................................................11
4.1 Description of Blocks.........................................................................................................................11
4.1.1 Clock Generator Block................................................................................................................11
4.2 CSMA/CD Block................................................................................................................................11
4.2.1 DMA Block..................................................................................................................................11
4.2.2 Arbiter Block................................................................................................................................11
4.2.3 MMU Block..................................................................................................................................12
4.2.4 BIU Block....................................................................................................................................12
4.2.5 MAC-PHY Interface Block ..........................................................................................................12
4.2.6 MII Management Interface Block................................................................................................13
Chapter 5 Data Structures and Registers.................................................................................................. .......15
5.1 Packet Format in Buffer Memory ......................................................................................................15
5.2 Typical Flow of Events for Transmit (Auto Release = 0)...................................................................37
5.3 Typical Flow of Events for Transmit (Auto Release = 1)...................................................................38
5.4 Typical Flow of Events for Receive...................................................................................................40
5.5 Memory Partitioning ..........................................................................................................................46
5.6 Interrupt Generation..........................................................................................................................46
Chapter 6 Operational De scription...................................................................................................................49
6.1 Maximum Guaranteed Ratings*........................................................................................................49
6.2 DC Electrical Characteristics.............................................................................................................49
Chapter 7 Timing Diagrams................................................................................................................ ..............51
Chapter 8 Package Outline................................................................................................................................56
List of Figures
Figure 2.1 – Pin Configuration ......................................................................................................................6
Figure 3.1 - LAN91C110 Block Diagram.....................................................................................................10
Figure 3.2 - LAN91C110 System Diagram .................................................................................................10
Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path...............................................................14
Figure 5.1 – Data Packet Format................................................................................................................15
Figure 5.2 – Interrupt Structure...................................................................................................................33
Figure 5.3 – Interrupt Service Routine........................................................................................................41
Figure 5.4 - RX INTR ..................................................................................................................................42
Figure 5.5 - TX INTR...................................................................................................................................43
Figure 5.6 - TXEMPTY INTR (Assumes auto release option selected)......................................................44
Figure 5.7 - Drive Send and Allocate Routines...........................................................................................45
Figure 5.8 – Interrupt Generation for Transmit, Receive, MMU..................................................................48
Figure 7.1 - Asynchronous Cycle - nADS=0...............................................................................................51
Figure 7.2 - Asynchronous Cycle - USING nADS.......................................................................................51
Figure 7.3 – Address Latching for All Modes..............................................................................................52
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 4 Revision 1.0 (11-04-08)
DATASHEET
Figure 7.4 - SRAM Interface .......................................................................................................................53
Figure 7.5 - MII Interface.............................................................................................................................55
Figure 8.1 - 144 Pin TQFP Package Outlines.............................................................................................56
List of Tables
Table 5.1 - In te r n a l I /O S p ac e M a p p i ng......................................................................................... ...............18
Table 8.1 – 144 Pin TQFP Package Parameters .......................................................................................56
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 5 Revision 1.0 (11-04-08)
DATASHEET
Chapter 1 General Description
The LAN91C110 is designed to facilitate the implementation of second generation Fast Ethernet PC Card
adapters and other non-PCI connectivity products. The LAN91C110 is a digital device that implements the
Media Access Control (MAC) portion of the CSMA/CD protocol at 10 and 100 Mbps, and couples it with a lean
and fast data and control path system architecture to ensure that the CPU to packet RAM data movement
does not cause a bo ttleneck a t 100 Mbps.
The LAN91C110 implements a generic 16-bit host interface which is adaptable to a wide range of system
buses and CPUs. This makes the LAN91C110 ideal for 10/100 Fast Ethernet implementations in systems
based on system buse s other than PCI.
Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding
packets. The LAN91C110 is software compatible with the LAN9000 family of products in the default mode and
can use existing LAN9000 drivers (ODI, IPX, and NDIS) with minor modifications in 16 and 32 bit Intel X86
based environments.
Memory management is handled using a unique patented MMU (Memory Management Unit) architecture
and an internal 32-bit wide data path. This I/O mapped architecture can sustain back-to-back frame
transmission and reception for superior data throughput and optimal performance. It also dynamically
allocates buffer memory in an efficient buffer utilization scheme, re ducing software tasks and relieving the
host CPU from performing these ho usekeeping functi ons. T he total memory size is 1 28 Kbytes (extern al),
equivalent to a total chip storage (transmit and receive) of 64 outstan ding packets.
FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The host
interface is “ISA-like” and is easily adapted to a wide range of system and CPU buses such as ISA,
PCMCIA, etc.
An IEEE-802.3 compliant Media Independent Interface (MII) provided on the network side of the LAN91C110.
The MII interface allows the use o f a w ide range o f MII complian t Phy sical Lay er (PH Y) devices to be used wi th
the LAN91C110. The LAN91 C110 al so pro vide s an interface to the tw o-line MII serial manage ment pro tocol .
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 6 Revision 1.0 (11-04-08)
DATASHEET
Chapter 2 Pin Configuration
LAN91C110
144 Pin TQFP
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VDD
GND
XTAL2
XTAL1
VDD
nCSOUT
TX25
RX_ER
RX_DV
GND
RX25
COL100
CRS100
RXD0
RXD1
RXD2
RXD3
TXD0
TXD1
TXD2
TXD3
TXEN100
nRWE0
RD7
RD6
RD5
RD4
GND
RD3
RD2
RD1
VDD
RD0
RD15
RD14
nLNK
VDD
GND
RD8
RA12
RA4
RA3
GND
nRWE3
RA2
RD24
RD25
RD26
RD27
RD28
RD29
nRWE2
RD30
RD31
VDD
RD16
RD17
RD18
RD19
RD20
GND
RD21
RD22
RD23
RD13
RD12
GND
RD11
RD10
VDD
RD9
nRWE1
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
37
38
39
40
41
42
43
44
A9
A8
A7
A6
A5
A4
A3
A2
A1
GND
D8
D9
VDD
D10
D11
D12
D13
D14
GND
D15
nADS
VDD
RA16
RA14
RA15
RA9
RA10
RA8
RA11
VDD
nROE
RA7
GND
RA13
RA5
RA6
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
nWR
RESET
GND
MCLK
AEN
AUISEL
MDO
MDI
AGND
N/C
AVDD
A10
VDD
nRD
INT0
GND
ARDY
D0
D1
D2
D3
GND
D4
D5
D6
nLDEV
D7
nBE1
nBE0
GND
A15
A14
A13
A12
VDD
A11
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Figure 2.1 – Pin Configuration
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 7 Revision 1.0 (11-04-08)
DATASHEET
Chapter 3 Description of Pin Functions
144 TQFP
PIN NO. NAME SYMBOL BUFFER
TYPE DESCRIPTION
115-112,
110-100 Address A[15:1 ] I Input. Used by LAN91C110 for inte rnal register
selection.
138 Address
Enable AEN I Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low .
118, 117 nBE[1:0] I Input. Used during LAN9 1C110 registe r accesses
to determine the width of the access and the
register(s) being accessed .
89, 91-95,
97-98, 119 ,
121-123,
125-128
Data Bus D[15:0] I/O8 Bidirectional. 16-bit data bus used to acce ss the
LAN91C110’s inte rnal reg isters. Da ta bu s has
weak internal pullups. Supp orts dire ct connection
to the sy stem bu s w ithou t exte rnal bu ffering .
135 Reset RESET IS Input. This input is no t conside red acti ve unless i t
is acti ve fo r a t least 100ns to filter na rrow glitches.
129 Asynchro-
nous
Ready
ARDY OD16 Open drain outpu t. ARD Y may be u sed w hen
interfacing asy nchronous buses to extend
accesses . Its rising (access completion ) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host C PU o r bus clock.
Note: Asserted for 100 to 150ns for the
appropriate NO WAIT bit state in the Configuration
register. See the NO WAIT bit description for
complete info rmation .
120 Local
Device nLDEV O16 Output. Local Device. This active low output is
asserted when AEN i s low and A4-A15 decode to
the LAN91C110 address prog rammed in to the
high byte of the Base Addre ss Register. nLD EV*
is a combina torial de code o f unla tched addre ss
and AEN signals.
88 nAddress
Strobe nADS IS Input. Address strobe. For systems tha t require
address latching . The ri sing edge of nADS
indicates the latching moment of A[1:15] and AEN.
All LAN91C110 internal functions of A[1 :15] and
AEN are latched .
131 Interrupt INTR0 O4 Output. The in te rrupt outpu t is enabl ed by
selecting the appropriate routing bits (INT SEL 1-
0) in the Configuration Register.
132 nRead
Strobe nRD IS Input. Used in a synchron ous bu s in terfaces.
134 nWrite
Strobe nWR IS Input. Used in a synchron ous bu s in terfaces.
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Datasheet
SMSC LAN91C110 Rev. B Page 8 Revision 1.0 (11-04-08)
DATASHEET
144 TQFP
PIN NO. NAME SYMBOL BUFFER
TYPE DESCRIPTION
56-57, 60-
65, 46-48,
50-54, 35-
38, 40-42,
45, 25-28,
30-32, 34
RAM Data
Bus RD[31:0] I/O4 with
pullups Bidirectional. Carries the loca l buffer memory
read and write da ta . Reads a re alway s 32 bi ts
wide. Writes are controlled individually at the by te
level.
86,84,85,
75,72,80, 82-
83,81, 77,74-
73, 71-70,67
RAM
Address
Bus
RA[16:2] O4 Outputs. This bus specifies the buffer RAM
doubleword being a cce ssed by the LAN91 C110 .
78 nROE O4 Output. Acti ve low signal used to read a
doubleword from buffe r RAM.
24,44,58, 68 nRWE[3:0] O4 Outputs. Active low signals used to write any
byte, word or dw ord in RAM.
2
3 Crystal 1
Crystal 2 XTAL1
XTAL2 Iclk An external 25 MHz cry stal is connected across
these pins. If a TTL clo ck is suppl ied instead , it
should be conne cte d to X TAL1 and X TAL2 should
be left open.
1 nLink
Status nLNK I with pullup Input. General purpose inpu t po rt used to convey
LINK status (EPHSR bit 14).
139 AUI Select AUISEL O4 Output. No n vola til e outpu t pin . D riven by AU I
SELECT (CONFIG bit 8).
23 Transmit
Enable
MII
TXEN100 O12 Output to MII PH Y. Envelope to 100 Mbps
transmission.
12 Carrier
Sense MII CRS100 I with
pulldown Input from MII PHY. Envelope of packet re cep tion
used for de ferral and ba ckoff purpose s.
8 Receive
Data Valid RX_DV I with
pulldown Input from MII PHY. Envelope o f data vali d
reception. Used for receive data framing.
11 Collision
Detect MII COL100 I with
pulldown Input from MII PHY. Collision dete ction input.
18,19,21, 22 Transmit
Data TXD[3:0] O12 Outputs. Transmit Data nibble to MII PHY.
6 Transmit
Clock TX25 I with pullup Input. Transmi t cl ock input from MII. Nib ble rate
clock (25 MHz).
10 Receive
Clock RX25 I with pullup Input. Receive clock input from MII PHY. Nibble
rate clock.
16-13 Receive
Data RXD[3:0] I Inputs. Received Da ta nibble from MII PHY.
141 Manage-
ment Data
Input
MDI I with
pulldown MII management data input.
140 Manage-
ment Data
Output
MDO O4 MII management data outpu t.
137 Manage-
ment
Clock
MCLK O4 MII management clock.
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 9 Revision 1.0 (11-04-08)
DATASHEET
144 TQFP
PIN NO. NAME SYMBOL BUFFER
TYPE DESCRIPTION
7 Receive
Error RX_ER I with
pulldown Input. Indicates a code e rror detected by PH Y.
Used by the LAN91C110 to discard the packet
being received. The error indication reported for
this event is the same as a bad CRC (Receive
Status Word bit 13).
5 nChip
Select
Output
nCSOUT O4 Output. Chip Select pro vided for mappin g of PH Y
functions into LAN91C110 de coded space . Active
on accesse s to L AN91C110’s eigh t lowe r
addresses when the BANK SELEC TED is 7.
4,20,33,43,5
5,66,79,
87,96,111,13
3
Power VDD +5V power supply pins.
144 Analog
Power AVDD +5V analog power supp ly pin s.
9,17,29,39,4
9,59,69,
76,90,99,
116,124,
130,136,
Ground GND Ground pins.
142 Analog
Ground AGND Analog ground pin .
BUFFER TYPES
O4 OUTPUT BUFFER WITH 2MA SOURCE AND 4MA SINK
O12 Output buffer with 6mA source and 12mA sink
OD16 Open drain buffer with 16mA sink
I/O4 Bidirectional buffer with 2mA source and 4mA sink
I/O8 Bidirectional buffer with 4mA source and 8mA sink
IS Schmitt Trigger (Hysteresis: 250mV)
I with pullup Rated at 30mA
I with pulldown Rated at 30mA
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 10 Revision 1.0 (11-04-08)
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Figure 3.1 - LAN91C110 Block Diagram
Figure 3.2 - LAN91C110 System Diagram
ADDRESS
CONTROL
DATA
ADDRESS
CONTROL
DATA
SYSTEM BUS
MII
RD0-31OE,WERA
SRAM
32kx81234
LAN91C110
FEAST 100BASE-T4
INTERFACE
CHIP 100BASE-T4
100BASE-TX
INTERFACE
LOGIC/
10BASE-T
100BASE-TX/
10BASE-T
OR
BUS
INTERFACE
UNIT
ARBITER
MEMORY
MANAGEMENT
UNIT
DIRECT
MEMORY
ACCESS
MEDIA
ACCESS
CONTROL
RD
FIFO WR
FIFO
Address
Data
Control
RAM 25 MHz
10/100 Mb/s
Media
Independent
Interface
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 11 Revision 1.0 (11-04-08)
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Chapter 4 Functional Description
4.1 Description of Blocks
4.1.1 Clock Generator Block
1. The X TAL1 and X TAL2 pins a re to be conne cted to a 25 MH z 50 PPM cry stal .
2. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a
10 Mbps PHY, and 25 MHz for a 100 Mbp s PH Y).
3. RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the
receive state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
4.2 CSMA/CD Block
This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out of
the block consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of the
FIFO stores 32 bits to exploit the 32 bit data path into memory, but the FIFOs themselve s are 16 bit w ide. The
Control Path consists of a set of registers interfaced to the CPU via the BIU.
4.2.1 DMA Block
This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing received
data. It interfaces the CSMA/CD Transmit and Receive FIFOs on one side, and the Arbiter block on the other.
To increase the bandwidth into memory, a 50 MHz clock is used by the DMA block, and the data path is 32
bits wide.
For example, du ring active re ception at 100 Mbp s, the C SMA/CD block will write a word into the Receive FIFO
every 160ns. The DMA will read the FIFO and accumulate two words on the output port to request a memory
cycle from the Arbi te r every 320ns.
The DMA machine is able to support full duplex operation. Independent receive and transmit counters are
used. Transmit and receive cycles are alternated when simultaneous receive and transmit accesses are
needed.
4.2.2 Arbiter Block
The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU
requests represent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD
data movemen t. The exte rnal memo ry u sed is a 25n s SRAM.
The Arbiter is also responsible for controlling the nRWE0-nRWE3 lines as a function of the bytes being
written. Read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the
appropriate lane s as a function of the a ddre ss.
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The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs
can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready'
whenever a cycle is initia ted that cannot be satisfied by the present sta te of the FIFO.
4.2.3 MMU Block
The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also
determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2k,
with a maximum me mory si ze o f 128k. MIR and MC R valu es are in terpre ted in 512 by te un its.
4.2.4 BIU Block
The Bus Interface Unit can handle synchronous as w ell as asynchronous buses; different signals are used for
each one. Transparent la tches a re added on the address pa th u sing ri sing n AD S fo r latch ing .
With ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for
notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the
leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C110 clock
and, therefore, asynchron ous to the bus.
The BIU is implemented using the following principles:
1. Addre ss decoding is based on the values o f A15 -A4 and AEN.
2. Address latching is performed by using transparent latches that are transparent when nADS=0 and
nRD=1, nWR=1 and latch on nADS rising edge.
3. Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword
write to offset Ch w ill only w rite the BANK SELECT REGISTER (offse t Fh).
4. No bus by te sw apping is implemen ted (no eigh t bit mode ).
5. Wo rd sw apping as a function of A1 i s imp lemen ted for 16 bi t bu s suppo rt.
6. The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading
edge of the strobe. The ARDY trailing edge i s con trolled by CLK.
4.2.5 MAC-PHY Interface Block
For the MII i nterface, tr ansmit dat a is clock ed out using t he TX25 clo ck input, while receiv e data is c locked i n
using RX25.
In 100 Mbps mode , the LAN9 1C110 provides the follow ing inte rface signals to the PHY :
For transmission : TXEN100 TXD0-3 TX25
For reception: RX_DV RX_ER RXD0-3 RX25
For CSMA/CD state machines: CRS100 COL100
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble
nibble. T XD0 carries t he least si gnifican t bit of the ni bble (that is t he one th at would go f irst out of t he EPH at
100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and TXD0-TXD3 are clocked
by the LAN91C110 using TX25 rising edges. TXEN100 goes inactive at the end of the packet on the last
nibble of the CRC.
During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to the
LAN91C110’s clocks and w ill be sy nchroni zed inte rnally to TX25 .
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
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DATASHEET
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will be
present at RXD0-RXD3 when RX_DV is activated. The LAN91C110 requires no training sequence beyond
a full flag octet for reception. RX_DV as well as RXD0-RXD3 are sampled on RX25 rising edges. RXD0
carries the least significant bit and RXD3 the most significant bit of the nibble. RX_DV goes inactive when
the last valid nibble of the packet (CRC) is presented at RXD0-RXD3.
RX_ER might be asserted during packet reception to signal the LAN91C110 that the present receive packet
is invalid . The LAN91C110 w ill disca rd the packet by trea ting i t as a CRC error.
RXD0-RXD3 should always be aligned to packet nibbles, therefore, opening flag detection does not
consider misaligned cases. Opening flag detection expects the 5Dh pattern and will not reject the packet on
non-preamble pa tterns .
CRS100 is used as a frame envelope signal for the CSMA/CD MAC state machines (deferral and backoff
functions), but it is not used for receive framing functions. CRS100 is an asynchronous signal and it will be
active whenever the re is ac tivity on the cable, including L AN91C110 transmissions and colli sion s.
The MII SELECT bit in the CONFIG REGISTER must always be set for prope r chip function .
Note that given the modular nature of the MII, TX25 and RX25 cannot be assumed to be free running
clocks. The LAN91C110 will not rely on the presence of TX25 and RX25 during reset and will use its own
internal clock w henever a timeou t on TX25 i s de te cted.
4.2.6 MII Management Interface Block
PHY management through the MII management interface is supported by the LAN91C110 by providing the
means to drive a tri-statable data output, a clock, and reading an input. Timing and framing for each
management command is to be genera ted by the CPU.
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8-16 bit
Bus
Interface
Unit
Arbiter
DMA
MMU
Ethernet
Protocol
Handler
(EPH)
External SRAM
WR
FIFO
RD
FIFO
Control
RX Data
TX Data
Control
Control
Address
Data
Control Control
RXD[0-3]
TXD[0-3]
Control
TX/RX
FIFO
Pointer
Control
EEPROM
INTERFACE
32-bit Data
32-bit Data
Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path
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Chapter 5 Data Structures and Registers
5.1 Packet Format in Buffer Memory
The pack et for mat i n memo ry is s imil ar for t he T ransm it an d Rec eive are as. T he first word is res erv ed for t he
status word. The next word is used to specify the t otal number of bytes, and it is follo wed by the data area.
The data are a hold s the packe t itsel f.
Figure 5.1 – Data Pac ket Format
TRANSMIT PACKET RECEIVE PACKET
STATUS WO RD Written by CSMA upon transmit
completion (see Status Register) Written by CSMA upon receive
completion (see RX Frame
Status Word)
BYTE COUNT Written by CPU Written by CSMA
DATA AREA Written/modified by CPU Written by CSMA
CONTROL BYTE Written by CPU to control
odd/even data bytes Written by CSMA; also has
odd/even bit
BYTE COUNT - Divided by two, it defines the total number of words including the STATUS WO RD, the BYTE
COUNT WORD, the DATA AREA and the CONTROL BYTE.
RESERVED BYTE COUNT (always even)
STATUS WORD
DATA AREA
LAST DATA BYTE (if odd)
bit0
bit15
RAM
OFFSET
(DECIMAL)
0
2
4
2046 Max CONTROL BYTE
Last Byte
1st Byte2nd Byte
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The receive byte count always appears as even; the ODDFRM bit of the receive status word indicates if the low byte of
the last word is relevant.
The tran smit byte coun t lea st signi fican t bi t w ill be a ssu med 0 by the con troller regardle ss of the value written in memo ry.
DATA AREA - The data area starts a t offset 4 o f the packet structure and can extend up to 2043 by tes.
The data area contains six bytes of DESTINATION ADDRESS followed by six bytes of SOURCE ADDRESS, followed by
a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
LAN91C110 does not in se rt its ow n source add ress. On receive, all bytes a re provided by the CSMA side.
The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by the LAN91C110. It is treated transparently
as data both for transmit and receive operations.
CONTROL BYTE - For transmit packets the CONTROL BYTE is written by the CPU as:
X X ODD CRC 0 0 0 0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the
number of da ta by tes is e ven and the by te be fore th e CON TROL B Y TE is no t tran smit ted.
CRC - When set, CRC w ill be appende d to the frame . This bit ha s only meaning i f the N OCRC bi t in the TCR is set.
For receive packets the CONTROL BYTE is written by the controller as:
0 1 ODD 0 0 0 0 0
ODD - If set, indicates an odd number of bytes, with the last byte being right before the CONTROL BYTE. If clear, the
number of da ta by tes is e ven and the by te befo re th e CO NTROL B YTE shou ld be igno red .
RECEIVE FRAME STATUS WORD
This word is written at the beginning of each receive frame in memory. It is not available as a register.
HIGH
BYTE ALGN
ERR BROD
CAST BAD
CRC ODD
FRM TOOLNG TOO
SHORT
LOW
BYTE HASH VALUE MULT
CAST
5 4 3 2 1 0
ALGNERR - Frame had alignment error. When MII SEL=1 alignment erro r is set when BADCRC =1 and an odd number of
nibbles was received be tween SFD an d RX_DV going inactive.
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BRODCAST - Re ceive frame w as broad cast.
BADCRC - Frame had CRC error, or RX_ER was asserted during recep tion.
ODDFRM - This bit w hen se t indi cates that the recei ved frame had an odd number o f by tes.
TOOLNG - Frame length was longe r than 802 .3 maximum size (1518 byte s on the cable).
TOOSHORT - Frame length was shorter than 802.3 minimum size (64 bytes on the cable).
HASH VALUE - Provides the hash value used to index the Multicast Registers. Can be used by re ceive routines to speed
up the group address search. The hash value consists of the six most significant bits of the CRC calculated on the
Destination Address, and maps into the 64 bit multicast table. Bits 5,4,3 of the hash value select a byte of the multicast
table, while bits 2,1,0 determine the bit within the byte selected. Examples of the address mapping:
ADDRESS HA SH VALUE 5-0 MULTICAST TA BLE B IT
ED 00 00 00 00 00
0D 00 00 00 00 00
01 00 00 00 00 00
2F 00 00 00 00 00
000 000
010 000
100 111
111 111
MT-0 bit 0
MT-2 bit 0
MT-4 bit 7
MT-7 bit 7
MULTCAST - Receiv e fram e was m ulti cast. If hash val ue corr espo nds to a multi cast ta ble bit t hat is set, and th e addre ss
was a multicast, the packet will pass address filt ering rega rdless o f o ther filtering cri teria.
I/O SPACE
The base I/O space is specified by the power-up I/O Base Register default. To limit the I/O space requirements to 16
locations, the registers are assigned to different banks. The last word of the I/O area is shared by all banks and can be
used to change the bank in u se. Regi sters are de scribed u sing the following con vention :
OFFSET NAME TYPE SYMBOL
HIGH
BYTE bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
X X X X X X X X
LOW
BYTE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
X X X X X X X X
OFFSET - Defines the address offset within the IOBASE where the register can be accessed at, provided the bank select
has the ap propria te value .
The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.
The odd byte can be a cce ssed using addre ss (offset + 1 ).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight bit registers, in that
case the o ffse t o f each on e is independen tly spe cified .
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Regardless of the functi onal descrip tion , all re gisters can be accessed as doublewords, w ords or bytes.
The default bi t values upon h ard re set a re highli ghted b elow each register.
Table 5.1 - In te r n a l I/ O Sp a ce Mapp i ng
BANK0 BANK1 BANK2 BANK3
0 TCR CONFIG MMU COMMAND MT0-1
2 EPH STATUS BASE PNR MT2-3
4 RCR IA0-1 FIFO PORTS MT4-5
6 COUNTER IA2-3 POINTER MT6-7
8 MIR IA4-5 DATA MGMT
A MCR - DATA REVISION
C RESERVED (0) CONTROL INTERRUPT RCV
E BANK SELEC T BANK SELECT BANK SELECT BANK SELEC T
A special BANK (BANK7) exists to support the addi tion of external reg isters.
BANK SELECT REGISTER
OFFSET NAME TYPE SYMBOL
E BANK SELECT
REGISTER READ/WRITE BSR
HIGH
BYTE 0 0 1 1 0 0 1 1
0 0 1 1 0 0 1 1
LOW
BYTE BS2 BS1 BS0
X X X X X 0 0 0
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the
register bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C110.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2.
Note: The bank select register can be accessed as a word at offset 0x0Eh, or as a byte at offset 0x0Fh.
BANK 7 has no internal regis ters other than the BANK SELECT REGISTER itself. On valid cycles wh ere BANK7 is
selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external reg isters.
Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be
done if the Revision Control register indicates the device is the LAN91C110.
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BANK 0
OFFSET NAME TYPE SYMBOL
0 TRANSMIT CONTROL
REGISTER READ/WRITE TCR
This register hold s bi ts programme d by the CPU to control some of the protocol transmit options.
HIGH
BYTE SWFDUP Reserved EPH
LOOP STP
SQET FDUPLX Re served Reserved NOCRC
0 0 0 0 0 0 0 0
LOW
BYTE PAD_EN Reserved Reserved Reserved Reserved FORCOL Reserved TXENA
0 0 0 0 0 0 0 0
SWFDUP - Enables Switched Full Duplex mode . In this mode, transmit state machine is inhi bi ted from re cognizing ca rrier
sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision related status bits in the EPHSR are
not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and SNGL COL). Uses COL100 as flow control, limiting
backoff and jam to 1 clock each before inter-frame gap, then retry will occur after IFG. If COL100 is active during
preamble, full preamble will be output before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have
no effect. This bit sh ould be low for no n-MII opera tion .
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults low. When
EPH_LOOP i s h ig h the f o ll o wing tr an sm it ou t puts are forc ed in act i ve: T XD 0- T XD3 = 0 h, T XEN1 00 = T XE N = 0, TXD = 1.
The follow ing and external in puts a re blocked : CRS=CRS100=0 , C OL=COL100=0, RX_DV= RX_ER=0.
STP_SQET - Stop transmission on SQET error. If set, stops and disables transmitter on SQE test error. Does not stop on
SQET error and transmits next fra me i f clea r. Defaul ts low .
FDUPLX - When set the LAN91C110 w ill cause fra mes to be received if they pass the address filter regardless of the
source for the frame. When clea r the node w ill not receive a frame sou rced by itsel f. Th is bi t doe s n ot con trol the duplex
mode operation, the duplex mode opera tion is controll ed by the SWFDUP bit.
NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired CRC. Defaults to
zero, namely CRC in se rted .
PAD_EN - When se t, the LAN 91C110 w ill pad tra nsmit frames shor ter than 64 by te s with 00. Fo r TX, CPU should write
the actual BYTE C OUNT be fore padded by the LAN91C110 to th e buffer RAM, excludes the padded 00. When this bit is
cleared, the L AN91C110 does not pad fra mes.
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set and cleared only
by the CPU. When TXENA is enabled with no packe ts in the queue and w hile th e FORC OL bit is se t, the LAN91C110 w ill
transmit a preamble pattern the next time a carrier is seen on the line. If a packet is queued, a preamble and SFD will be
transmitted. This bit defaults low to normal operation. NOTE: The LATCOL bit in the EPHSR, setting up as a result of
FORCOL, will reset TXEN A to 0. In order to force another collision , TXENA mu st be set to 1 again .
TXENA - Transmit enabled when set. Transmi t is disab led if clear. When the bit is clea red the LAN91C110 will comple te
the current transmission befo re stopping . When stopping due to an error, thi s bi t is a uto ma tically cl eared .
SMSC LAN91C110 Rev. B Page 20 Revision 1.0 (11-04-08)
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BANK 0
OFFSET NAME TYPE SYMBOL
2 EPH STATUS REGISTER READ ONLY EPHSR
This register stores the status of the last transmitted frame. This register value, upon individual transmit packet
completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use
the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used
for real time values (like TXENA and LIN K OK). If TXENA is cleared the register holds the last packet completion statu s.
HIGH
BYTE Reserved LINK_
OK Reserved CTR
_ROL EXC
_DEF Re served LATCOL Reserved
0 -nLNK
pin 0 0 0 0 0 0
LOW
BYTE TX
DEFR LTX
BRD SQET 16COL LTX
MULT MUL
COL SNGL
COL TX_SUC
0 0 0 0 0 0 0 0
LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value
of this bit gene rates an in terrupt.
CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by
reading the ECR register.
EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte times. Cleared
at the end of every packet sent.
LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into
the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting
TXENA in TC R.
TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 μs of the inter frame gap. Cleared at
the end of eve ry packet sen t.
LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit
frame.
SQET - Signal Quality Error Test. SQET bit is al ways set after first transmit, except if SWFDUP=1. As a consequence,
the STP_SQET bit in the TCR register cannot be set as it will always result in transmit fatal error. Transmission stops and
EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit is cleared by setting TXENA high.
16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset.
Cleared when TXENA i s se t high.
LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit
frame.
MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced.
Cleared when TX_ SUC i s high at the end of the pa cket being sent.
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SNGLCOL - Single collision detected for the last transmit frame. Set when a collision is detected. Cleared when TX_SUC
is high at the end o f the packe t being sen t.
TX_SUC - Last transmit was successful. Set if transmit completes without a fatal error. This bit is cleared by the start of a
new frame transmi ssio n or when TXENA i s se t high. Fatal errors are:
16 collisions (1 /2 duplex mod e only )
SQET fail and STP_SQET = 1 (1/2 duplex mode only)
Late collision (1/2 duplex mode only )
BANK 0
OFFSET NAME TYPE SYMBOL
4 RECEIVE CONTROL REGISTER READ/WRITE RCR
HIGH
BYTE SOFT
RST FILT
CAR ABORT_E
NB Reserved Reserved Reserved STRIP
CRC RXEN
0 0 0 0 0 0 0 0
LOW
BYTE Reserved Reserved Reserved Reserved Reserved ALMUL PRMS RX_
ABORT
0 0 0 0 0 0 0 0
SOFT_RST - Software-Activated Rese t. Acti ve high. Initia ted by w riting this bit high and termina ted by w riting the bit low.
The LAN91C110’s configuration i s not p reserved excep t for Configu ration, Base, and IA0-IA5 Registers. EEPROM is not
reloaded after software reset.
FILT_CAR - Filter Carrier. When set filters leading edge of carrier sense for 12 bit times (3 nibble times). Otherw ise
recognizes a receive frame a s soon as carrier sense i s acti ve . (Does N OT fil te r RX D V o n M II!)
ABORT_ENB - Enables abort of re ceive w hen colli sion occu rs. De faults low . When set, the LAN91C110 will
automatical ly abo rt a pa cke t being rece ived w hen the app ropria te colli sion input is This bi t h as no e ffe ct i f the SWFDUP
bit in the TCR is set.
STRIP_CRC - When set it strips the CRC on received frames. When clear the CRC is stored in memory following the
packet. Defaul ts low .
RXEN - Enables the receive r when set. If cleared, completes receiving cu rrent frame and then goes idle. Defaul ts low on
reset.
ALMUL - When set a ccep ts all multica st fra mes (frames i n w hich the first bi t of DA i s '1'). When clear accep ts only the
multicast frames that match the multicast table setting. Defaults low.
PRMS - Promiscuous mode. When set receives all frames. Does not rece ive i ts own transmission unless it is in Full
Duplex!
RX_ABORT - This bi t is set i f a receiv e fra me was a borted due to leng th longer than 2K by tes. The frame will no t be
received. The bit is cleared by RESET or by the CPU writing it low.
Reserved - Must be 0.
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BANK 0
OFFSET NAME TYPE SYMBOL
6 COUNTER REGISTER READ ONLY ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared
when reading the registe r and do no t w rap around bey ond 15.
HIGH
BYTE NUMBER OF EXC. DEFFERED TX NUMBER OF DEFFERED TX
0 0 0 0 0 0 0 0
LOW
BYTE MULTIPLE COLLISION COUNT SINGLE COLLISION COUNT
0 0 0 0 0 0 0 0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS REGISTER bit
description, occurs. Note that the counters can only increment once per enqueued transmit packet, never faster, limiting
the rate of interrupts that can be generated by the counters. For example if a packet is successfully transmitted after one
collision the SINGLE COLLISION COUNT field is incremented by one. If a packet experiences between 2 to 16 collisions,
the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences deferral the NUMBER OF
DEFERRED TX field is incre mented by one, even if the packet experienced mul tiple de ferral s durin g its col lision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts
are generated on successfu l transmi ssi ons.
Reading the register in the tran smit service routine will be enough to main tain stati stics.
BANK 0
OFFSET NAME TYPE SYMBOL
8 MEMORY INFORMATION REGISTER READ ONLY MIR
HIGH
BYTE FREE MEMORY AVAILABLE (IN BYTES * 256 * M)
1 1 1 1 1 1 1 1
LOW
BYTE MEMORY SIZE (IN BYTES *256 * M)
1 1 1 1 1 1 1 1
FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The
register defaults to the MEMORY SIZE upon re set or upon the RESET MMU command .
MEMORY SIZE - This register can be read to determine the to tal memo ry size.
All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR
upper byte.
These register de faul t to FFh, which should be in terpre ted as 256 .
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BANK 0
OFFSET NAME TYPE SYMBOL
A MEMORY CONFIGURATION
REGISTER Lower Byte -
READ/WRITE
Upper Byte -
READ ONLY
MCR
HIGH
BYTE MEMORY SIZE MULTIPLIER
0 0 1 1 0 1 0 1
LOW
BYTE MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)
0 0 0 0 0 0 0 0
MEMORY RESERVED FOR TRANSMIT - Programming this value allows the host CPU to reserve memory to be used
later for transmit, limiting the amount of memory that receive packets can use. When programmed for zero, the memory
allocation between tr an sm it an d r ec e iv e is co mpl et e l y d yna m ic. Whe n pr o gr am m e d f or a no n- z er o v a lue , th e al l oc at i o n is
dynamic if the free memory exceeds the programmed value, while receive allocation requests are denied if the free
memory is less or equal to the programmed value. This register defaults to zero upon reset. It is not affected by the
RESET MMU command .
The value w ritten to the MCR is a reserved memory spac e IN ADDITION TO ANY MEMORY C URREN TLY IN USE. If the
memory allocated for transmit plus the reserved space for transmit is required to be constant (rather than grow with
transmit allocation s) the CPU should up date the va lue of this register a fter a llocating or releasing memo ry.
The contents of the MIR as well as the low byte of the MCR are specified in units of 256 * M bytes, where M is the
Memory Size Multip lier. M=2 for the LAN91 C110. A value of 04h in the lower by te of the MCR is equal to one 2K page (4
* 256 *2 = 2K); since memory must be reserved in multiples of pages, bits 0 and 1 of the MCR should be written to 1 only
when the enti re me mory is being reserved fo r tran smi t (i .e., low byte of MC R = FF h).
BANK1
OFFSET NAME TYPE SYMBOL
0 CONFIGURATION REGISTER READ/WRITE CR
The Configuration Register holds bits that define the adapter configuration and are not expected to change during run-
time. This register is part of the EEPROM saved setup.
HIGH
BYTE MII
SELECT Reserved NO WAIT Reserved
FULL
STEP Re served AUI
SELECT
1 0 1 0 0 0 0 0
LOW
BYTE 1 Reserved Reserved INT SEL1 INT SEL0
1 0 1 1 0 0 0 1
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MII SELECT - Used to select the network interface port. When set, the LAN91C110 will use its MII port and interface a
PHY device at the nibble rate . This bit must always be set fo r proper chip function.
NO WAIT - When set, does not request additional wait states. An exception to this are accesses to th e Data Register i f not
ready for a transfe r. When clea r, negate s ARD Y for two to three clo cks on any cy cle to the LAN91C110 .
FULL STEP - Reserved
AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and can be used as a general
purpose non-vola tile con figuration pin . De faults low .
Reserved - Must be 0.
INT SEL1-0 - Used to select interrup t pin. The bits mu st remain 00 for the in terrup t pin to be as se rted for in terrup t
indication. All other bi t co mbination s are undefined .
BANK 1
OFFSET NAME TYPE SYMBOL
2 BASE ADDRESS REGISTER READ/WRITE BAR
This register holds the I/O address de code op tion chosen for the LAN91C110. Is not usua lly modi fied during run-ti me.
HIGH
BYTE A15 A14 A13 A9 A8 A7 A6 A5
0 0 0 1 1 0 0 0
LOW
BYTE Reserved 1
0 0 0 0 0 0 0 1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the
LAN91C110‘s registers. The 64k I/O spa ce is fully decoded by the LAN91C110 dow n to a 16 location space, there fo re the
unspecified address lines A4 , A10 , A11 and A12 must be all zeros.
The I/O base de code de faul ts to 300h (name ly, the high by te de faul ts to 18h ).
Reserved - Must be 0.
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BANK 1
OFFSET NAME TYPE SYMBOL
4 THROUGH 9 INDIVIDUAL ADDRESS REGISTERS READ/WRITE IAR
These registers are required to be written by the host following power-up and hardware reset. For PC Card designs, the
CIS contains the node address. The S/W driver must load that address into these registers. The registers are modified by
the software driver. Bit 0 of Individual Addre ss 0 registe r corresponds to the first bit o f the address on the cable .
LOW
BYTE ADDRESS 0
0 0 0 0 0 0 0 0
HIGH
BYTE ADDRESS 1
0 0 0 0 0 0 0 0
LOW
BYTE ADDRESS 2
0 0 0 0 0 0 0 0
HIGH
BYTE ADDRESS 3
0 0 0 0 0 0 0 0
LOW
BYTE ADDRESS 4
0 0 0 0 0 0 0 0
HIGH
BYTE ADDRESS 5
0 0 0 0 0 0 0 0
BANK 1
OFFSET NAME TYPE SYMBOL
A
Reserved.
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BANK 1
OFFSET NAME TYPE SYMBOL
C CONTROL REGISTER READ/WRITE CTR
HIGH BYTE Reserved RC V_
BAD Reserved 1 AUTO
RELEASE Reserved 1 Reserved
0 0 0 1 0 0 1 0
LOW BYTE LE
ENABLE CR
ENABLE TE
ENABLE 1 Reserved
Reserved Reserved Reserved
0 0 0 1 0 0 0 0
RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and their
memory i s rel ea sed .
AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful
(when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet
numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will generate an interrupt
only when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence
experiences a fatal error (TX INT will be set). Upon a fatal error TXENA is cleared and the transmission sequence stops.
The packet number that failed, is present in the FIFO PORTS register, and its pages are not released, allowing the CPU
to restart the sequence a fter corrective a ction is taken .
LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into the
EPH INT bit. Clearing the LE ENABLE bit after an EPH INT interrupt, caused by a LINK_OK transition, will acknowledge
the interrup t. LE ENABLE de faults low (disabled ).
CR ENABLE - Counter Roll over Enable. When set, it enables the CTR_ROL bit as one of the interrupts merged into the
EPH INT bit. Reading the COUNTER register after an EPH INT interrupt caused by a counter rollover, will acknowledge
the interrup t. CR ENABLE de faults low (disabled ).
TE ENABLE - Transmit Error Enable. When set it enables Transmit Error as one of the interrupts merged into the EPH
INT bit. An EPH INT interrupt caused by a transmi t ter error is acknowledged by setting TXEN A bit in the TCR regi ster to 1
or by clearing the TE ENABLE bit. TE ENABLE defaults low (disabled). Transmit Error is any condition that clears TXENA
with TX_SUC staying low as de scribed in the EPH SR regi ster.
Reserved 2-0: These reserve d bits must always be written to as zero(0).
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SMSC LAN91C110 Rev. B Page 27 Revision 1.0 (11-04-08)
DATASHEET
BANK2
OFFSET NAME TYPE SYMBOL
0 MMU COMMAND REGISTER WRITE ONLY
BUSY Bit Reada ble MMUCR
This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO control. The three
command bits dete rmine the co mmand i ssu ed as de scribed below :
HIGH
BYTE
LOW
BYTE COMMAND Reserved Reserved N2 N1 N0/BUSY
X Y Z
0
COMMAND SET:
xyz
000 0) NOOP - NO OPERATION
001 1) ALLOCATE MEMORY FOR TX - N2, N1, N0 defines the amount of memory requested as (value + 1) * 256
bytes. Namely N2, N1, N0 = 1 will request 2 * 256 = 512 bytes. A shift-based divide by 256 of the packet
length yields the appropriate value to be used as N2, N1, N0. Immediately generates a completion code at
the ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful completion. N2,
N1, N0 are ignored by the LAN91C110 but should be implemented in LAN91C110 software drivers for
LAN9000 compa tibili ty.
010 2) RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts, resets packet
FIFO pointers.
011 3) REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed processing of present
receive frame. This command removes the receive packet number from the RX FIFO and brings the next
receive frame (if any) to the RX area (output of RX FIFO).
100 4) REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by the packet
presently at the RX FIFO output. The MMU busy time after issuing REMOVE and RELEASE command
depends on the time when the busy bit is cleared. The time from issuing REMOVE and RELEASE command
on the last receive packet to the time when receive FIFO is empty depends on RX INT bit turning low. An
alternate approa ch can be checking the read RX FIFO reg iste r.
101 5) RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the PACKET NUMBER
REGISTER. Should not be used for frames pending transmission. Typically used to remove transmitted
frames, after reading their completion status. Can be used following 3) to release receive packet memory in
a more flexible way than 4).
110 6) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just
loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER.
111 7) RESET TX FIFOs - This command will reset both TX FIFOs: The TX FIFO holding the packet numbers
awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling
packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command
should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX
FIFOs does not release any memory .
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
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DATASHEET
Note 1: Bits N2,N1,N0 bits are ignored by the LAN91C110 but should be used for command 0 to preserve software
compatibility with the LAN91C92 and fu ture devices. They should be zero fo r all other command s.
Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register be fo re issuing the co mmand .
Note 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet
number has memory allo cate d to i t.
COMMAND SEQUENCING
A second allocate command (command 1) should not be issued until the present one has completed. Completion is
determined by reading the FAILED bit o f the allocation result regi ster or through the alloca tion inte rrup t.
A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The BUSY
bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be
changed until BUSY goe s low . After issuing command 4 , command 3 should not be issued until BUSY goes low .
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a
release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon
the trailing edge of comman d.
BANK 2
OFFSET NAME TYPE SYMBOL
2 PACKET NUMBER REGISTER READ/WRITE PNR
Reserved Reserved PACKET NUMBER AT TX AREA
0 0 0 0 0 0 0 0
PACKET NUMBER AT TX AREA - The value written into th is registe r de termines w hich pa cket number i s accessible
through the TX area . So me MMU co mmand s use the nu mbe r sto red in this regi ster a s the packet number parame te r. Thi s
register is cleared by a R ESET or a R ESET MMU Command .
OFFSET NAME TYPE SYMBOL
3 ALLOCA TION R ESU LT REG IST ER READ ON LY ARR
This register is upda ted upon an AL LOCATE MEMORY MMU command.
FAILED Reserved ALLOCATED PACKET NUMBER
1 0 0 0 0 0 0 0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the
pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT
in the Interrup t Sta tus Regi ster should be used because i t i s synchronized to the read operation . Sequ ence:
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
SMSC LAN91C110 Rev. B Page 29 Revision 1.0 (11-04-08)
DATASHEET
1. Allocate Command
2. Poll ALLOC_INT bit until set
3. Read Allocation Result Register
ALLOCATED PACKET NUMBER - Packet number asso cia ted w ith the last memo ry al loca tion request. The value is only
valid if the FAILED bit is clear.
Note: For software compatibility with future versions, the value read from the ARR after an allocation request is intended
to be w ritten into the PN R a s is, w ithou t ma sking higher bits (p rovided FAILED = 0).
BANK 2
OFFSET NAME TYPE SYMBOL
4 FIFO PORTS REGISTER READ ONLY FIFO
This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet
numbers to be proce ssed by the inte rrup t service routines are read fro m th is register.
HIGH
BYTE REMPTY 0 RX FIFO PACKET NUMBER
1 0 0 0 0 0 0 0
LOW
BYTE TEMP TY 0 TX FIF O PACKE T NUM BER
1 0 0 0 0 0 0 0
REMPTY - No receive packets queued in the RX FIFO. For poll ing purposes, use s the RCV_INT bit in the In terrup t Statu s
Register.
TOP OF RX FIFO PACKET NUMBER - Packet number presently at the out put of t he R X FIF O. On ly v ali d if R EMPT Y is
clear. The packet is removed from the RX FIFO using MMU Commands 3) or 4).
TEMPTY - No transmit packets in completion queue. For polling purposes, uses the TX_INT bit in the Interrupt Status
Register.
TX FIFO PA CK ET NU MBE R - Pack et numb er pr es entl y at the o utp ut of t he T X FIFO. O nly va li d if TE MPT Y is c lea r. Th e
packet is removed when a TX IN T acknowledge is issued .
Note: For software compatib ility with future version s , the value read from each FIFO regi ster is intended to be w ritten into
the PNR as is, w ithout masking highe r bi ts (pro vided TEMPTY and REMPTY = 0 respec tively).
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
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BANK 2
OFFSET NAME TYPE SYMBOL
6 POINTER REGISTER READ/WRITE
NOT EMPTY is a read
only bit
PTR
HIGH
BYTE RCV AUTO
INCR. READ Reserved NOT
EMPTY POIN TE R H IGH
0 0 0 0 0 0 0 0
LOW
BYTE POINTER LOW
0 0 0 0 0 0 0 0
POINTER REGISTER - The value of this register determines the address to be accessed within the transmit or receive
areas. It will auto-increment on accesses to the data register when AUTO INCR. is set. The increment is by one for every
byte access, by two for every word access, and by four for every double word access. When RCV is set the address
refers to the receive area and uses the output of RX FIFO as the packet number, when RCV is clear the address re fers to
the transmit a rea and uses the pa cke t nu mber at the Pa cket Nu mber Reg ister.
READ - Determines the type of access to follow. If the R EAD bit is high the operation intended i s a read. If the R EAD bit is
low the operation is a write. Loading a new pointer value, with the READ bit high, generates a pre-fetch into the Data
Register for read pu rpose s.
Readback of the pointer will indicate the value of the address last accessed by the CPU (rather than the last pre-fetched).
This allows any interrupt routine that uses the pointer, to save it and restore it without affecting the process being
interrupted. The Pointer Register should not be loaded until the Data Register FIFO is empty. The NOT EMPTY bit of this
register can be read to determine if the FIFO is empty. On reads, if IOCHRDY is not connected to the host, the Data Register
(ARDY) should no t be read before 370ns afte r the pointer w as loaded to a llow the Data Register FIFO to fill.
If the poin ter is loaded u sing 8 bit writes, the low byte should be loaded fi rst and the high by te last.
Reserved – Must be 0.
NOT EMPT Y - Wh en set indi cat es th at th e Writ e Dat a FIF O is not empt y yet . T he CPU can verif y tha t th e FIF O is em pt y
before loading a new pointe r value . Thi s is a read only bit.
Note: If AUTO INCR. is not set, the pointer must be loaded with a dword aligned value .
BANK 2
OFFSET NAME TYPE SYMBOL
8 THROUGH Bh DATA REGISTER READ/WRITE DATA
DATA HIGH
X X X X X X X X
DATA LOW
X X X X X X X X
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DATA REGISTER - Used to read o r w rite the data bu ffer by te/w ord pre sen tly add ressed by the poin ter reg ister.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C110 regardless of
whether the pointer address is even, odd or dword aligned. Data goes through the write FIFO into memory, and is pre-
fetched from me mory into the read FIFO. If byte accesses are used, the approp ria te (next) byte can be accessed through
the Data L ow or Dat a High r egist ers. T he or der to a nd from t he FIF O is pr eserv ed. B yte word access es can b e mixe d on
the fly in any orde r.
This register is mapped in to two conse cutive w ord locations. The DATA registe r is a ccessible a t any add ress in the 8
through Ah range, while the number of by tes being transfe rred is de te rmined by A1 and nBE0-nBE. The FIFOs are 12
bytes each.
BANK 2
OFFSET NAME TYPE SYMBOL
C INTERRUPT STATUS REGISTER READ ONLY IST
Reserved EPH INT
RX_OVRN
INT ALLOC
INT TX
EMPTY
INT
TX INT RCV IN T
0 0 0 0 0 1 0 0
OFFSET NAME TYPE SYMBOL
C INTERRUPT ACKNOWLEDGE
REGISTER WRITE ONLY ACK
Reserved RX_OVRN
INT TX
EMPTY
INT
TX INT
OFFSET NAME TYPE SYMBOL
D INTERRUPT MASK REGISTER READ/WRITE MSK
Reserved EPH INT
MASK
RX_OVRN
INT
MASK
ALLOC
INT
MASK
TX
EMPTY
INT
MASK
TX INT
MASK
RCV INT
MASK
0 0 0 0 0 0 0 0
This register can be read and w ritten as a w ord o r as tw o individual by tes.
The Interrup t Ma sk Register bi ts enable the appropriate bits when high and d isabl e them w hen low . A MASK bi t being se t
will cause a hardw are in terrup t.
Note: The Bit 7 mask must never be written high (1).
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
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Reserved – Must be 0.
EPH INT - Set w hen the Etherne t Pro tocol Handler section indi cates one ou t of va riou s possible special condi tions. This
bit merges exception type o f in terrup t sources, whose service time is no t cri tical to the execu tion speed of the low level
drivers. The exa ct natu re o f the in terrup t can be ob tained from the EPH Sta tus Register (EPHSR), and enabling of these
sources can be done via the Control Registe r. The possibl e sources are :
1. LINK - Link Test transition
2. CTR_ROL - Statistics counter roll over
3. TXENA cleared - A fa tal transmit error occurred forcing TXENA to be clea red . TX_ SUC w ill be low and the spe ci fic
reason will be re fle cted by the bits:
3.1) SQET - SQE Error
3.2) LOST CARR - Lost Carrier
3.3) LATCOL - Late Collision
3.4) 16COL - 16 collision s
Any of the a bove in te rrupt sources can b e masked by the appropria te EN ABLE bits in the Con trol Regi ster. 1 ) LE
ENABLE (Link Error Enable), 2) CR ENABLE (Counte r Ro ll Over), 3) TE ENABLE (Transmit Error Enable)
EPH INT w ill only be cleared by the follow ing method s:
1. Clearing the L E EN ABL E bit in the Control Regi ster if an EPH inte rrup t i s cau sed by a L INK_OK transi tion.
2. Reading th e Coun te r Registe r i f an EPH in terrup t is cause d by sta tistics coun te r roll o ver.
3. Setting TXEN A bit high i f an EPH in te rrupt is caused by any of the fa tal tran smit er ror listed above (3.1 to 3.5).
RX_OVRN INT - Set w hen 1) the recei ver aborts du e to an ov errun due to a failed memo ry a llocation, 2 ) the receiver
aborts due to a pa cke t length of greater than 2K by tes, o r 3 ) the recei ver aborts du e to the RCV D ISCRD bit in the RC V
register set. The RX_OVRN INT bit latches the condi tion for the pu rpose o f being pol led or gene ra ting an in terrupt, and
will only be cleared by writing the acknowledge register with the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement of the FAILED bit
in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU when the next allocation request
is processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to gene rate a single in terrupt a t the end o f a sequen ce o f
packets enqueued fo r transmission. This bit latch es the empty condition, and the bi t will stay se t until it is spe cifica lly
cleared by writing the acknowledge regi ster with the TX EMPTY INT bit set. If a real time reading of the FIFO empty is
desired, the bit should be first clea red and then read.
The TX_EMPTY MASK bit should only be set after the following steps:
1. A packet i s enqueued fo r transmission
2. The previou s empty condi tion is cleared (a cknowledged)
TX IN T - Se t w hen at least one packe t tran smis sion wa s com ple ted or any o f the below transmit fatal erro rs o ccur s:
1. SQET - SQE Error
2. LOST CARR - Lost Carrier
3. LATCOL - Late Collision
4. 16COL - 16 collisions
The first packet number to be serviced can be read from the FIFO PORTS register. The TX INT bit is always the logic
complement of the TEMPTY bit in the FIFO PORTS register. After servicing a packet number, its TX INT interrupt is
removed by writing the In terrupt Acknow ledge Register w ith the TX INT bit se t.
RCV INT - Set when a receive interrupt is generated. The first packet number to be servi ced can be read from the FIFO
PORTS register. The RC V IN T bit is alw ay s the logi c comp lement of the REMPTY bit in the FIFO PORTS register.
Receive Inte rrupt is clea red when RX FIFO is empty.
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Figure 5.2 – Interrupt Structure
TX FIFO EMPTY
DQS
nQ
IntAck1
DQS
nQ
IntAck2
DQS
nQ
IntAck4 RX_OVRN
nWRACK
TX Complete
Fatal TX Error
SQET
LOST CARR
LATCOL
16COL
Interrupt Status Register
76543210
nRDIST
Interrupt Mask Register
76543210
OE nOE
Edge Detector on Link Err
LEMASK
CTR-ROL
CRMASK
TEMASK
TXENA
TX_SVC
EPHSR INTERRUPTS
MERGED INTO EPH INT
ALLOCATION
FAILED
RX_OVRN INT
EPH INT
ALLOC INT
TX EMPTY INT
TX INT
RCV INT
INT
RCV FIFO
NOT EMPTY
D[7:0] D[15:8]
DATA BUS
D[15:0]
MAIN INTERRUPTS
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BANK3
OFFSET NAME TYPE SYMBOL
0 THROUGH 7 MULTICAST TABLE READ/WRITE MT
LOW
BYTE MULTICAST T ABLE 0
0 0 0 0 0 0 0 0
HIGH
BYTE MULTICAST T ABLE 1
0 0 0 0 0 0 0 0
LOW
BYTE MULTICAST T ABLE 2
0 0 0 0 0 0 0 0
HIGH
BYTE MULTICAST T ABLE 3
0 0 0 0 0 0 0 0
LOW
BYTE MULTICAST T ABLE 4
0 0 0 0 0 0 0 0
HIGH
BYTE MULTICAST T ABLE 5
0 0 0 0 0 0 0 0
LOW
BYTE MULTICAST T ABLE 6
0 0 0 0 0 0 0 0
HIGH
BYTE MULTICAST T ABLE 7
0 0 0 0 0 0 0 0
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most significant bits of
the CRC of the destination addresses. The three msb's determine the register to be used (MT0-MT7), while the other
three determine the bit within the register.
If the appropriate bit in the table is set, the packet is received .
If the ALMUL bit in the RCR regi ster is set, all mul ticast addresse s are received regard less of the multicast table value s.
Hashing is only a partial group addressing filtering scheme, but being the hash value available as part of the receive
status word, th e rec eive ro utin e can r educ e the sea rch tim e signi fica ntly. W ith t he pro per memo ry stru cture , the se arch is
limited to co mpa ring only the multicast addresses tha t ha ve the a ctu al hash value in question .
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
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BANK 3
OFFSET NAME TYPE SYMBOL
8 MANAGEMENT INTERFACE READ/WRITE MGMT
HIGH
BYTE FLTST MSK_
CRS100
0 0 1 1 0 0 1 1
LOW
BYTE MDOE MCLK MDI MDO
0 0 1 1 0 0 MDI Pin 0
FLTST - Facilitates the inclusion of packet forwarding information on the receive packet memory structure. When 0, RD0-
RD7 is always driven. When 1, RD0-RD7 is floated during RECEIVE FRAME STATUS WORD writes (RA2-RA16=0,
RCVDMA=1, nRWE0-nRWE3=0 ).
MSK_CRS100 - Disables CRS100 de tection du ring transmit in hal f duplex mode (SWFDUP=0 ).
MDO - MII Management outpu t. The value o f this bit dri ves the MDO pin.
MDI - MII Managemen t inpu t. The value o f the MD I p in is readable u sing thi s bit.
MDCLK - MII Management clock. The value o f this bi t drives the MDCLK pin.
MDOE - MII Managemen t ou tpu t enable . When high pin MD O is d riven , w hen low pin MDO is tri -stated.
The purpose o f thi s interfa ce, along w ith the corresponding pins is to i mplemen t MII PH Y man agemen t in so ftware .
BANK 3
OFFSET NAME TYPE SYMBOL
A REVISION REGISTER READ ONLY REV
HIGH
BYTE
0 0 1 1 0 0 1 1
LOW
BYTE CHIP REV
1 0 0 1 0 0 0 0
CHIP - Chip ID . Can be u sed by so ftware d rivers to iden ti fy the device used .
REV - Revi sion ID. Inc remented for ea ch revi sion of a give n de vice.
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CHIP ID VALUE DEVICE
3 LAN91C90/LAN91C92
4 LAN91C94
5 LAN91C95
4* LAN91C96
7 LAN91C100
8 LAN91C100FD
9 LAN91C110
*Note: Shares the chip ID with the LAN91C94. Distinction is made by the revision ID. Revision ID of 6 or higher
represents the LAN91C96.
OFFSET NAME TYPE SYMBOL
C RCV REGISTER READ/WRITE RCV
HIGH
BYTE
0 0 0 0 0 0 0 0
LOW
BYTE RCV
DISCRD Reserved Reserved MBO MBO MBO MBO MBO
0 0 0 1 1 1 1 1
RCV DISCRD - Set to discard a packet being received. Will discard packets only in the process of being received. When
set prior to the end of receive packet, bit 4 (RXOVRN) of the interrupt status register will be set to indicate that the packet
was discarded. Otherwise, the packet will be received normally and bit 0 set (RCVINT) in the interrupt status register.
RCV DISCRD is self clearing.
MBO – Must be 1.
BANK7
OFFSET NAME TYPE SYMBOL
0 THROUGH 7 EXTERNAL REGISTERS
nCSOUT is driven low by the LAN91C110 w hen a valid access to the EXTERNAL REGISTER range occurs.
HIGH
BYTE EX TERNAL R /W RE GISTE R
LOW
BYTE EX TERNAL R /W RE GISTE R
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CYCLE nCSOUT LA N91C110 DATA BUS
AEN=0
A3=0
A4-15 matches I/O BASE
BANK SELEC T = 7
Driven low . Transparently latched on
nADS rising edge. Ignored on write s.
Tri-stated o n read s.
BANK SELECT = 4,5,6 High Ignore cycle.
Otherwise High Norma l LAN91C110 cycle .
5.2 Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX pac ket
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed u ntil a
transmit interrupt is generated.
5 The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duple x mode
only) state.
6 a) Upon transmit completion the first word in
memory is written with the status word. The
packet number is moved from the TX FI F O into
the TX completion FIFO. Interrupt is generated
by the TX completion FIFO being not empty.
b) If a TX failure occurs on any packets, TX INT
is generated and TXENA is cleared,
transmission sequence stops. T he packet
number of the failure packet is presented at the
TX FIFO PORTS Register.
7 a) SERVICE INTERRUPT - Read Interrupt Status
Register. If it is a transmit interrupt, read the TX
FIFO Packet Number from the FIFO Ports
Register. Write the packet number into the Packet
Number Register. The corresponding status word
is now readable from memory. If status word
shows successful transmission, issue RELEASE
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S/W DRIVER MAC SIDE
packet number command to free up the mem ory
used by this packet. Remove packet number
from completion FIFO by writing TX INT
Acknowledge Register.
b) Option 1) Release the packet.
Option 2) Check the transmit status in the EPH
STATUS Regis ter, write the packet number of
the current packet to the Packet Number
Register, re-enable TXENA, then go to step 4 to
start the TX sequence again.
5.3 Typical Flow of Events for Transmit (Auto Release = 1)
S/W DRIVER MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N
BYTES - the MMU attempts to allocate N bytes
of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION
CODE - Poll until the ALLOC INT bit is set or
enable its mask bit and wait for the interrupt.
The TX packet number is now at the Allocation
Result Register.
3 LOAD TRANSMIT DATA - Copy the TX pac ket
number into the Packet Number Register. Write
the Pointer Register, then use a block move
operation from the upper layer transmit queue
into the Data Register.
4 ISSUE "ENQUEUE PACKET NUMBER TO TX
FIFO" - This command writes the number
present in the Packet Number Register into the
TX FIFO. The transmission is now enqueued.
No further CPU intervention is needed u ntil a
transmit interrupt is generated.
5 The enqueued packet will be transferred to the
MAC block as a function of TXENA (nTCR) bit
and of the deferral process (1/2 duple x mode
only) state.
6 Transmit pages are released by transmit
completion.
7 a) The MAC generates a TXEMPTY interrupt
upon a completion of a sequence of en queued
packets.
b) If a TX failure occurs on any packets, TX INT
is generated and TXENA is cleared, transmi ssion
sequence stops. The packet number of the
failure packet is presented at the TX FIFO
PORTS Register.
8 a) SERVICE INTERRUPT – Read Interrupt
Status Register, exit the interrupt service
routine.
b) Option 1) Release the packet.
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S/W DRIVER MAC SIDE
Option 2) Check the transmit status in the EPH
STATUS Regis ter, write the packet number of
the current packet to the Packet Number
Register, re-enable TXENA, then go to step 4 to
start the TX sequence again.
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5.4 Typical Flow of Events for Receive
S/W DRIVER MAC SIDE
1 ENABLE RECEPTION - By setting the RXEN
bit.
2 A packet is received with matching address.
Memory is requested from MMU. A packet
number is assigned to it. Additional memory is
requested if more pages are neede d.
3 The internal DMA logic generates sequential
addresses and writes the receive words into
memory. The MMU does the sequential to
physical address translation. If overrun, packet
is dropped and memory is released.
4 When the end of packet is detected, the status
word is placed at the beginning of the receive
packet in memory. Byte count is placed at the
second word. If the CRC checks correctly the
packet number is written into the RX FIFO. The
RX FIFO, being not empty, causes RCV INT
(interrupt) to be set. If CRC is incorrect the
packet memory is released and no interrupt will
occur.
5 SERVICE INTERRUPT - Read the Interrupt
Status Register and determine if RCV INT is set.
The next receive packet is at receive area. (Its
packet number can be read from the FI FO Ports
Register). The software driver can process the
packet by accessing the RX a rea, and c an move
it out to system memory if desired. When
processing is complete the CPU issues the
REMOVE AND RELEASE FROM TOP OF RX
command to have the MMU free up the used
memory and packet number.
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DATASHEET
Figure 5.3 – Interrupt Service Routine
ISR
Save Bank Select & Address
Ptr Registers
M ask SMC91C100FD
Interrupts
Read Interrupt Register
Call TX INTR or TXEMPTY
INTR TX INT R?
Get Next TX
RX INTR?
Yes
No
No Yes
Ca ll RX INTR
ALLOC INTR?
No Yes Write Allocated Pkt # into
Packet Number Reg.
W rite Ad Ptr Reg. & Copy Data
& Source Address
Enqueue Pack et
Packet
Available for
Transmission?
Yes No
Call ALLOCATE
EPH INTR? NoYes
Call EPH INTR
Set "Ready for Packet" Flag
Return Buffers to Upper Layer
Disable Allocation Interrupt
Mask
R estore Address Pointer &
Bank Select Registers
Unmask SMC91C100FD
Interrupts
Exit ISR
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RX INT R
Write Ad. Ptr. Reg. & Read
Word 0 from RAM
Destination
Multicast?
Read Words 2, 3, 4 from RAM
for Address Filtering
Address
Filtering Pass?
Status Word
OK?
Do Receive Lookahead
Get Copy Specs from Upper
Yes No
Yes
No
No Yes
Layer
Okay to
Copy?
Copy Data Pe r Upper Layer
Specs
Iss ue "Remove and Release"
Command
Return to ISR
No Yes
Figure 5.4 - RX INTR
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Write Into Packet Number
Register
TX Status
OK?
TX INTR
Save Pkt Number Regist er
Read TXDONE Pkt # from
FIFO Ports Reg.
Immediately Issue "Release"
Command
Acknowledge TXINTR
Read TX INT Again
Return to ISR
NoYes
Read Status Word from RAM
Update Statistics
Re-Enable TXENA
Update Variables
TX INT = 0?
Restore Packet Number
Yes
No
Write Address Pointer Register
Figure 5.5 - TX INTR
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TXEM PTY INTR
Write Acknow ledge Reg. with
TXEM P T Y Bit Set
Read TXEMPTY & TX INTR
Acknowledge TXINT R
Re-Enable TXEN A
R e tu rn to IS R
Issue "Release" Comm an d
Res tore Packet N umber
TXEM PT Y = 0
&
TXINT = 0
(Wa iting for Completion)
TXEMPT Y = X
&
TXIN T = 1
(Transm iss ion Failed)
TXEMPTY = 1
&
TXIN T = 0
(Every thing went through
successfully)
Read Pk t. # Register & Save
Wr it e Ad dress Point er
Register
Read Status Word from RA M
U p d a te S ta tis tic s
Update Variables
Figure 5.6 - TXEMPTY INTR (Assumes auto release option selected)
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Figure 5.7 - Drive Send and Allocate Rou tines
ALLOCATE
Issue "Allocat e Memo ry"
Command to MMU
Read Interrupt Status Register
Enqueue Packet
Set "Ready for Pac ket" Flag
Return
Copy Remai ning TX Data
Packet into RAM
R eturn Buffers to Upper La yer
Write Allocated Packet into
P ack et # Register
W rite Address Pointer Register
Copy Part of TX Data Packet
int o RAM
W rite Source Address into
Proper Location
Store Data Buffer Pointer
Clear "Ready for Packet" Flag
Enable Allocation Interrupt
Allocation
Passed?
Yes No
DRIVER SEND
Choose Bank Select
Register 2
Call ALLOCATE
Exit Driver Send
Read Allocation Result
Register
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DATASHEET
5.5 Memory Partitioning
Unlike other controllers, the LAN91C110 does not require a fixed memory partitioning between transmit
and receive resources. The MMU allocates and de-allocates memory upon different events. An
additional mechanism allows the CPU to prevent the receive process from starving the transmit memory
allocation.
Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the
MAC for receive. The CPU can control the number of bytes it requests for transmit but it cannot
determine the number of bytes the receive process is going to demand. Furthermore, the receive pr ocess
requests will be dependent on network traffic, in particular on the arrival of broadcast and multicast
packets that might not be for the node, and that are not subject to upper layer software flow control.
In order to prevent unwanted traffic from using too much memory, the CPU can program a "memory
reserved for transmit" parameter. If the free memory fa lls b elo w the "memor y res erved for transmit" value,
MMU requests from the MAC block will fail and the packets will overrun and be ignored. Whenever
enough memory is released, packets can be received again. If the reserved value is too large, the node
might lose data which is an abnorm al condition. If the value is kept at zero, memor y allocation is handle d
on first-come first-served basis for the entire memory capacity.
Note that with the memor y management bu ilt into th e LAN9 1C110, the CP U can dynamic ally program th is
parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more
memory to be allocated for receive (by reducing the v alue of the reserved memory). Whenev er the driver
needs to burst transmissions it can reduce the receive memory allocation. The driver program the
parameter as a function of the follo wing variables:
1. Free memory (read only register)
2. Memor y size (r ead only register)
The reserved memory value can be changed on the fly. If the MEMORY RESERVED FOR TX value is
increased above the FREE MEMORY, receive packets in progress are still received, but no new packets
are accepted until the FREE MEMORY increases above the MEMORY RESERVED value.
5.6 Interrupt Generation
The interrupt strategy for the transmit and receive processes is such that it does not represent the
bottleneck in the transmit and receive queue management bet ween the soft ware driver and the control ler.
For that purpose there is no register reading necessary before the next element in the queue (namely
transmit or receive packet) can be handled b y the controller. The transmit and receive r esults are placed
in memory.
The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and
receive interrupts are en abled. This allows the interr upt service routine to process many receiv e packets
without exiting, or one at a time if the ISR just returns after processing and removing one.
There are two types of transmit interrupt strategies:
1. One interrupt p er packet.
2. One interrupt per sequence of packets.
The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used.
TX INT bit - Set whenever the TX completion FIFO is not empty.
TX EMPTY INT bit - Set whenever the TX FIFO is empty.
AUTO RELEASE - When set, successful transmit packets are not written into comp letion FIFO, and their
memory is released automatically.
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1. One interrupt per packet: enable TX INT, set AUTO RELEASE=0. T he software driver can find th e
completion result in memory and process the interrupt one packet at a time. Depending on the
completion code the driver will take different actions. Note that the transmit process is working in
parallel and other transmissions might be taking place. The LAN91C110 is virtually queuing the
packet numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by
reading the TX FIFO PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the
driver to keep a list of packet numbers being transmitted. The numbers are queued by the LAN91C110
and provided back to the CPU as their transmission completes.
2. One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO
RELEASE=1. TX EMPTY INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has
stopped and therefore the FIF O will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-allocation. Note that
when AUTO RELEASE=1 the CPU is not provided with the packet numbers that completed successfully.
Note: The pointer register is share d by any process acc essing the LAN9 1C110 memor y. In order to all o w
processes to be interruptable, the interrupting process is responsible for reading the pointer value before
modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1. Transmit loading (sometimes interrupt driven)
2. Receiv e unloading (interrupt driven)
3. Transmit Status reading (interrupt driven).
1) and 3) also share the usag e of the Packet Number R egist er. Therefore savin g and restoring the PNR i s
also required from interrupt service routines.
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
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DATASHEET
TX
FIFO
TX COMPLETION
FIFO
RX
FIFO
CSMA/CD
LOGICAL
ADDRESSPACKET #
MMU
PHYSICAL ADDRESS
RAM
CPU ADDRESS CSMA ADDRESS
RX PACKET
NUMBER
RX FIFO
PACKET NUMBER
PACKET NUMBER
REGISTER
PACK # OUT
M.S. BIT ONLY
'EMPTY'
'NOT E M PTY'
TX DONE
PACKET NUMBER
'NOT EMPTY'
INTERRUPT
STATUS REGISTER
RCV
INT
TX EMPTY
INT
TX
INT
ALLOC
INT
TWO
OPTIONS
Figure 5.8 – Interru pt Generation for Transmit, Receive, MMU
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DATASHEET
Chapter 6 Operational Description
6.1 Maximum Guaranteed Ratings*
Operating Temperature Range ................................................................................................................ 0 EC to +70EC
Storage Temperature Range .............................................................................................................-55EC°to + 150EC
Lead Temperature Range .........................................................................................Refer to JEDEC Spec. J-STD-020
Positive Voltage on any pin, with respect to Ground ......................................................................................VCC + 0.3V
Negative Voltage on any pin, with respect to Ground ............................................................................................-0.3V
Maximum VCC ........................................................................................................................................................... +7V
*Stresses above those listed above could cause permanent damage to the device. This is a stress rating only and
functional operation of the device at any other condition above those indicated in the operation sections of this
specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or dev ice failure can result. Some power supplies exhibit volt age spikes on their
outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on
the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
6.2 DC Electrical Characteristics
(TA = 0EC - 70EC, VCC = +5.0 V ± 10%)
PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I Type Input Buffer
Low Input Level
High Input Level
VILI
VIHI
2.0
0.8
V
V
TTL Levels
IS Type Input Buffer
Low Input Level
High Input Level
Schmitt Trigger Hysteresis
VILIS
VIHIS
VHYS
2.2
250
0.8
V
V
mV
Schmitt Trigger
Schmitt Trigger
ICLK Input Buffer
Low Input Level
High Input Level
VILCK
VIHCK
3.0
0.4
V
V
Input Leakage
(All I and IS buffers except
pins with pullups/pulldowns)
Low Input Leakage
High Input Leakage
IIL
IIH
-10
-10
+10
+10
µA
µA
VIN = 0
VIN = VCC
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DATASHEET
PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
O4 Type Buffer
Low Output Level
High Output Level
Output Leakage
VOL
VOH
IOL
2.4
-10
0.4
+10
V
V
µA
IOL = 4 mA
IOH = -2 mA
VIN = 0 to VCC
I/O4 Type Buffer
Low Output Level
High Output Level
Output Leakage
VOL
VOH
IOL
2.4
-10
0.4
+10
V
V
µA
IOL = 4 mA
IOH = -2 mA
VIN = 0 to VCC
I/O8 Type Buffer
Low Output Voltage
High Output Voltage
Output Leakage
VOL
VOH
IOL
2.4
-10
0.4
+10
V
V
µA
IOL = 8 mA
IOH = -4 mA
VIN = 0 to VCC
O12 Type Buffer
Low Output Level
High Output Level
Output Leakage
VOL
VOH
IOL
2.4
-10
0.5
+10
V
V
µA
IOL = 12 mA
IOH = -6 mA
VIN = 0 to VCC
OD16 Type Buffer
Low Output Level
Output Leakage
VOL
IOL
-10
0.5
+10
V
µA
IOL = 16 mA
VIN = 0 to VCC
Supply Current Active
Supply Current Standby
ICC
ICSBY
60
8
95
mA
mA
All outputs open.
CAPACITANCE TA = 25EC; fc = 1MHz; VCC = 5V
LIMITS
PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION
Clock Input Capacitance CIN 20 pF
Input Capacitance CIN 10 pF
Output Capacitance COUT 20 pF
All pins except pin
under test tied to
AC ground
CAPACITIVE LOAD ON OUTPUTS
ARDY, D0-D15 240 pF
All other outputs 45 pF
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Chapter 7 Timing Diagrams
Figure 7.1 - Asynchronous Cycle - nADS=0
PARAMETER MIN TYP MAX UNITS
t1 A1-A15, AEN, nBE0-nBE1 Valid and nADS Low Setup to
nRD, nWR Active 25 ns
t2 A1-A15, AEN, nBE0-nBE1 Hold After nRD, nWR Inactive
(Assuming nADS Tied Low) 20 ns
t3 nRD Low to Valid Data 40 ns
t4 nRD High to Data Floating 30 ns
t5 Data Setup to nWR Inactive 30 ns
t5A Data Hold After nWR Inactive 5 ns
Figure 7.2 - Asynchronous Cycle - USING nADS
PARAMETER MIN TYP MAX UNITS
t1 A1-A15, AEN, nBE0-nBE1 Valid and nADS Low Setup to nRD,
nWR Active 25 ns
t3 nRD Low to Valid Data 40 ns
t4 nRD High to Data Floating 30 ns
t5 Data Setup to nWR Inactive 30 ns
t5A Data Hold After nWR Inactive 5 ns
t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising 10 ns
t9 A1-A15, AEN, nBE0-nBE1 Hold after nADS Rising 15 ns
t8 t9
t5
t3 t4
t1
t5A
A1-A15, AEN, nBE0-nBE1 valid
D0-D15 valid
ADDRESS
nADS
READ DATA
nRD, nWR
WRITE DATA
A1-A15, AEN, nBE0-nBE1 validADDRESS
t3 t4
nADS
READ DATA
t5 t5A
D0-D15 valid
WRITE DATA
t1
nRD, nWR t2
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Figure 7.3 – Address Latching for All Modes
PARAMETER MIN TYP MAX UNITS
t8 A1-A15, AEN, nBE0-nBE1 Setup to nADS Rising 10 ns
t9 A1-A15, AEN, nBE0-nBE1 Hold After nADS Rising 15 ns
t25 A4-A15, AEN to nLDEV Delay 20 ns
t8 t9
t25
A1-A15, AEN, nBE0-nBE1
nADS
ADDRESS
nLDEV
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Figure 7.4 - SRAM Interface
PARAMETER MIN TYP MAX UNITS
t34 Write – RA2-RA16 Setup to nRWE0-nRWE3 Falling 0 ns
t35 Write – RA2-RA16 Hold after nRWE0-nRWE3 Rising 0 ns
t36 Write – RD0-RD31 Setup to nRWE0-nRWE3 Rising 12 ns
t37 Write – RD0-RD31 Hold after nRWE0-nRWE3 Rising 0 ns
t39 Write – nRWE0-nRWE3 Pulse Width 15 ns
t54 Write – RA2-RA16 Valid to End of Write 12 ns
t38 Read – RA2-RA16 Valid to RD0-RD31 Valid 15 ns
t51 Read – RD0-RD31 Hold after RA2-RA16 Ch ange 3 ns
t52 Read – nROE enable to RD0-RD31 Valid 12 ns
t53 Read – nROE disable to RD0-RD31 Invalid 0 8 ns
t50 Read/Write – Cycle Time 25 ns
t53t52
t37t36
t39t39
t50
t35
t54t50
t34
t50 t51
t50
t38
RE AD CYCLE WRITE CYCL E
RA2-RA16
nRWE0-nRWE3
nROE
RD0-RD31
t52
t38
t51
t38
t50 t51
t38
t50
t51
t38
M UL TIP LE READ CYCLES
RA2-RA16
nRWE0-nRWE3
nROE
RD0-RD31
t53t52
t37t36
t39t39
t50 t51
t50
t38
t50
t35
t54t50
t34
RE AD CYCLEW RITE CYCLE
RA2-RA16
nRWE0-nRWE3
nROE
RD0-RD31
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DATASHEET
APPLICATION NOTE
The following is the list of potential SRAMs and suppliers for the LAN91C110 Rev B. These SRAMs meet all timing
requirements for LAN91C110 Rev B. But any other SRAM that meets the specification will also work wit h the
LAN91C110 Rev B.
Min ≥ 3ns Max≤15ns Min≤25ns Max≤12ns Max≤8ns Min≤12ns Min≤12ns Min≤15ns
Manufacturer Part # t51 Data
Hold after
Address
Change
t38
Address
Valid to
Data Valid
R/W
Cycle Output
Enable to
Output
Valid
nROE
Disable to
Output in
High Z
Address
Valid to
End of
Write
Data
Setup to
End of
Write
Write
Pulse
Width
ISSI IS61C3216-10 3 10 10 5 5 9 5 7
ISSI IS61C3216-12 3 12 12 5 6 10 6 8
ISSI IS61C3216-15 3 15 15 7 7 11 7 10
Alliance AS7C256-12 3 12 12 5 3 8 6 8
Alliance AS7C256-15 3 15 15 6 4 10 8 9
Winbond 24257AJ-10 3 10 10 5 5 9 6 9
Winbond 24257AJ-12 3 12 12 6 6 10 7 10
Cypress CY7C199-10VC 3 10 10 5 5 7 5 7
Cypress CY7C199-12VC 3 12 12 5 5 9 8 8
Cypress CY7C199-15VC 3 15 15 7 7 10 9 9
Cypress CY7C1021-10 3 10 10 5 5 7 5 7
Cypress CY7C1021-12 3 12 12 6 6 8 6 8
Cypress CY7C1021-15 3 15 15 7 7 10 8 10
IDT IDT71016S12 4 12 12 7 6 9 7 9
IDT IDT71016S15 4 15 15 8 6 10 8 10
IDT IDT71256SA12 3 12 12 6 6 9 6 8
IDT IDT71256SA15 3 15 15 7 6 10 7 10
SamSung K6E0808C1E-C10 3 10 10 5 5 8 5 8
SamSung K6E0808C1E-C12 3 12 12 6 6 9 6 9
SamSung K6E0808C1E-C15 3 15 15 7 7 10 7 10
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DATASHEET
t28
t28 t28
t27
t27
t29
t29
TX25
TXD0-TXD3
TXEN100
RXD0-RXD3
RX25
RX_DV
RX_ER
Figure 7.5 - MII Interface
PARAMETER MIN TYP MAX UNITS
t27 TXD0-T XD3, TXEN100 Delay from TX25 Rising 0 15 ns
t28 RXD0-RXD3, RX_DV, RX_ER Setup to R X 25 Rising 10 ns
t29 RXD0-RXD3, RX_DV, R X_E R Hold After RX25 Rising 10 ns
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Chapter 8 Package Outline
Figure 8.1 - 144 Pi n TQFP Package Outlines
Table 8.1 – 144 Pin TQFP Package Parameters
MIN NOMINAL MAX REMARK
A ~ 1.0 1.20 Overall Package Height
A1 0.05 0.10 0.15 Standoff
A2 0.95 1.00 1.05 Body Thickness
D 21.80 22.00 22.20 X Span
D/2 10.90 11.00 11.10 1/2 X Span Measure from Centerline
D1 19.80 20.00 20.20 X body Size
E 21.80 22.00 22.20 Y Span
E/2 10.90 11.00 11.10 1/2 Y Span Measure from Centerline
E1 19.80 20.00 20.20 Y body Size
H 0.09 ~ 0.20 Lead Frame Thickness
L 0.45 0.60 0.75 Lead Foot Length from Centerline
L1 ~ 1.00 ~ Lead Length
e 0.50 Basic Lead Pitch
0o 3.5o 7
o Lead Foot Angle
W 0.13 0.18 0.23 Lead Width
R1 0.08 ~ ~ Lead Shoulder Radius
R2 0.08 ~ 0.20 Lead Foot Radius
ccc ~ ~ 0.0762 Max Coplanarity (Assemblers)
ccc ~ ~ 0.08 Max Coplanarity (Test House)
Note 1: Controlling Unit: millimeter
Note 2: Tolerance on the position of the leads is ± 0.04 mm maximum.
Note 3: Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion Is 0.25
mm.
Note 4: Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane is 0.78-1.08 mm.
Note 5: D etails of pin 1 identi fier are optional but must be located w ithin the zone indicated.
