1
SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
BLOCK DIAGRAM
■ Max.togglefrequencyof700MHz
■ ClocktoQmax.of1200ps
■ IEEmin.of–98mA
■ Industrystandard100KECLlevels
■ Extendedsupplyvoltageoption:
VEE=–4.2Vto–5.5V
■ Voltageandtemperaturecompensationforimproved
noiseimmunity
■ Internal75kΩinputpull-downresistors
■ 50%fasterthanFairchild300K
■ Betterthan20%lowerpowerthanFairchild
■ FunctionandpinoutcompatiblewithFairchildF100K
■ Availablein28-pinPLCCpackage
FEATURES
HEXDFLIP-FLOP SY100S351
DESCRIPTION
The SY100S351 offers six D-type, edge-triggered, master/
slave ip-ops with differential outputs, and is designed for
use in high-performance ECL systems. The ip-ops are
controlled by the signal from the logical OR operation on a
pair of common clock signals (CPa, CPb). Data enters the
master when both CPa and CPb are LOW and transfers to the
slave when either CPa or CPb (or both) go to a logic HIGH.
The Master Reset (MR) input overrides all other inputs and
takes the Q outputs to a logic LOW. The inputs on this device
have 75kΩ pull-down resistors.
Rev.: I Amendment: /0
Issue Date: June 2010
Pin Function
D0 — D5 Data Inputs
CPa, CPb Common Clock Inputs
MR Asynchronous Master Reset Input
Q0 — Q5 Data Outputs
Q0 — Q5 Complementary Data Outputs
VEES VEE Substrate
VCCA VCCO for ECL Outputs
PINNAMES
2
SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
PACKAGE/ORDERINGINFORMATION
28-PinPLCC(J28-1)
OrderingInformation
Package Operating Package Lead
PartNumber Type Range Marking Finish
SY100S351JC J28-1 Commercial SY100S351JC Sn-Pb
SY100S351JCTR(1) J28-1 Commercial SY100S351JC Sn-Pb
SY100S351JZ(2) J28-1 Commercial SY100S351JZ with Matte-Sn
Pb-Free bar-line indicator
SY100S351JZTR(1, 2) J28-1 Commercial SY100S351JZ with Matte-Sn
Pb-Free bar-line indicator
Notes:
1. Tape and Reel.
2. Pb-Free package is recommended for new designs.
TRUTHTABLES
AsynchronousOperation(1)
Inputs Outputs
Dn CPa CPb MR Qn(t+1)
X X X H L
NOTE:
1. H = High Voltage Level
L = Low Voltage Level
X = Don't Care
t = Time before CP Positive Transition
t+1 = Time after CP Positive Transition
u = LOW-to-HIGH Transition
SynchronousOperation(1)
Inputs Outputs
Dn CPa CPb MR Qn(t+1)
L u L L L
H u L L H
L L u L L
H L u L H
X H u L Qn(t)
X u H L Qn(t)
X L L L Qn(t)
SY100S351JY(1) J28-1 Industrial SY100S351JY with
Pb-Free bar-line indicator
Matte-Sn
SY100S351JYTR(1,2) J28-1 Industrial SY100S351JY with
Pb-Free bar-line indicator
Matte-Sn
3
SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
DCELECTRICALCHARACTERISTICS
VEE = –4.2V to –5.5V unless otherwise specied; VCC = VCCA = GND
Symbol Parameter Min. Typ. Max. Unit Condition
IIH Input HIGH Current µA VIN = VIH (Max.)
MR 270
D0 – D5 200
CPa, CPb 300
IEE Power Supply Current –98 –71 –49 mA Inputs Open
ACELECTRICALCHARACTERISTICS
TA=0°CTA=+25°CTA=+85°C
Symbol Parameter Min. Max. Min. Max. Min.Max.UnitCondition
fMAX Toggle Frequency 700 700 700
tPLH Propagation Delay 1200 1200 1200
tPHL CPa, CPb to Output
tPLH Propagation Delay 1200 1200 1200
tPHL MR to Output
tTLH Transition Time 300 900 300 900 300 900
tTHL 20% to 80%, 80% to 20%
tS Set-up Time ps
D0–D5 500 500 500
MR (Release Time) 1000 1000 1000
tH Hold Time, D0–D5 550 550 550
tPW (H) Pulse Width HIGH 1000 1000 1000
CPa, CPb, MR
VEE = –4.2V to –5.5V unless otherwise specied; VCC = VCCA = GND
MHz
ps
ps
ps
ps
ps
TA=-40°C
Min. Max.
700
1200
1200
300 900
500
1000
550
1000
4
SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
TIMINGDIAGRAMS
PropagationDelay(Clock)andTransitionTimes
NOTE:
VEE = –4.2V to –5.5V unless otherwise specied; VCC = VCCA = GND
PropagationDelay(Resets)
5
SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
TIMINGDIAGRAMS
DataSet-upandHoldTime
Notes:
1. VEE = –4.2V to –5.5V unless otherwise specied; VCC = VCCA = GND
2. tS is the minimum time before the transition of the clock that information
must be present at the data input.
3. tH is the minimum time after the transition of the clock that information
must remain unchanged at the data input.
6
SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
28-PINPLCC(J28-1)
MICREL,INC. 2180FORTUNEDRIVE SANJOSE,CA 95131 USA
t e l + 1 (408) 944-0800 f a x + 1 (408) 474-1000 w e b http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specications at any time without notication to the customer.
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