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SY100S351
Micrel, Inc.
M9999-060910
hbwhelp@micrel.com or (408) 955-1690
BLOCK DIAGRAM
■ Max.togglefrequencyof700MHz
■ ClocktoQmax.of1200ps
■ IEEmin.of–98mA
■ Industrystandard100KECLlevels
■ Extendedsupplyvoltageoption:
VEE=–4.2Vto–5.5V
■ Voltageandtemperaturecompensationforimproved
noiseimmunity
■ Internal75kΩinputpull-downresistors
■ 50%fasterthanFairchild300K
■ Betterthan20%lowerpowerthanFairchild
■ FunctionandpinoutcompatiblewithFairchildF100K
■ Availablein28-pinPLCCpackage
FEATURES
HEXDFLIP-FLOP SY100S351
DESCRIPTION
The SY100S351 offers six D-type, edge-triggered, master/
slave ip-ops with differential outputs, and is designed for
use in high-performance ECL systems. The ip-ops are
controlled by the signal from the logical OR operation on a
pair of common clock signals (CPa, CPb). Data enters the
master when both CPa and CPb are LOW and transfers to the
slave when either CPa or CPb (or both) go to a logic HIGH.
The Master Reset (MR) input overrides all other inputs and
takes the Q outputs to a logic LOW. The inputs on this device
have 75kΩ pull-down resistors.
Rev.: I Amendment: /0
Issue Date: June 2010
Pin Function
D0 — D5 Data Inputs
CPa, CPb Common Clock Inputs
MR Asynchronous Master Reset Input
Q0 — Q5 Data Outputs
Q0 — Q5 Complementary Data Outputs
VEES VEE Substrate
VCCA VCCO for ECL Outputs
PINNAMES