4 _(MARCOM)DC2515 DOCUMENT CONTROL MASTER PRODUCT SPECIFICATION 216635 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER ory Cxpilacr Fe nn at a eee te ee FEATURES @ Low power CMOS technology @ Two general-purpose SCC channels, four DMA channels; and Universal Bus interface Unit = Software compatible to the Zilog CMOS SCC = 4DMAchannels; twotransmit and two receive channels to and from the SCC @ 4 gigabyte address range per DMA channel Flyby DMA transfer mode Programmable DMA channel priorities = Independent DMA register set = AU)niversal Bus Interface Unit providing simple interface to most CPUs multiplexed or non-multiplexed bus; compatible with 680x0 and 8x86 CPUs @ 32-bit addresses multiplexed to 16-pin address/data lines 8-bit data supporting highfow byte swapping = 10 MHz timing @ 16 MHz timing planned 68-pin PLCC PRODUCT SPECIFICATION 216035 CMOS ISCC INTEGRATED SERIAL COMMUNICATIONS CONTROLLER Supports ail Zilog CMOS SCC features: & Two independent, 0 to 4.0 M bit/second, full-duplex channels, each with a separate crystal oscillator, baud rate generator, and digital phase-locked loop circuit for clock recovery. = = Multi-protocol operation under program control; programmable for NRZ, NRZI, or FM data encoding. Asynchronous mode with five to eight bits and one, one and one-half, or two stop bits per character; programmable clock factor; break detection and generation; parity, overrun, and framing error detection. = Synchronous mode with internal or external character synchronization on one or two synchronous characters and CRC generation and checking with CRC-16 or CRC-CCITT preset to either 1's or O's. SDLC/HDLC mode with comprehensive frame-level control, automatic zero insertion and deletion, |-field residue handling, abort generation and detection, CRC generation and checking, and SDLC Loop mode operation. Local Loopback and Auto Echo modes @ Supports T1 digital trunk Enhanced SDLC 10x19 Status FIFO for DMA support Fuil CMOS SCC register set GENERAL DESCRIPTION The Z16C35 ISCC is a CMOS superintegrated device with a flexible Bus Interface Unit (BIU) connecting a built- in Direct Memory Access (DMA) celt to the CMOS Serial Communications Control (SCC) cell. The ISCC is a dual-channel, multi-protocol data communi- cations peripheral which easily interfaces to CPU's with either multiplexed or non-multiplexed address and data buses. The advanced CMOS process offers lower powerconsumption, higher performance, and superior noise immunity. The programming flexibility of the internal reg- isters allow the ISCC to be configured for a wide variety of serial communications applications. The many on-chip features such as, streamlined bus interface, four channel DMA, baud rate generators, digital phase-locked loops, and crystal oscillators dramatically reduce the need for external logic. Additional features, including a 10x19 bit status FIFO, are added to support high speed SDLC transfers using on-chip DMA controllers. The ISCC can address up to 4 gigabytes per DMA channel by using the /UAS and /AS signats to strobe out 32-bit multiplexed addresses. The ISCC handles asynchronous formats, synchronous byte-oriented protocols such as IBM Bisync, and synchro- nous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device supports virtually any serial data transfer application (terminals, printers, diskette, tape drives, etc.). The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The ISCC also has facilities for modem controls in both channels. In applica- tions where these controls are not needed, the modem controls can be used for general-purpose I/O. {EI ANT Controt Signals AD15-AD0 AD15-AD8 IEO Control Signals AD7-ADO The standard Zilog interrupt daisy chain is supported for interrupt hierachy control. Internally, the SCC cell has higher interrupt priority than the DMA cell. The DMA cell consists of four DMA channels; one for transmit and one for receive to and from each SCC chan- nel, respectively. The cycle time for each DMA transfer is 400 ns for the 10 MHz version. There is no idle cycle between DMA transfers. The DMA cell adopts a simple fly-by mode DMA transfer, allowing easy programming of the DMA cell and yet providing a powerful and efficient DMA access. The cell does not support memory-to-memory transfer. Priorities between the four DMA channels are program- mabie to custom-fit user applications. Arbitration of Bus priority control signals between the ISCC DMA and other system DMA's should be handled outside the ISCC. The BIU has a universal interface to most system/CPU bus structures and timing. The first write to the [SCC after a hardware reset will confirm the bus interface type being implemented. ANT Channel A 1 Channel B i Request , | { 1 4 Channel DMA t /BUSACK /BUSREQ Figure 1. Block Diagram Bee aren ee men ey> 3. & ESe8 & 3 BEZIL8eseseee ssa Donny to 1% *BUSREQ ANT CJ [] PCLK SYNCA [] /SYNCB ATxca CI [J /RTxcB GND C] /_] GND Vee (I i} Vee ADO CJ [_] ADs ADt ISCC /] ADS Abe 216C35 } AD10 ADS CI [) ADI AD4 CC] [] AD12 ADS CJ [] ADI3 AD [J [] AD14 AD7 (J [7 ADI5S GND GN Vec CJ ] Vee ne [J] ne Too oy o ooo Figure 2. Pin Assignments PIN DESCRIPTION The following section describes the Z16C35 pin functions. Figures 1 and 2 detail the respective pin functions and pin assignments. Ail references to DMA are internal. /CTSA, /CTSB. Clear To Send(inputs, active Low). If these pins are programmed as Auto Enables, aLowon the inputs enables the respective transmitters. If not programmed as Auto Enables, they may be used as general-purpose inputs. Both inputs are Schmitt-trigger buffered to accom- modate slowrise-time inputs. The SCC cell detects pulses on these inputs and can interrupt the CPU on both logic level transitions. /DCDA, /OCDB. Data Carrier Detect (inputs, active Low). These pins function as receiver enables if they are pro- grammed for Auto Enables; otherwise they are used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slowrise time signals. The SCC cell detects pulses on these pins and can interrupt the CPU on both logic level transitions. /DTRA, /DTRB. Data Terminal Ready (outputs, active Low). These outputs follow the state programmed into the DTR bit. IEt. Interrupt Enable In (input, active High). El is used with EO to form an interrupt daisy chain when there is more than one interrupt driven device. A high {Et indicates that no other higher priority device has an interrupt under service or is requesting an interrupt. The SCC ceil has a higher interrupt priority than the DMA cell. IEO. interrupt Enable Out{output, active High). {EO is High only if IE is High and the CPU is not servicing the ISCC (SCC or DMA) interrupt, or the SCC is not requesting an interrupt (Interrupt Acknowledge cycie only). EO is con- nected to the next lower priority device's IEI input and thus inhibits interrupts from lower priority devices. Cae aP% DESCRIPTION (Continued) AN. Interrupt(output, active Low). This signal is activated when the SCC or DMA requests an interrupt. Note that /INT iS miled high and is not an open-drain output. MITACK. Interrupt Acknowledge (input, active Low). This 6 strobe which indicates that an interrupt acknowledge cyte is in progress. During this cycle, the SCC and DMA interupt daisy chain is resolved. The device is capable of setuning an interrupt vector that may be encoded with the we of interrupt pending during this acknowledge cycle wher RD or DS become high. INTACK may be pro- yanmed to accept a status acknowledge, a single pulse ackiowledge, or a double pulse acknowledge. This is progammed in the Bus Configuration Register (BCR). The douwle pulse acknowledge is compatible with 8x86 family mucoprocessors. PCIK. Clock (input). This is the master SCC and DMA @iom used to synchronize internal signals. PCLK is a TTL ipve signal. PCLK is not required to have any phase telaionship with the master system clock. RxfA, RxDB. Receive Data (inputs, active High). These fou signals receive serial data at standard TTL levels. RICA, /RTxCB. Receive/Transmit Clocks (inputs, active tow, These pins can be programmed to several modes of spention. In each channel, RTxC may supply the receive How, the transmit clock, the clock for the baud rate genzator, or the clock for the Digital Phase-Locked Loop. hee pins can also be programmed for use with the respective SYNC pins as a crystal oscillator. The receive soa may be 1, 16, 32, or 64 times the data rate in $yichronous modes. RTE, ARTSB. Request To Send (outputs, active Low). Wher the Request To Send (RTS) bit in Write Register 5 is 32t. he RTS signal goes Low. When the RTS bitis reset in fre 4synchronous mode and Auto Enable is on, the signal oes igh after the transmitter is empty. In Synchronous nod: or in Asynchronous mode with Auto Enable off, the 7S yin strictly follows the state of the RTS bit. Both pins an 1a used as general-purpose outputs. SYA, SYNCB. Synchronization (inputs or outputs, active Low). These pins can act either as inputs, outputs, & patof the crystal oscillator circuit. In the Asynchronous feceve mode (crystal oscillator option not selected), flesenins are inputs similar to CTS and DCD. In this mode, tansaions on these lines affect the state of the Synchro- nwusHunt status bits in Read Register 0 but have no other hincton. In External Synchronization mode with the crystal oscilla- tor not selected, these lines also act as inputs. tn this mode, SYNC must be driven Low to receive clock cycles after the last bit in the synchronous character is received. Character assembly begins on the rising edge of the receive clock immediately preceding the activation of SYNC. In the Internal Synchronization mode (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which synchronous condition is not latched. These outputs are active each time a synchroni- zation pattern is recognized (regardless of character boundaries). In SDLC mode, the pins act as outputs and are valid on receipt of a flag. TxDA, TxDB. Transmit Data (outputs, active high). These output signals transmit serial data at standard TTL levels. /TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or out- puts, active Low). These pins can be programmed in several different modes of operation. TRxC may supply the receive clock or the transmit clock in the input mode or supply the output of the Digital Phase-Locked Loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. ICE. Chip Enable (input, active Low). This signal selects the ISCC for a peripheral read or write operation. This signal is not used when the ISCC is bus master. AD15-AD0. Data bus (bidirectional, 3-state). These lines Carry data and commands to and from the ISCC. /RD. Read (bidirectional, active Low). When the ISCC is a Peripheral (i.e. bus slave), this signal indicates a read operation and when the ISCC is selected, enables the ISCC's bus drivers. As an input, /RD indicates that the CPU wants to read from the {SCC read registers. During the InterruptAcknowledge cycle, /RD gates the interrupt vector onto the bus if the ISCC is the highest priority device requesting an interrupt. When the ISCC is the bus master, this signal is used to read data. As an output, after the ISCC has taken control of the system buses, /RD indicates a DMA-controlled read from amemory or I/O port address. MWR. Write (bidirectional, active Low). When the ISCC is selected, this signal indicates a write operation. As an input, this indicates that the CPU wants to write contro! or command bytes to the ISCC write registers. As an output, after the SCC has taken control of the system buses /WR indicates a DMA-controlled write to a memory or I/O port address./DS. Data Strobe (bidirectional, active Low). A Low on this signal indicates that the AD15-ADO bus is used for data transfer. When the ISCC is notin control of the system bus and the external system is transferring information to or from the ISCC, /DS is a timing input used by the ISCC to move data to or from the ADO-AD15 bus. Data is written into the [SCC by the external system on the Low to High /DS transition. Data is read from the ISCC by the external system while /DS is Low. There are no timing requirements between /DS as an input and ISCC clock; this allows use of the ISCC with a system bus which does not have a bussed clock. During a DMA operation when the ISCC is in control of the system, DS is an output generated by the ISCC and used by the system to move data to or from the ADO-AD15 bus. When the ISCC has bus control, it writes to the external system by placing data on the AD15-ADO bus before the High-to-Low DS transition and holds the data stable until after the Low-to-High DS transition; while reading from the external system, the Low-to-High transition of DS inputs data from the AD15-ADO bus into the ISCC. RIM. Read/Write (bidirectional). Read polarity is High and write polarity is Low. When the ISCC is bus master, R//W indicates the data direction of the current bus transaction, andis stable from when AS is High unti! the bus transaction ends. When the ISCC is not in control of the system bus and the external system is transferring information to or from the ISCC, R//W is a status input used by the ISCC to determine if data is entering or leaving on the ADO-AD15 bus during /DS time. Insuch a case, Read (High) indicates that the system is requesting data from the SCC and Write (Low) indicates that the system is presenting data to the ISCC. The only timing requirements for R/MW as an input are defined relative to DS. When the !SCC is in control of the system bus, R//W is an output generated by the ISCC, with Read indicating that data is being requested from the addressed location or device, and Write indicating that data is being presented to the addressed location or device. IUAS. Upper Address Strobe (Output, active Low). This signal is used if the address is more than 16-bit. The upper address, A31-A16, can be latched externally by the rising edge of this signal. /UAS is active first before AS becomes active. This signal and AS are used by the DMA cell. IAS. Lower Address Strobe (Bidirectional, active Low). When the ISCC is bus master, this signal when an output, is used as a lower address strobe for AD15-ADO. [tis used in conjunction with UAS since the address is 32-bits. This signal and /UAS are used by the DMA cell when it is bus master. When ISCC is not bus master, this signal is used in the multiplexed bus modes to latch the address on the ADlines. The /AS signal is not used in the non-multiplexed bus modes and should be tied to Vcc in these cases. NWAIT/IRDY. Wait/Reaay (bidirectional, active Low). It may be programmed to function either as a Wait signal or Ready signal during the BCR write. When the BCR is written to Channel A (A1/A//B High during the BCR write), this signal functions as a WAIT and thus supports the READY function of 8X86 microprocessors family. When the BCR writes to Channel B (A1/A//B Low), this signal functions as a READY and supports the DTACK function of the 680X0 microprocessor family. This signal is an output when the ISCC in not bus master. In this case, the Wait/RDY signal indicates when the data is available during a read cycle; when the device is ready to receive data during a write cycle; and when a valid vector is available during an interrupt acknowledge cycle. When the ISCC is the bus master (the DMA cell has taken control of the bus), the /Wait//RDY signal functions as a WAIT or READY input. Slow memories and peripheral devices can assert WAIT to extend /DS during bus trans- fers. Similarly, memories and peripherals use READY toin- dicate that its output is valid or that it is ready to latch input data. /BUSACK. Bus Acknowledge (input, active Low). Signals the bus has been released to the DMA. If the /BUSACK is inactive before the DMA transfer is completed, the current DMA transfer is aborted. /BUSREQ. Bus Request (output, active Low). This signal is used by the DMA to obtain the bus from the CPU. AO/SCC/IDMA. DMA Channel/SCC SelecyDMA Select (bidirectional). When this pin is used as input, a high selects the SCC cell and a low selects the DMA cell. When this pin is used as output, the signal on this pin is used in conjunction with A1/A//B pin output to identify which DMA channelis active. This information can be used by the user to determine whether to issue a DMA abort command. AO/SCC//DMA and A1/A//B output encoding is shown below: A1/A//B A0/SCC//DMA DMA channel 1 1 RxA 1 0 TxA 0 1 RxB 0 0 TxB RP ait as +PIN DESCRIPTION (Continued) A1/A//B. DMA Channel/Channel A/Channel B (bidirec- tional). This signal, when used as input, selects the SCC channel in which the read and write operation occurs. Note that AO/SCC//DMA pin must be held high to select this feature. When this pin is used as an output, it is used in conjunction with the AQ/SCC//DMA pin output to identify which DMA channel is active. During a DMA peripheral access, the A1/A//B pin is ignored. /RESET. (input, active Low). This signal resets the device to a known state. The first write to the ISCC after a reset accesses the BCR to select additional bus options for the device. FUNCTIONAL DESCRIPTION The functional capabilities of the SCC are described in three blocks: the SCC cell, the DMA cell, and the Bus Interface Unit (BIU). Each of the blocks are described in- dependently in the following sections with the ISCC archi- tecture shown in Figure 3. Please refer to the ISCC Technical Manual for a detailed description of the func- tions outlined here. Baud Rete Generator DMA A Channel 0 i} Serial Data LN] channet A bt 1 chan Internal xis | Po tne soos DMA Channel t Channel A Frame | Wait Registers eae Registers Status FIFO Discrete --* |} Modem, DMA, TY conkat [A f or Other & AL Controls ADO-ADI5 9 av interna BUS Status Conta C1) * Oltecrete [-a- Modem, DMA, | \| || II -N contol [+ } or other . & Stas B fm J Controls interrupt ;_ Interrupt Ct 10X19 Control =" Controt Channa 2 Revlatere Frame Lines __ ps] Logic Staus ~ } Serial Oata FIFO Channel 8 [*" } Channel Clocks ae /Sync Channel 3 _ | Baud Rete Malt Generator KO + 5V GND PCLK 8 Figure 3. Block Diagram of ISCC Architecture SCC Cell Data Communications Capabilities. The ISCC provides two independent full-duplex programmable channels for use in any common asynchronous or syn- chronous data communications protocol. The |SCC is built from Zilogs industry standard SCC core and is compatible with designs using Zilogs SCC to receive and transmit data. 6tm Uled Bed OOS! py aunBig ONAS (1078111980) WOOD JOBIEUeEH Hq = ~<-__4 OxLY w~oK NWdd -4 ae ~~ ox WOOD WUSUBLL <} ~~ incino Ta ~ YOO|O eAjeOey ~<a} <__ indyno somseUueD Hea dino dd dd lw mda epoceq ~ , ue-| axy nse OHO [ Teyseup IZUN xn ou0 Oyo O10sS 49019 4078J0U8D ywsuB Duo (sug-8) veisiBey XNW font Awjeg OUD muse ods OHO | (sue-s) ouo esu) 0107 ONAS Avo 118-2 9 = | onas (sg-8) seisiBey | | sug sisted o18z 8 poouy XN usuBL oudkg eajeoey & deisiBey ONAS IZUN 7 DNAS rT i ' bee eee tL 4 (ONASIE) @POW 1UNH ONASY 91607 1003 seuno . : eneoey Nev ug i 40\8/6ey | yusuBl) I ung ' ulus | Neroz i: zs indino ; induy s0yB0UeH JSO,UNOD UMO>C 11G-91 40} BJOUCE) XAW XL ost ood wa 8 OL He 4 ee 7 4 t 1 t Jou meg ax. meg J018\Gey sasGey | | VT TTT 7 7 Osld srg wEsUCD WILL luwisu0D eWLL | Oe yuu, BUM ouks SUA ous ZIM eajeoey enjooey ousws4 61 X OL erkgiemoy ZbHM | | etqueddy CLM mc tt U Lt JNO OL SN Beg eUelY {f if wna | nie | jouueyd Wewnrs mame eee am Asynchronous Modes. Send and Receive can be accom- plished independently on each channel with five to eight bits per character, plus optional even or odd parity. The transmitters can supply one, one-and-a-half, or two stop bits per character and can provide a break output at any time. The receiver break-detection logic interrupts the CPU both at the start and at the end of a received break. Reception is protected from spikes by a transient spike- rejection mechanism that checks the signal one-half a bit time after a Low level is detected on the receive data input (RxDA or RxDB in Figure 1). If the Low does not persist (e.g., a transient), the character assembly process does not start. Framing errors and overrun errors are detected and buff- ered together with the partial character on which they occur. Vectored interrupts allow fast servicing or error conditions using dedicated routines. Furthermore, a built- in checking process avoids the interpretation of a framing error as a new start bit: a framing error results in the addition of one-half a bit time to the point at which the search for the next start bit begins. The ISCC does not require symmetric transmit and receive clock signals - a feature allowing use of the wide variety of. clock sources. The transmitter and receiver can handle data at a rate supplied to the receive and transmit clock inputs. In Asynchronous modes, the SYNC pin may be programmed as an input used for functions such as monitoring a ring indicator. Synchronous Modes. The ISCC supports both byte-ori- ented and _ bit-oriented synchronous communication. Synchronous byte-oriented protocols can be handled in several modes, allowing character synchronization with a 6-bit or 8-bit synchronous character (Monosync), and 12- bit synchronization pattern (Bisync), or with an external synchronous signal. Leading sync characters can be removed without interrupting the CPU. Five or 7-bit synchronous characters are detected with 8- or 16-bit patterns in the ISCC by overlapping the larger pattern across multiple incoming synchronous characters as shown in Figure 5. aH [_[sync] sync] [ sync | vata | vata | vata | vata | ee) 16 Figure 5. Detecting 5- or 7-Bit Synchronous Characters CRC checking for Synchronous byte oriented modes is delayed by one character time so that the CPU may disable CRC checking on specific characters. This per- mits the implementation of protocols such as IBM Bisync. Both CRC-16 (X' + X + X2 +1) and CCITT (X16 + X'2 4 x5 +1) error checking polynomials are supported. Either polynomial may be selected in all Synchronous modes. Users may preset the CRC generator and checker to all 1's or all O's. The ISCC also provides a feature that automati- cally transmits CRC data when no other data is available for transmission. This allows for high speed transmissions under DMA control, with no need for CPU intervention at the end of a message. When there is no data or CRC to send in Synchronous modes, the transmitter inserts 6-, 8-, or 16-bit synchronous characters, regardless of the programmed character length. The ISCC supports Synchronous bit-oriented protocols, such as SDLC and HDLC, by performing automatic flag sending, zero insertion, and CRC generation. A special command is used to abort a frame in transmission. At the end of a message, the ISCC automatically transmits the CRC and trailing flag when the transmitter underruns. The transmitter may also be programmed to send an idle line consisting of continuous flag characters or a steady mark- ing condition. If a transmit underrun occurs in the middle of a message, an external/status interrupt warns the CPU of this status change so thatan abort may be issued. The ISCC may also be programmed to send an abort itself in case of an underrun, relieving the CPU of this task. One to eight bits per character can be sent, allowing reception of a mes- sage with no prior information about the character struc- ture in the information field of a frame. The receiver automatically acquires synchronization on the leading flag of a frame in SDLC or HDLC and provides a synchronization signal on the SYNC pin (an interrupt can also be programmed). The receiver can be programmed to search for frames addressed by a single byte (or four bits within a byte) of a user-selected address or to a global broadcast address. In this mode, frames not matching either the user-selected or broadcast address are ig- nored. The number of address bytes can be extended under software control. For receiving data, an interrupt on the first received character, or an interrupt on every char- acter, or on special condition only (end-of-frame) can be selected. The receiver automatically deletes all O's in- serted by the transmitter during character assembly. CRC is also calculated and is automatically checked to validate frame transmission. At the end of transmission, the status of a received frame is available in the status registers. In SDLC mode, the ISCC must be programmed to use the SDLC CRC polynomial, but the generator and checker eeveemay be preset to all 1's or all O's. The CRC is inverted before transmission and the receiver checks against the bit pattern 0001110100001 111. NRZ, NRZI or FM coding may be used in any 1x mode. The parity options available in Asynchronous modes are avail- able in Synchronous modes. SDLC Loop Mode. The ISCC supports SDLC Loop mode in addition to normal SDLC. In an SDLC Loop, there is a primary controller station that manages the message traf- tic flow on the loop and any number of secondary stations. In SDLC Loop mode, the ISCC performs the functions of a secondary station while an ISCC operating in regular SDLC mode acts as a controller (Figure 6). Figure 6. An SDLC Loop Asecondary station in an SDLC Loop is always listening to the messages being sent around the loop and, in fact, passes these messages to the rest of the loop by retrans- mitting them with a one-bit-time delay. The secondary Station places its own message on the loop only at specific times. The controller signals that secondary stations can transmit messages by sending a special character, called an EOP (End Of Poll), around the loop. The EOP character is the bit pattern 11111110. Because of zero insertion during messages, this bit pattern is unique and easily recognized. When a secondary station has a message to transmit and recognizes an EOP on the line, it changes the last binary 1 of the EOP to a0 before transmission. This has the effect of turning the EOP into a flag sequence. The secondary station now places its message on the loop and terminates the message with an EOP. Any secondary stations further down the loop with messages to transmit appends their messages to the message of the first secondary station by the same process. Any secondary stations without mes- Sages to send merely echo the incoming message and are prohibited from placing messages on the loop (except upon recognizing an EOP.) SDLC Loop mode is a programmable option in the ISCC. NRZ, NRZI, and FM coding may all be used in SDLC Loop mode. SDLC FIFO. The ISCCs ability to receive high speed back-to-back SDLC frames is maximized by a 10-bit deep by 19-bit wide status FIFO. When enabled (through WR 15, bit D2), it provides the DMA the ability to continue to transfer data intomemory so that the CPU can examine the message later. For each SDLC frame, a 14-bit byte count and 5 status/error bits are stored. The byte count and status bits are accessed through Read Registers 6 and 7. Read Registers are only accessible when the SDLC FIFO is enabled. The 10x19 status FIFO is separate from the 3 byte receive data FIFO. Notes on the SDLC FIFO: When using the SDLC FIFO enhancment in channel B, it is necessary to enable the enhancmentin channel A. There is no special requirement to enable the enhancement in channet A only , or to use it in both channels. Designs using only one channet should, therefore, use channel A. When an SDLC frame is received with an abort condition, the byte counter in the FIFO enhancment is not reset. Therefore, after the abort is received, a dummy frame consisting of a flag should be sent by the transmitter. This resets the byte counter for the next frame. The aborted frame has a byte count which includes the byte count of the next dummy frame. Baud Rate Generator. Each channel in the ISCC contains a programmable baud rate generator. Each generator consists of two 8-bit time constant registers that form a 16- bit time constant, a 16-bit down counter, and a flip-flop on the output producing a square wave. On startup, the flip- flop on the output is setin a High state, the value in the time constant register is loaded into the counter, and the counter starts counting down. The output of the baud rate generator toggles upon reaching 0, the vaiue in the time constant register is loaded into the counter, and the process is repeated. The time constant may be changed at any time, but the new value does not take effect until the next load of the counter. The output of the baud rate generator may be used as either the transmit clock, the receive clock, or both. it can also drive the Digital Phase-Locked Loop (see next sec- tion). If the receive clock or transmit clock is not programmed to come from the TRxC pin, the output of the baud rate generator may be echoed out via the TRxC pin. EE NNT ES LT BNR WIN RT AAT RE ID SL RW! RENTON BT RATE TETBURY UENOThe following formula relates the time constant to the baud rate where PCLK or RTxC is the baud rate generator input frequency in Hertz. The clock mode is 1, 16, 32, or 64, as selected in Write Register 4, bits D6 and D7. Synchronous operation modes should select 1 and Asynchronous should select 16, 32 or 64. PCLK or RTxC Frequency Time Constant = __ - 2 2(Baud Rate)(Clock Mode) Digital Phase-Locked Loop. The ISCC contains a Digital Phase-Locked Loop (DPLL) to recover clock information from a data stream with NRZI or FM encoding. The DPLL is driven by a clock that is nominally 32 (NRZ!) or 16 (FM) times the data rate. The OPLL uses this clock, along with the data stream, to construct a clock for the data. This clock is then used as the ISCC receive clock, the transmit clock, or both. For NRZI encoding, the DPLL counts the 32x clock to create nominal bit times. As the 32x clock is counted, the DPLL is searching the incoming data stream for edges (either 1 to0, or Oto 1). Whenever an edge is detected, the DPLL makes a count adjustment (during the next counting cycle), producing a terminal count closer to the center of the bit cell. For FM encoding, the DPLL still counts from 0 to 31, but with a cycle corresponding to two bit times. When the DPLL is locked, the clock edges in the data stream should occur between counts 15 and 16 and between counts 31 and 0. The DPLL looks for edges only during a time centered on the 15 to 16 counting transition. The 32x clock for the DPLL can be programmed to come from either the RTxC input or the output of the baud rate generator. The DPLL output may be programmed to be echoed out of the {SCC via the TRxC pin (if this pin is not being used as an input). Data Encoding. The ISCC may be programmed to encode and decode the serial data in four different ways (Figure 7). in NRZ encoding, a 1 is represented by a High level and a Ois represented by a Lowlevel. In NRZi encoding, a 1 is represented by no change in level and a O is represented by a change in level. In FM1 (more properly, bi-phase mark), a transition occurs at the beginning of every bit cell. A 1is represented by an additional transition at the center of the bit cell and a O is represented by no additional transition at the center of the bit cell. in FMO (bi-phase space), a transition occurs at the beginning of every bit cell. AQ is represented by an additional transition at the center of the bit cell, and a 1 is represented by no additional transition at the center of the bit cell. In addition to these four methods, the {SCC can be used to decode Manchester (bi-phase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester encoding always produces a transition at the center of the bit cell. If the transition is 0 to 1, the bitis a0. If the transition is 1 to 0, the bitis a 1. Figure 7. Data Encoding Methods Auto Echo and Local Loopback. The ISCC is capable of automatically echoing everything it receives. This feature is useful mainly in Asynchronous modes, but works in Synchronous and SDLC modes as weil. In Auto Echo mode, TxDis RxD. Auto Echo mode can be used with NRZI or FM encoding with no additional delay because the data stream is not decoded before retransmission. In Auto Echo mode, the /CTS input is ignored as a transmitter enable (although transitions on this input can still cause interrupts if programmed to do so). In this mode, the transmitter is actually bypassed and the programmer is responsible for disabling transmitter interrupts and WAIT//REQUEST on transmit. The SCC is also capable of local toopback. In this mode TxD is RxD is just like Auto Echo mode. However, in Local Loopback mode the internal transmit data is tied to the internal receive data and RxD is ignored (except to be echoed out via TxD). The /CTS and /DCD inputs are also ignored as transmit and receive enables. However, tran- sitions on these inputs can still cause interrupts. Local Loopback works in Asynchronous, Synchronous and SDLC modes with NRZ, NRZI or FM coding of the data stream. DMA Core. The SCC contains four independent fly-by mode DMA channels. Each of the {SCCs transmit and receive channels has a DMA channel dedicated to it to move data to-and-from memory. The DMA channels are dedicated to the transmit and receive FIFO's, and there- fore, can not be used for device initialization. Each DMA has a 32-bit address and a 16-bit byte counter. The DMA address may be incremented or decremented providing flexibility in doing block transfers. See the I/O Interface Capabilities Section for more details on the DMA features. 10@ BUS INTERFACE UNIT (BIU) DESCRIPTION The ISCC contains a flexible bus interface that is compat- ible with a variety of microprocessors and microcon- trollers. The device is designed to work with 8- or 16-bit bus systems and may be used with address/data multi- plexed busses or non-multiplexed busses. The multi- plexed bus is selected for the ISCC if there is an Address Strobe prior to or during the transaction which writes the BCR. Ifno Address Strobe is present prior to or during the transaction which writes the BCR, anon-multiplexed bus is selected. When the {SCC is initialized for non-multiplexed operation, register addressing for the ISCC cell is (with the exception of WRO and RRO), accomplished as follows. Programming the write registers requires two write operations and read- ing the read registers requires both a write and a read operation. The first write is to WRO which contains four bits that point to the selected register (note point high com- mand). The second write is the actual control word for the selected register. If the second operation is a read, the selected register is accessed. When in the non-multi- plexed mode, all of the registers in the SCC cell of the ISCC, including the data registers, are accessed in this fashion. The pointer register is automatically cleared after the second read or write operation so that WRO (or RRO) is addressed again. Note that when the DMA is not used to address the data, the data registers must be accessed by pointing to Register 8. This is in contrast to the Z8530 which allows directaddressing of the data registers through the C/D pin. When the ISCC is initialized for non-multiplexed operation, register addressing for the DMA cell (with the exception of CSAR) is accomplished as follows and is completely independent of the SCC cell register addressing. Pro- gramming the write registers requires two write operations and reading the read registers requires both a write and a read operation. The first write is to the Command Status Address Register (CSAR) which contains five bits that point to the selected register (CSAR bits 4-0). The second write is the actual control word for the selected register. If the second operation is a read, the selected register is accessed. When in the non-multiplexed mode, all of the registers in the DMA ceil of the ISCC may be accessed in this fashion. The pointer bits are automatically cleared after the second read or write operation so that CSAR is addressed again. When the ISCC is initialized for multiplexed bus operation, all registers in the SCC cell are directly addressable with the register address occupying AD5 through AD1, or AD4 through ADO (Shift Left/ Shift Right modes). Two additional pins, AO/SCC//DMA and A1/A//B control the channel A/B register selection and the SCC channel /DMA selection. Refer to the AO/SCC//DMA and A1/A//B pin descriptions for the encoding of these signals. The Shift Left / Shift Right modes for the address decoding for the internal registers (multiplexed bus) are separately programmable for the SCC cell and for the DMA cell. For the SCC cell the programming and operation is identical to that in the SCC; programming is accomplished through Write Register O (WRO), bits 1 and O (Figure 9-1). The programming of the Shift Left / Shift Right modes for the DMA cell is accomplished in the BCR, bit 0. In this case, the shift functionis similar to that for the SCC cell; with Shift left, the internal register addresses are decoded from bits ADS through AD1 and with Shift Right, the internal register addresses are decoded from bits AD4 through ADO. When the multiplexed bus mode is selected, Write Regis- ter 0 (WRO) takes on the form of WRO in the Z8030 ( Figure 9). Ail data transfers to and from the ISCC are done in bytes even though the data can, at special times, occupy the lower or upper byte of the 16-bit bus. When accessed as a peripheral device (i.e., when the SCC is not a bus master performing DMA transfers), all bus transactions are on the lower 8 bits of the bus with the following exception: When the ISCC registers are read, the byte data is present on both the lower 8 bits of the bus and the upper 8 bits of the bus. Data is accepted only on the lower 8 bits of the bus except in certain DMA transfers. During DMA transfers, data may be transferred to or from the ISCC on the upper 8 bits of the bus for odd or even byte transfers. During DMA transfers tomemory from the ISCC, byte data only is transferred and the data appears on both the lower 8 bits and is replicated on the upper 8 bits of the bus. During DMA transfers to the ISCC from memory, byte data only is transferred and normally data is accepted only on the lower 8 bits of the bus. However, the byte swapping feature may be used to elect on which byte of the bus the data is accepted. The byte swapping feature is enabled by programming the Byte Swap Enable bit to a 1 in the BCR. The odd/even byte transfer selection is made by programming the Byte Swap Select bitin the BCR. If Byte Swap Select is a 1, then even address bytes (transfers where the DMA address has AO equal 0) are transferredon the lower 8 bits of the bus and odd address bytes (transfers where the DMA address has AO equal 1) are transferred on the upper 8 bits of the bus. If Byte Swap Selectis a0, then even address bytes (transfers where the DMA address hasAO equal 0) are transferred on the upper 8 bits of the bus and odd address bytes(transfers where the DMA address has AO equal 1) are transferred on the lower 8 bits of the bus. VO INTERFACE CAPABILITIES The ISCC offers the choice of Polling, Interrupt (vectored or non-vectored), and DMA Transfer modes to transfer data, status, and control information to and from the CPU. Polling. In this mode all interrupts and the DMAs are disabled. Three status registers in the SCC are automati- cally updated whenever any function is performed. For example, end-of-frame in SDLC mode sets a bit in one of these status registers. With polling, the CPU must periodi- Cally read a status register until the register contents indicate the need for some CPU action to be taken. Only one register in the SCC needs to be read; depending on the contents of the register, the CPU either reads data, writes data, or satisfies an error condition. Two bits in the register indicate the need for data transfer. An alternative is to poll the interrupt Pending register to determine the source of an interrupt. The status for both SCC channels resides in one register. Interrupts. When the SCC responds to an Interrupt Ac- knowledge signal (INTACK) from the CPU, an interrupt vector is placed on the data bus. Both the SCC and the DMA contain vector registers. Depending on the source of interrupt, one of these vectors is returned. either unmodi- fied or modified by the interrupt status to indicate the exact cause of the interrupt. Each of the six sources in interrupts in the SCC (Transmit, Receive, and External/Status interrupts in both channels) and each DMA channel has three bits associated with the interrupt source: [Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). If the IE bit is set for any given source of interrupt, then that source can request interrupts. The only exception to this rule is when the associate Master Interrupt Enable (MIE) bit is reset, then no interrupts are requested. Both the SCC and the DMA have an associated MIE bit. The IE bits in the SCC are write only, but the JE bits in the DMA are read write. The ISCC provides for nesting of interrupt sources with an interrupt daisy chain using the IEI, EO, and INTACK pins. As amicroprocessor peripheral, the ISCC may request an interrupt only when no higher priority device is requesting one, e.g., when IE! is High. If the device in question requests an interrupt, it enables the /INT signal. The CPU then responds with /INTACK, and the interrupting device places the vector on the data bus. Inthe ISCC, the IP bit signals a need for interrupt servicing. When an IP bitis 1 and the IEI input is High, the /INT signal is activated, requesting an interrupt. In the SCC, if the IE bit is not set, then the IP for that source can never be set. The IP bits in the DMA are set independent of the iE bit. The IUS bits signal that an interrupt request is being serviced. If an IUS is set, all interrupt sources of lower priority in the ISCC and external to the ISCC are prevented from requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the ISCC being pulled Low and propagated to subsequent peripherals. internally, the SCC is higher priority than the DMA. An IUS bit is set during an Interrupt Acknowledge cycle if there are no higher priority devices requesting interrupts. Within the SCC portion of the ISCC there are three types of interrupts: Transmit, Receive, and External/Status. Each interrupt type is enabled under program control with Channel A having higher priority than Channel B, and with Receive, Transmit, and External/Status interrupts priori- tized in that order within each channel. When the Transmit interrupt is enabled, the CPU is interrupted when the transmit buffer becomes empty. This implies that the transmitter had a data character written into it to make it empty. When enabled, the receiver interrupts the CPU in one of three ways: 1. Interrupt on First Receive Character or Special Receive Condition 2. Interrupt on All Receive Characters or Special Receive Condition 3. Interrupt on Special Condition Only Interrupt on First Character or Special Condition, and Interrupt on Special Condition Only, are typically used when doing block transfers with the DMA. A Special Receive Condition is one of the following: receiver overrun, framing error in Asynchronous mode, end-of-frame in SDLC mode and, optionally, a parity error. The Special Receive Condition interrupt is different from an Ordinary Receive Character Available interrupt only by the status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First Receive Character, an interrupt occurs from Special Receive Conditions any time after the First Receive Character interrupt. 12 my wee ene, Cc@ The main function of the External/Status interrupt is to monitor the signal transitions of the /CTS, /DCD, and /SYNC pins; however, an External/Status interrupt is also caused by a Transmit Underrun condition, or a Zero count in the baud rate generator, or by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC- Loop mode) sequence in the data stream. The interrupt caused by the Abort or EOP has a special feature allowing the [SCC to interrupt when the Abort or EOP sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and the accurate timing of the Abort condition in external logic. Each DMA in the ISCC has two sources of interrupt, which share an IP bit and an IUS bit, but have independent enables: Terminal Count and Abort. The Abort interrupt is generated when an active DMA channel is forced to terminate its transfers because /BUSACK is de-asserted during a transfer. The Terminal Count interrupt is gener- ated when the DMA transfer count reaches zero. The DMA channels themselves are prioritized in a fixed order: Re- ceive A, Transmit A, Receive B, and Transmit B. DMA Transfer. In this mode, the on-chip DMA channels transfer data directly to the transmit buffers or directly from the receive buffers. No other transfers are possible (for initialization, for example). The request signals from the receivers and transmitters are hard-wired to the request inputs of the DMA channels internally. Each DMA channel provides a 32-bit address which is either incremented or decremented with a 16-bit transfer length. Whenever a DMA channel receives a request from its associated receiver or transmitter and the DMA channet is enabled, the ISCC activates the /BUSREQ signal. Upon receipt of an active /BUSACK, the DMA channel transfers data between memory and the SCC. This transfer continues until the receiver or transmitter stops requesting a transfer, until the terminal count is reached, or /BUSACK is deacti- vated. The four DMA channels operate independently when the Request Per Channel option is selected; other- wise, all requests pending at the time of bus acquisition will be serviced before the bus is released. Each DMA channel is independently enabled and disabled. Bus Interface. The ISCC contains a flexible bus interface that provides the resources necessary to interface the ISCC to virtually any type of bus. The [SCC directly supports either an 8-bit or a 16-bit bus, although all transfers to and from the device are limited to 8-bits at a time. The control signals provided allow connection to either a multiplexed address/data type bus or to a sepa- rate address and data type bus. While the ISCC is bus master, the upper address, lower address, and data are multiplexed on ADO-15. Interrupt Acknowledge is sig- naled through the /INTACK signal, which may be programmed as either a status input, a pulsed input, or a double-pulsed input. The ISCC also contains a MWAITIIRDY input for synchronizing CPU or DMA and memory accesses. This pin may be programmed to act as either a /WAIT signal or a/READY signal. The appropriate signal is provided by the ISCC when it is not bus master, and is sampled by the SCC when it is bus master. The ISCC requests the bus via a/BUSREQ signal and assumes bus mastership upon receipt of a /BUSACK signal. REGISTERS The ISCC contains separate register sets for the SCC core and the DMA core. Access to each setis controlled by the AO/SCC//DMA pin. When this pin is an input, a High selects the SCC core and a Low selects the DMA core. The first write to the iSCC after reset is always to the Bus Configu- ration Register (BCR), see Figure 8. If an /AS is present before the BCR is written to, a multiplexed bus is selected. Ifno/ASis present before the BCR write, anon-multiplexed bus is selected. The BCR cannot be changed without resetting the ISCC. [o7 [os os |o ]0s ] 02] 01 | oo] L_ Shift Right/Left Address for DMA interrupt Acknowledge Type Figure 8. Bus Contiguration Register (BCR) mets f f ' iSCC Cell. The SCC core contains 13 write registers (14 counting the transmit buffer) and ten read registers (11 counting the receive buffer) in each channel. Two of the write registers are shared (WR2 and WRQ) and are ac- cessed by both channels. WR2 contains the interrupt vector for both channels, while WR9 contains the interrupt control bits. Table 1 is a list of the SCC write registers and Table 2 is a list of the SCC read registers. Figures 9 and 10 show the write and read register formats. Read Regis- ters 6 and 7 are only accessible when the SDLC FIFO is enabled. When the SDLC FIFO is not enabled, Read Registers 6 and 7 are images of Read Registers 2 and 3, respectively. DMA Gell. The DMA cell contains 17 registers (counting the BCR). All of the registers are write/read except the BCR, CCAR and (CSR. The ISCC also has two status registers, the DMA status register (DSR) and the Interrupt Status Register (ISR), which are addressed by reading the CCAR and ICSR. The DMA also reserves two addresses for future use and should not be addressed or should be written with all zeros to prevent unexpected operation and maintain compatibility with future products. Each DMA channel has a 32-bit wide address register providing an addressing range of 4 gigabytes. Each channel also has a 16-bit count register for up to 64K byte data packet sizes. Table 1. SCC Write Registers Bit Description WRO Register Pointers, various initialization commands WR1_ Transmit and Receive interrupt enables, WAIT/DMA commands WR2 _ interrupt Vector WR3__~ Receive parameters and control modes WR4 __ Transmit and Receive modes and parameters WR5 Transmit parameters and control modes WR6__ Sync Character or SDLC address WR7 Sync Character or SDLC flag WR8 _ Transmit buffer WRQ_ Master Interrupt control and reset commands WR10. Miscellaneous transmit and receive control bits WR11. Clock mode controls for receive and transmit WR12 Lower byte of baud rate generator WR13 Upper byte of baud rate generator WR14 Miscellaneous control bits WR15_ External status interrupt enable control : 14Write Register 1 [07 ]06 [os] os Jos | 2} os | vo] Write Register 0 (non-muitiplexed bus mode) [07 [sos ]> ]00] p2 [0+ | oo | | | L_ Ext int Enable 0 Register 0 | ! 0 0 1 Register 1 Tx Int Enable 0 1 OO Register 2 Partty ts Special Condition 0 1 1 Register3 i 0 : Reviter 5 0 Rx Int Disable 1 #1 #490 Revetor 6 1 Rx Int On First Character or Special Condition 1 1 1 Register7 Q Int On All Rx Characters or Special Condition 0 0 O Registers 1 Rx Int On Special Condition Onty 0 0 1 Register 9 0 1 0 Register 10 WAIT/OMA Request On 0 1 1 + Register 11 * Receive//Trans! 1 0 0 Register 12 t 1 0 1. Register 19 WAIT/DMA Request Function 1 1 0 Register 14 WAIT/DMA Request Enable 1 4 4 Register 15 0 0 O Null Code 0 0 1. Point High 0 1 0 Reset Ext/Status Interrupts Write Register 2 Pi) eee bres 1. 0 0 Enable int on Next Rx Character [07 [06 [0s [>4 03 | 02 | 01 | bo) 1 0 + Reset Tx Int Pending 1 1 0 Error Reset | 1 1 1 Reset Highest 1US vo vi OG 0 Null Code v2 OQ 1 Reset Rx CRC Checker 1 0 Reset Tx CRC Generator v3 Interrupt 1 1 Reset Tx Underrun/EOM Latch vA Vector * With Point High Command V5 V6 vw Write Register 0 (multiplexed bus mode) [> [oe os]o]oa]o2]o* [oo | | Write Register 3 0 [27 [06 Jos fos | 02} 02 Jo1 | oo | | L_ Rx Enable Syne Character Load Inhibit 0 O O Null Code Address Search Mode (SDLC) 0 0 1 Null Code Rx GRC Enable 0 1 O Reset Ext/Status Interrupts 0 1 1 Send Abort Enter Hunt Mode 1 0 0 Enable int on Next Rx Character auto Enab 1 0 1. Reset Tx Int Pending 1 1 OQ Error Reset 1 1 1 Reset Highest IUS 0 O Rx 5 Bits/Character 0 1 Rx7 Bits/Character 1 0 Rx 6 Bits/Character 0 Null Code 1 1 Ax 8 Bits/Character 0 1 Reset Rx CRC Checker 1 0 Reset Tx CRC Generator 1 1 Reset Tx Underrun/EOM Latch * B Channel Only Figure 9. Write Register Bit Functions PENIS SN 0 ST ETL RR OR OS EN EERIE 15Write Register 4 Parity EVEN//ODD Syne Modes Enable 1 Stop Bit/Character 1 1/2 Stop Bits/Character 2 Stop Bits/Character | | L_ Parity Enable 0 oO o 1 1 0 14 Write Register 5 6 Tx GRC Enable RTS SDLC/CRC-16 Tx Enable Send Break [- 0 0 Tx5 Bits(Or Less)/Character 0 O 8-Bk Sync Character 0 1 1x7 Bits/Character 0 1 16-Bf Sync Character 1 O Tx 6 Bits/Character 1 0 SDLC Mode (01111110 Flag) 1 1) 1x8 Bits/Character 1 1 External Sync Mode 0 0 X1 Clock Mode @ 1 X16 Clock Mode 1 0 X32 Clock Mode 1 1 X64 Clock Mode (ore [oso oo] o=] > [m] [er]os]os ][o4]os]o2]o1 [oo] Sync7 Sync4 = Sync Monosync, 8 Bits Sync1 Sync Sis Sync4 = Sync3 Synca Syrci Synod Monosync, 6 Bits Sync7 Synce6 SyncS Sync4 Sync3 Sync2 Synct Sync0 Bisync, 16 Bits Sync3 Sync2 Sync! = SyncO 1 1 1 1 Bisync, 12 Bits ADR7 ADR6 ADRS ADR4 ADR3 ADR2 ADR1 ADRO SDLC ADR7 ADR6 ADRS ADR4 x x x x SDLC (Address Range) Figure 9. Write Register Bit Functions (Continued) q@ 16 wee e ae ens iWrite Register 9 [07 [oe] os Jos os} 2] 03 Joo o let 0 0 No Reset 4 0 1 Channel Reset B 1 Channel Reset A 1 1 Force Hardware Reset Write Register 10 [07 ]o]0s ] 04] ps ] 02] 0s [po] ~=-0600 FMI (Transition = 1) 0 1 NRZI 0 1 FMO (Transition = 0) Write [oro oe] oo [oe 7 [>7os]os]o os [oe] [oo] ml gyre? Sync6 Sync5 Syncs Sync4 Sync3_ Sync2 Synct5 Synct4 Synet3 Synet2 Sync11 Synct0 Sync Sync8 0 1 1 1 6 Bit//e BR Sync Loop Mode Abort//Flag On Underun Mark//Flag idle Go Active On Poll CRC Preset 1/0 Sync3 Sync2 Syret Sync Monosyne, 8 Bits ynct Syncd Monosyne, 6 Bits Sync11 Synci0 sync synce Bisync, 16 Bis Syne7 Sync6 SyncS Sync4 Bisync, 12 Bits 1 1 1 0 SOLC Write Register 11 [07 [os [os] 04] 02} 2] 0+ | vo] 0 0 /TRXC Out = Xtal Output 0 1 /TRxC Out Transmit Clock 1 0 /TRxC Out = BR Generator Output 1 1 /TAxC Out = DPLL Output TRxC OA 0 0 Transmit Clock = /ATxC Pin 0 1 Transmit Clock = /TRxC Pin 1. 0 Transmit Clock = BR Generator Output 1 1. Transmit Clock = DPLL Output 0 OQ Receive Clock = /RTxC Pin 0 1. Receive Clock = /TRxC Pin 4 0 Receive Clock = BR Generator Output 1 1. Receive Clock = DPLL Output /RTxC Xtal//No Xtal Write Register 12 [07 [ps | 0s | 0s ] 09 v2 || oo] | L_ TCO TC1 Tc2 Tc3 Lower Byte of TCs Time Constant TCS TCE 1c7 Figure 9. Write Register Bit Functions (Continued) 17Write Register 13 D7 Write Register 14 6 [o7 [06 Jos J > [ba [02 [ot [oo for] ve [os] >< 58] 52] 0: [on] | H ros | Le sree ene BR Generator Source TC10 /OTRRequest Function To U B Ipper Byte of Ect To12 Time Constant Auto Local Loopback To13 TO14 0 0 0 Null Command Tc15 0 0 1 Enter Search Mode 0 1 0 Reset Missing Clock 0 1 1 Disable DPLL 1 0 0 Set Source = BR Generator 1 1 Set Source = RTxC 1 1 0 Set FM Mode 1 1 1 Set NRZI Mode Write Register 15 Jor} os]> [oa] o2]o1] 00 | tH Zero Count IE SDLC FIFO Enable DCD IE Syne/Hunt iE CTS IE Tx Underrun/EOM IE Break/Abort IE 9 Figure 9. Write Register Bit Functions (Continued) Table 2. SCC Read Registers Bit Description RRO Transmit and Receive buffer status and external status RR1 Special Receive Condition status RR2 Modified interrupt vector (Channel B only), Unmodified interrupt vector (Channel A only) RR3 Interrupt pending bits (Channel A only) RR6 SDLC FIFO byte counter lower byte (only when enabled) RR7 SDLC FIFO byte count and status (only when enabied) RR8 Receive buffer RR10 Miscellaneous status bits RR12 Lower byte of baud rate generator time constant RR13 Upper byte of baud rate generator time constant RR15 External Status interrupt information 18d Read Register 0 [07 [98 05 Jo os [2 } ot {oo [= - Rx Character Avallable Zero Count Tx Buffer Empty Read Register 1 107 [os [os ]o Joa Joe os | bo - All Sent Residue Code 2 Residue Code 1 Residue Code 0 Parity Error (= Read Register 2 }07 [6] 0s Jo [0] 02 os [00 [e - * Modified In B Channel Rx On Error CRC/Framing Error End of Frame (SDLC) vo 1 v2 v3 Interrupt va Vector * V5 ve Read Register 3 g - Channel B Ext/Status IP Channel 8 Tx IP Channel B Rx IP . Channel A Ext/Status IP Channel A Tx IP Channel A Rx IP 0 * Always 0 In B Channel Read Register 6 * J07 [08 [os] ps] 00] 02 os | v0] L_ BCO BC1 BCc2 BCc3 BC4 BCs BCE BC7 * Can only be accessed if the SDLC FIFO enhancement is enabled (WR15 bit D2 set to 1) SDLC FIFO Status and Byte Count (LSB) Read Register 7 * Ls BCS BC10 BC11 Bc12 BCc13 FDA: FIFO Available Status 1 = Status Reads from FIFO FOS: FIFO Overflow Status 1 = FIFO Overflowed 0 = Noma g * Can only be accessed if the SDLC FIFO enhancement is enabled (WR15 bit 02 set fo 1) SDLC FIFO Status and Byte Count (MSB) Figure 10. Read Register Bit Functions 19 conn geeon 9 N Read Register 10 Read Register 13 0 }07 | 06} 05 | o4] 03 | 2 [os [00 [07 Jos | 05 | 4] 09] p2] 0 | oo) | | On Loop | [ Tc9 0 TC10 0 Tet Upper Byte Loop Sending Tc12 of Time Constant 0 To13 Two Clocks Missing TC14 Read Register 12 Read Register 15 }o7 08 [os [os | 02 [2 | v1 [oo oz ]o2 os Jv [3 [D2 | os Joo] Tco | | L_ 0 Tet Zero Count IE Tc2 0 . Tca Lower Byte DCD IE Tc of Time Constant SynefHunt IE Tcs CTSIE T= TCc Tx Und (EOM IE Tc7 Break/Abort IE Figure 10. Read Register Bit Functions (Continued)Hoe A ei ta : 122A aera ant ha tale wm ER Nt cote Table 3. DMA Cell Register Description Address Name Description XXXXX BCR Bus Configuration Register 00000 CCAR Channe! Command/Address Register (Write) 00000 DSR DMA Status Register (Read) 00001 ICR Interrupt Control Register 00010 IVR Interrupt Vector Register 00011 ICSR Interrupt Command Register (Write) 00011 ISR Interrupt Status Register (Read) 00100 DER DMA Enable/Disabie Register 00101 DCR DMA Control Register 00110 Reserved Address 00111 Reserved Address 01000-01001 RDCRA Receive DMA Count Register Channel A (Low-high byte) 01010-01011 TDCRA Transmit DMA Count Register Channel A 01100-01101 RDCRB Receive DMA Count Register Channel B 01410-01111 TDCRB Transmit DMA Count Register Channel B 10000-10011 RDARA Receive DMA Address Register Channel A 10100-10111 TDARA Transmit DMA Address Register Channel A 11000-11011 RDARB Receive DMA Address Register Channel B 14100-11111 TDARB Transmit DMA Address Register Channel B Address: 00000 (Write) Address: 00000 (Read) or oso ]oe] so ]o=] >" ]oo] >=] o=] oe] =] se] L_ Address 0 | | Tx B DMA Abort Address 1 Rx B DMA Abort Address 2 Tx A DMA Abort Address 3 Fix A DMA Abort Address 4 Tx B DMA Terminal Count DMA Commands Fix B DMA Terminal Count 0 0 0 Nut Command Tx A DMA Terminal Count 0 0 1 Reserved 0 1 0 Reset Highest [US Rx A DMA Terminal Count 0 1 1 DMAReset 1 0 Enable Tx B DMA 1 1. Enable Rx 8 DMA 1 1 Enable Tx A DMA 1 1 1 Enable Px A DMA Figure 12. DMA Status Register Figure 11. Channel Command/Address Register 21Address: 00001 Jor [8] os Jo [oe [oe [0% Joo [_ Tx B DMA interrupt Enable Fx B DMA Interrupt Enable Tx A DMA Interrupt Enable Fix A DMA interrupt Enable vis NV DLc MIE Figure 13. Interrupt Control Register Address: 00010 Jo7 Js [0 [4] os] 02 [0% Too M1 v2 * Iva V4 vs v6 V7 * Potentially modified by interrupt condition Figure 14. Interrupt Vector Register Address: 00011 (Write) o7 os | os ]o]os]o2]o: Joo] Select Tx B DMA Select Rx B DMA Select Tx A DMA Select Rx A DMA Reserved DMA Interrupt Commands - 0 0 O Nu Command 0 O 1 Reset IP 0 1 O Reset ius 0 1 1 Reset IP and 1US 1 0 O Reserved 1 0 1 SetIP 1 1 #O Setlus 1 1 1 SetIP andIus Figure 15. Interrupt Command/Register Address: 00011 (Read) [e708 Jos [o oe [oz ]os [oo] - [Ee Tx B DMA IP Rx B DMA [P Tx A DMA iP Rx A DMA IP Tx B DMA IUS Rx B DMA IUS Tx A DMA IUS Rx A DMA IUS Figure 16. Interrupt Status Register Address: 00100 07 os fos [04] os oe] ot [oo (e - Tx B DMA Abort Enable Rx B DMA Abort Enable Tx A DMA Abort Enable Rx A DMA Abort Enable Tx B DMA Enable Rx B DMA Enable Tx A DMA Enable Rx A DMA Enabie Figure 17. DMA Enable Register Address: 00101 07 Jos] 0s |p4 fos] o2 fo: [oo] 0 9 1 1 - = DMA Priority Rx A/Tx A/Rx B/Tx B Rx B/Tx B/Rx A/Tx A Rx AVRx B/Tx A/Tx B Rx B/Rx A/Tx B/Tx A =o+-0 Figure 18. DMA Control Register Tx B DMA Address Inc//Dec Rx B DMA Address Inc//Dec Tx A DMA Address Inc//Dec Rx A DMA Address Inc//Dec Reserved Bus Request per Channel e01001 (High Byte) 01001 (High Byte} o7 [08] os [4 fos [2 }os [oo Jo? [os ]05 Jo] 00] 02] 01] Do Rx ACnto Rx A Crite Rx A Crit Rx A Crto Rx A Cnt2 Rx A Cnitto Rx A Cnia Ax ACatt1 Rx A Crta Rx A Cati2 Rx A Cts Rx ACatt3 : Rx A Cni Rx ACntt4 Rx A Cnt7 Rx A Cots : (A) LSB (B) MSB ( 0 Address: 01000 (Low Byte) Address: 01000 (Low Byte) /- i Figure 19. Receive DMA Count Register Channel A 0 Address: 01010 (Low Byte) Address: 01010 (Low Byte) 01011 (High Byte) 01011 (High Byte) e [07 | 06] 0s | o [0a [oe] 01 | bo) [7] 8 | os [D4 | 03] b2 [01 | . | [_ Tx A Cnto | [_ Tx A Cts Tx ACntt Tx A Cnt9 Tx A Cai2 Tx A Cntto Tx ACnt3 Tx A Critt1 Tx A Cats Tx A Crntt2 Tx ACatS Tx A Cnti3 Tx A Cnt Tx A Cnti4 Tx ACnt7 TxA Cntts (A) LSB (B) MSB Figure 20. Transmit DMA Count Register Channel A 23Address: 01100 (Low Byte) 07 [8 [os | o | 03] 02] os [oo 01101 (High Byte) Address: 01100 (Low Byte) 01101 (High Byte) [07 [8 os | p [os [2 [b+ | vo] | g22 eae Le = Rx B Crt7 Address: 01110 (Low Byte) o7 [06 os o J 03 Joa Jo [00 01111 (High Byte) (A) LSB (B) MSB Figure 21. Receive DMA Count Register Channel B Address: 01110 (Low Byte) 01111 (High Byte) b7 }o8 jos | 4 [3 | ne Jo [00 Tx B Cnto Tx B Catt Tx B Cnt2 Tx B Cnt3 Tx B Cnt4 Tx B Cats Tx B Cnt Tx B Cnt7 | [- (A) LSB (B) MSB Figure 22. Transmit DMA Count Register Channel B g 2 ii Rx B Crtto Rx B Cott Rx B Crtt2 Rx B Cntt3 Rx B Cnit4 Rx B Cntt5 Tx B Cnt Tx B Cato Tx B Cm10 Tx B Cntt1 Tx B Cntt12 Tx B Catt3 Tx BCm14 Tx BCm15 24( | Adkdress: 10000 (Bits 0-7) }o7 [66 ]05] 04 J 02] 2] 01 |o0| | | L_ Pix A Addr Rx A Addrt Px A Addr2 Px A Add Pix A Addr4 Px A Adds Px A Addr (A) Address: 10001 (Bits 8-15) Dy (9 (B) a a 7 A [= Rx A Addr7 Rx A Addr8 Rx A Addrd Rx A Addrt0 Rx A Addr11 Rx A Addni2 Rx A Addrt3 Rx A Addr14 Rx A Addr 5 Address: 10010 (Bits 16-23} o ~ T= Address: 10011 (Bits 24-31) g (D) Figure 23. Receive DMA Address Register Channel A Rx A Addri Rx A Addr17 Rx A Addr18 Rx A Addr19 Rx A Addr20 Rx A Addr21 Rx A Addr22 Rx A Addr23 ee AM iAddress: 10100 (Bits 0-7) o7 os [05] p4 fos] o2 [0+ [oo Tx A AddrO Tx A Addr1 Tx A Addr2 Tx A Addr Tx A Addr4 Tx A Addr5 Tx A Addr Address: 10101 (Bits 8-15) [ ie Tx A Addr7 Tx A Addr8 Tx A Addro Tx A Addr10 Tx A Addr11 Tx A Addri2 Tx A Addr13 Tx A Addrt4 (B) Tx A Addr15 Address: 10110 (Bits 16-23) }o7 [06 os [4 [oa | 2 | os | [= [F- Address: 10111 (Bits 24-31) (C) [07 [0s [os [ Js J 02 Jor [oo - (D) Figure 24. Transmit DMA Address Register Channel A Tx A Addr16 Tx A Addr17 Tx A Addr18 Tx A Addri9 Tx A Addr20 Tx A Addr21 Tx A Addr22 Tx A Addr23 Tx A Addr24 Tx A Addr25 Tx A Addr26 Tx A Addr27 Tx A Addr28 Tx A Addr29 Tx A Addr30 Tx A Addr31 26(9 (9 tt atta Address: 11000 (Bits 0-7) Jor js] 05] p+ oe [oe or [oo i Rx B Addro Rx B Addr1 Rx B Addr2 Rx B Addr3 Rx B Addr4 Rx B AddrS Rx B Addr Rx B Addr7 (A) Address: 11001 (Bits 8-15) 07 }o6] os Jos [oe] oe [ox [oo] iz Rx B Adds Rx B Addo Rx B Addr10 Rx B Addrt1 Rx B Addri2 Rx B Addr13 Rx B Addr14 (B) Rx B Addrt5 Address: 11010 (Bits 16-23) }07 [6] 5 }os [oe [oe [or [oo] | Rx B Addr17 Rx B Addr18 Rx B Addri9 Rx B Addr20 Rx B Addr21 Rx B Addr22 Rx B Addr23 Address: 11011 (Bits 24-31) - Rx B Addri (C) [07 [6 05 [04] pa] 02 fos [oo] Rx B Addr24 Rx B Addr25 I Rx B Addr26 Rx B Addr27 Rx B Addr28 Rx B Addr29 Rx B Addr30 Rx B Addr31 (D) Figure 25. Receive DMA Address Register Channel B EO EU Re et CR me ne 27 TaareAddress: 11100 (Bks 0-7) Jo7 | 06] 05 Jo4 Jos 02 [os | oo i ia Address: 11101 (Bits 8-15) g i i (B) Tx B Added Tx B Addrl Tx B Addr2 Tx B Addr3 Tx B Addr4 Tx B AddrS Tx B Addr6, Tx B Add7 Tx B Addr Tx B Addrd Tx B Addrt 0 Tx B Addit 1 Tx B Addri2 Tx B Addri3 Tx B Addr14 Tx B Addr 5 Address: 11110 (Bits 16-23) Jo7 [6 ] 05] o Jos] oz] 0+ {oo | (C) Address: 11111 (Bits 24-31) Jor 0s [05 [04 fos Joe | oJ v0] (D) Figure 26. Transmit DMA Address Register Channei B Tx B Addri6 Tx B Addrt7 Tx B Addri8 Tx B Addri9 Tx B Addr20 Tx B Addr21 Tx B Addr22 Tx 8 Addr23 Tx B Addr24 Tx B Addr25 Tx B Addr26 Tx B Addr27 Tx B Addr28 Tx B Addr29 Tx B Addr30 Tx B Addr31 dVJ ABSOLUTE MAXIMUM RATINGS Voltages on all pins, with respect TO GND. eect cs ceetececeeceeneaeeetetaees 0.3V 10 +7.0V Operating Ambient Temperature 0... eceeeeees See Ordering Information Storage Temperature 00.00... cece -85C to 150C Voltages on all inputs, with respect TO GND once eee eteeeteteteneeeeseees -0.3 V to V, + 0.3 V Stresses greater than those listed under Absolute Maxi- mum Ratings may cause permanent damage to the de- vice. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. STANDARD TEST CONDITIONS The DC Characteristics and Capacitance section below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin. Standard conditions are as follows: +4.75 Vs Vcc $5.25 V GND =0V T, as specified in Ordering Information 2.0K 2 From Output Under Test 80 pt 250 pA Figure 27. Standard Test Load CAPACITANCE Symbol Parameter Min Max Unit Condition Cy, Input Capacitance 10 pF Unmeasured Pins Cour Output Capacitance 15 pF Returned to Ground Cw Bidirectional Capacitance 20 pF f = 1 MHz over specfied temperature range. Unmeasured pins returned to ground. Miscellaneous: Transistor Count52,047 Z16C35 DC CHARACTERISTICS Symbol Parameter Min Typ Max Unit Condition Vee Input High Voltage 2.2 Veg +0.3 Vv Ve Input Low Voltage -0.3 0.8 Vv Vout Output High Voltage 2.4 Vv ly = 1-6 MA Vow Output High Voltage VV, -0.8 Vv logy = -200 pA Vo. Output Low Voltage 0.4 Vv lg = +2.0 mA I Input Leakage + 10.00 pA 04<V,,<+24V la Output Leakage + 10.00 pA 0.4 < Vag < +2.4V Voc Voge Supply Current 7 50 mA Voge = SV. VY, = 4.8 V, V, = 0.2V Vee = 5 V + 5% unless otherwise specified, over specified temperature range.AC CHARACTERISTICS 10MHz * No Symbol Parameter Min Max Notes 1 Tcyc Bus Cycle Time ATcPC 2 TwASl /AS Low Width 40 3 TwASh /AS High Width 90 4 TwDSI /DS Low Width 70 5 TwDSh /DS High Width 60 6 TdAS(DS) IAST to /DSL Delay Time 5 7 TdDS(AS) /DST to /ASJ Delay Time 5 8 TdDS(DRa) /DS4 to Data Active Delay 0 9 TdDS(DRv) /DSJ to Data Valid Detay 85 10 TdDS(DRn) /OST to Data Not Valid Delay 0 1 TdDS(DRz) /DST to Data Float Delay 20 12 TsCS(AS) ICS to /AST Setup Time 15 13 ThCS(AS) ICS to /AST Hold Time 0 14 TsADD(AS) Direct Address to /AST Setup Time 15 [1] 15 ThADD(AS) Direct Address to /AST Hold Time 5 [1] 16 TsSIA(AS) Status /INTACK to /AST Setup Time 15 17 THSIA(AS) Status /INTACK to /AST Hold Time 5 18 TsAD(AS) Adress to /AST Setup Time 15 19 ThAD(AS) Address to /AST Hold Time 5 20 TsRW(DS) R/W to /DSL Setup Time ) 21 ThRW(DS) R/MW to (DSL Hold Time 25 22 TdDSK(RDY) /DSI to (READYL Delay 50 23 TdDSr(RDY) /DST to /READYT Delay 40 24 TsDW(DS) Write Data to /DSJSetup Time 0 25 ThDW(DS) Write Data to /DSLHold Time 25 26 TdRDY(DRv) /READY4 to Data Valid Delay 40 28 TwRDI {RD Low Width 70 29 TwRDh {RD High Width 60 30 TdAS(RD) /AST to /RDL Detay Time 5 31 TdRD(AS) /RDTto /ASL Delay Time 5 32 TdRD(DRa) /RDJ to Data Active Delay 0 33 TdRD(DRv) /RDL to Data Valid Delay 85 34 TdRD(DRn) /RDT to Data Not Valid Detay 0 35 TdRO(DRz) /RDTto Data Float Delay 20 36 TdRD{&(RDY) /RDLto READY Delay 50 37 TdRDr(RDY) IRDT to /READYT Delay 40 38 TwWRI MWR Low Width 70 39 TwWRh MR High Width 60 40 TdAS(WR) /AST to (WR Delay Time 5 At TdWR(AS) WeTto ASL Delay Time 5 * Units in nanoseconds. 30 wosMF Ate gg AC CHARACTERISTICS (Continued) 10MHz * No Symbol Parameter Min Max Notes 42 TsDW(WR) Write Data to /WRL Setup Time 0 43 ThDW(WR) Write Data to (WRL Hold Time 25 44 TdWRi(RDY) MWR to /READYL Delay 50 45 TdWRr(RDY) MRT to /READYLDelay 40 46 TsCS(DS) ICS to /DSL Setup Time 0 (2] 47 ThCS(DS) ICS to /DS1 Hold Time 25 [2] 48 TsADD(DS) Direct Address to /DS1 Setup Time 9) (1,2] 49 ThADD(DS) Direct Address to /DSJ Hold Time 25 [1,2] 50 TsSIA(DS) Status /INTACK to /DS! Setup Time 0 (2] 51 ThSIA(DS) Status /INTACK to /DSL Hold Time 25 [2] 52 TsCS(RD) ICS to /RDJL Setup Time 0 (2) 53 ThCS(RD) ICS to (RDJL Hold Time 25 {2] 54 TsADD(RD) Direct Address to /RDLSetup Time 8) [1.2] 55 ThADD(RD) Direct Address to /RDJ Hold Time 25 [1,2] 56 TsSIA(RD) Status /INTACK to /RDJL Setup Time 0 (2] 57 ThHSIA(RD) Status /INTACK to /RDL Hold Time 25 (2] 58 TsCS(WR) /CS to WRI Setup Time 0 {2] - 59 ThCS(WR) ICS to WRI Hold Time 25 [2] 60 TsADD(WR) Direct Address to /WRL Setup Time 0 [1,2] 61 ThADD(WR) Direct Address to /WRJ Hold Time 25 [1,2] 62 TsSIA(WR) Status /INTACK to (WRI Setup Time 0 (2] 63 ThSIA(WR) Status /INTACK to /WRL Hold Time 25 {2] 78 TdDSKRDY) /DS1. (Intack) to (READY Delay 300 [4] 81 TsIEl(DSI) IE! to (DSL (Intack) Setup Time 60 82 ThIEI(DSI) IEl to /DST (intack) Hold Time 0) 83 TdIEM(IEO) IE] to [EO Delay 60 84 TdAS(IEO) /AST or Status Intack to EO Delay 60 85 TdDSI(INT) /DS4 (Intack) to /INT Inactive Delay 200 86 TdDSK(Wh) /DSJ (Intack) to WAITS Delay 40 87 TdOSI(Wr) /DSJ (Intack) to WAITT Delay 300 [4] 88 TdW(DRy) MAITT to Data Valid Delay 40 89 TdRDI(RDY) /RD4 (intack) to READYL Delay 300 [4] 91 TsIEKRDI) IEI to RD (Intack) Setup Time 60 92 ThIEKRD!) IEl to (ROT (Intack) Hold Time 0 93 TdRDI(INT) IRD (intack) to (INT Inactive Delay 200 94 TdRDI(WE) /RDL (Intack) to WAITL Delay 40 95 TdRDI(Wr) /RD4J (Intack) to WAITT Delay 300 [4] 96 TwPIA | Pulsed /INTACK Low Width 70 97 TwPIAh Pulsed /INTACK High Width 60 98 TdAS(PIA) /AST to Pulsed /INTACK Delay Time 5 * Units in nanoseconds. 31AC CHARACTERISTICS (Continued) 10MHz * No Symbol Parameter Min Max Notes 99 TdPIA(AS) Pulsed /INTACKT to /ASJ Delay Time 5 100 ~- Td PIA(DRa) Pulsed /INTACK4 to Data Active Delay 0 101. TdPEA(DRn) Pulsed /INTACKT to Data Not Valid Delay 0 102. Td PIA(DRz) Pulsed /INTACKT to Data Float Delay 20 103 TSIEI(PIA) IEI to Pulsed /INTACK Setup Time 60 104 ThiEI(PIA) IEl to Pulsed /ANTACKT Hold Time 0 105 TdPIA(IEO) Pulsed /INTACK4L to IEO Delay 60 106 TdPIA(INT) Pulsed /INTACK4 to /INT Inactive Delay 200 107 TdPIA(RDY) Pulsed /INTACKL to /READYL Delay 300 (4] 108 TdPIAr(RDY) Pulsed /INTACKT to /READYT Delay 40 109. TdPIA(Wf) Pulsed /INTACK to /WAITL Delay 40 110 = TdPIA(Wr) Pulsed /INTACK to /WAITT Delay 300 [4] 111. TdSIA(INT) Status /INTACK4 to /INT Inactive Delay 200 [2] 113 TwRESI /RESET Low Width 170 114 TwRESh [RESET High Width 60 115 TdRES(STB) /RESETT to /Strobed 60 (3] 116 =TdPC(BUSa) PCLKT to Bus Active Delay 40 [5] 117 TdPC(BRQ) PCLKT to /BUSREQ Delay 40 118 TsBAK(PC) /BUSACK to PCLKT Setup Time 10 119 ThBAK(PC) /BUSACK to PCLKTHold Time 30 120 = TwPCl PCLK Low Width 35 121 = TwPCh PCLK High Width 35 122 TcPC PCLK Cycle Time 100 123. TIPC PCLK Fall Time 10 124 TrPC PCLK Rise Time 10 125. TdPCr(UAS) PCLKT to /UAS Delay 30 [5] 126 TWUASI /UAS Low Width 30 (5,6) 127. TdPCf(UAS) PCLK1 to /UAS Delay 30 [5] 128 TdPCr(AS) PCLKTto /AS Delay 30 (5) 129 TwASI /AS Low Wiath 30 [5,6] 130. TdPCK(AS) PCLK to /AS Delay 30 [5] 131 TdAS(DSr) /AST to (OS (Read) Delay 30 [5.7] 132. TdDS(PCr) PCLKT to /DS Delay 30 [5] 133. TwDSir /DS Low Width (Read) 135 [5,8] 134 TdPCf(DS) PCLK to /DS Delay 30 [5] 135. TsDR(DS) Read Data to /DST Setup Time 30 [5] 136 ThDR(DS) Read Data to /DST Hold Time 0 [5] 137. TdPC(RW) PCLKT to R//W Delay 30 [5] 138 TdAS(RD) /AST to /RDL Delay 30 [5,7] 139. TdPCr(RD) PCLKT to /RD Delay 30 [5] * Units in nanoseconds. 32AC CHARACTERISTICS (Continued) 10MHz * No Symbol Parameter Min Max Notes 140 TwADI /RD Low Width 135 [5.8] 141 TdPCI(RD) PCLK to /RD Delay 30 [5] 142 TsDR(RD) Read Data to /RDT Setup Time 30 [5] 143. ThDR(RD) Read Data to /RDT Hold Time 0 [5] 144 TdPC(ADD) PCLKT to Direct Address Delay 30 [1,5] 145 = TdPC(AD) PCLKT to Address Delay 40 [5] 146 ThAD(PC) Address to PCLKT Hold Time 0 [5] 147 TdPC(ADz) PCLKT to Address Float Delay 50 [5] 148 TdPC(ADa) .PCLKT to Address Active Delay 40 [5] 149 TsAD(UAS) Address to /UAST Setup Time 20 [5] 150 ThAD(UAS) Address to /UAST Hold Time 20 [5] 151 TsAD(AS) Address to /AST Setup Time 20 [5] 152. ThAD(AS) Address to /ASTHold Time 20 [5] 153. TsW(PC) WAIT to PCLKL Setup Time 10 (5] 154 ThW(PC) MAIT to PCLK4 Hold Time 30 [5] 155 TsRDY(PC) IREADY to PCLK Setup Time 10 [5] 156 ThRDY(PC) [READY to PCLKL Hold Time 30 (5] 157 ThDW(PC) Write Data to PCLKT Hold Time 0 [5] 158 TdAS(DSw) /AST to /DS! (Write) Delay 85 (5.9] 159 TsDW(DS) Write Data to /DSJ Setup Time 30 [5,6] 160 TwDSlw /DS Low Width (Write) 90 [5,10] 161 ThDW(DS) Write Data to /DST Hold Time 30 (5, 7] 162. TdAS(WR) /AST to WRI Delay 85 (5,9] 163 TsDW(WR) Write Data to WRI Setup Time 30 [5.6] 164. Twwri WR Low Width 90 (5,10) 165 ThDW(WR) Write Data to (WRT Hold Time 30 {5,7] 166 TdPC(WR) PCLK4 to (WR Delay 30 [5] 167 TdPC(BUSz) PCLKT to Bus Float Delay 50 (5) Notes: [1] Direct address is A1/A//B or AO/SCC//DMA. [2] The parameter applies only when /AS is not present. [3] /Strobe is any of /DS, /RD, WR or Pulsed /INTACK. [4] Clock-cycle dependent, 2TcPC + TwPCl + TIPC + 55. (5) Parameter applies only while ISCC is bus master. [6] Clock-cycle dependent, TwPCh + TEPC - 15. [7] Clock-cycle dependent, TwPC1 + TrPC - 15. [8] Clock-cycle dependent, TePC + TwPCh + TrPC - 10. [9] Clock-cycle dependent, TePC - 15. [10] Clock-cycle dependent, TePC - 10. * Units in nanoseconds. 33yoo a ts | AVAIB K A0/SCCH/DMA a ANTACK (Status) / A ! Oey +t G | ns it Kf ' (6 )>| >-7) @ > (1} \ _~= i Raw / ' \ sl 0 7 __ /0S N. 7 \ at (4)} a at )}__>} ADO-AD15 \f \ L 4 y 18 att 8 10 > W MAITRDY / (Wait) MAITIRDY (Ready) @) 8) Figure 28. Multiplexed /DS Read Cycle 34 | reer| i ics AT/IA/B A0/SCC/IDMA ANTACK (Status) JAS RW Ds ADO-AD15 MWAIT//RDY (Wait) MAIT/RDY (Ready) [ 1 . 8 Figure 29. Multiplexed /DS Write Cycle 35A wim we eee tee eee en enn ee ics AVAB A0/SCC//DMA ANTACK (Status) JAS /RO ADO-AD15 MWAITHRDY (Walt) MATT/RDY (Ready) <++@ oy) . ; K 7 A r @ ! @ _/ _/ Figure 30. Multiplexed /RD Read Cycle 36AU/A/B AQ/SCC//DMA marci x K_ i) ses 7, /AS 4 Ie ' Q ADO-AD15 ><) WAIT/IADY | (Ready) ) @ AWATTIOY / _/ Figure 31. Multiplexed /WR Write Cycle 37era toa ne mo ree pee Tt oe am Rm eo aN NMR nbd ics AV/A/B AO/SCC//IDMA ANTACK (Status) RW 0s ADO-AD15 MAITIIRDY (Wait) WAITIIRDY (Ready) Figure 32. Non-multipiexed /DS Read Cycle Ten Eat0 0 ics AVA/B " AO/SCC//DMA @ L@ ie x ANTACK (Status) / RW \ A Nom X 2 <i-f] bt 21 cxcr /DS NL # ) >i 5) (1) WP ADO-AD15 MAIT//RDY (Walt) MWATT//RDY (Ready) Figure 33. Non-multiplexed /DS Write Cycle pepe PRIS 39AI/A/B , A0/SCC//DMA &) /INTACK F (Status) / tt (57) __7 RD N 7 A < (2) > a (7) ~ Oy, ADO-AD15 \t X. g @ ae el O MWAIT/RDY . (Wai) NWAIT/RDY (Ready) / ike ) = Figure 34. Non-multiplexed /RD Read CycleAAS AQ/SCC//DMA 4 stans) 7 \ ON ON ADO-AD15 ) | MAITIIRDY (Wak) (1) IWAIT//RDY ) ! e (Ready) Figure 35. Non-multiplexed /WR Write Cycle 41 CREE2 a eae Oe et NRE ee men eine we oe meen and : VO /AS 7 jt (6)-b>| < +i) i ANTACK \ (Status) K Vv 68) tp] | (7) N nV ms \. # \ < (4)- | | ___(5 = aa i Vv ADO-AD15 OM y (18) (49) 8 10 > ' ~(41) MWAITI/RDY os KH e fl 2) @) WAIT//RDY (Wait) IE 5 ( ) } K_ (1) (e2) IEO q P\ (83) tw} (64 ANT J [<+{6)>} Figure 36. Multiplexed /DS Status INTACK Cycle 42/AS / <a (1) wa \ ILE @->| > 47) a f N mp N 7 \ < > <)> ADO-AD15 d @) ) 8 PG g . 5 Sie! >) MWAIT//RDY (Ready) (28) WAITT/IRDY (Wait) (04) (95) (68) IEl K. {EO ( \ @++1 b+e ANT A (33) Figure 37. Multiplexed /RD Status INTACK Cycle 43/AS ANTACK (Pulsed) ADO-AD15 q MAITIRDY (Ready) MWAITRDY (Wait) eo (EI X. {EO q ANT Figure 38. Multiplexed Pulsed INTACK Cycle 2 ree, see ee ke AR@ AINTACK ON (Status) v V <@>| a ms N # \ < (ay wm! be ()__> o - ADO-AD15 MM jf 8 (10 > =H MWATTIIRDY (Ready) ike 8) J WAIT//IRDY (Walt) (08) (37) (68) ie 1El x q ) A. 4 A ANT / Figure 39. Non-multiplexed /DS INTACK Cycle 45pune ant taro a ae ce. Teer CO EEE ANTACK oN (Status) RO \ iv ADO-AD15 4 Mt MWAITIIRDY (Ready) MAITADY (Wait) _# TS ) K IEO ( \ ANT J Figure 40. Non-multiplexed /RD Status INTACK Cycle 46/INTACK N J (Pulsed) {1} VY Uv ADO-AD15 E y MWAITIRDY (Ready) WAIT//RDY (Wait) IE IE \ ANT J Figure 41. Non-multiplexed Pulsed INTACK Cycle 47 |ce co 3 | 819AD HOV_LNI @SINd-81qnog pexaidiinw zy esnBi4 x a <Gs) el $1} ~ Loafni)- VY (em) AQW/LIVAV e+ a) ____ | (kpeeu) AQd/LIVA Ts a @)- I Q | ~ tre [t+ La) B. ; = a Siav-oay ~@- -______- . @+} |e -@- ma / N f 5 (esing-2) kK 7 MOWLNY SN J aa $v SPARRO Se AEE eg49 81949 MOV_LNI @SiNdg-21GN0g paxeidyinw-uON ep einBl4 et F, (em) i AQH//LIVAY . (Apeey) i AQHLIVW i Sldv-odv (esing-z) OVNI3 Le 2 Figure 44. Reset Re ee ste ae Se RE OA TI oe Ae Ee +) 6 TR Tso Ts To 11 rm Nf \_L\N_F NS /UAS / tT -(116 : IAS / le 1 (DS / | He | ; PUN / : y 6 mre | IRD / Oo | ; al (6 A1,AO < <6 AD15-0 < <=-- muSREQ | | /BUSACK ON Y G4 Hi) ) @ Figure 45. Z16C35 Start-up 51AS RW At, Ao ADI5.0 AWak/IRDY (Wak) MWakiROY (Ready) /BUSACK Figure 46. Z16C35 Memory Read 52 eM ARN NEN UMN REM NEN TINpp SLOSS LSE LEVI as LS Ny (130) RW At, AO AD15-0 Malt/RDY (Ready) Wak//RDY (Walt) /BUSACK Figure 47. Z16C35 Memory Write 53K / @ \ @ Figure 48. Wait and Ready Timing / @ \ @cai UAS JAS /DS RW /RD WR Ai, AO AD15-0 , y @ | | 2 WE | A d Figure 49. BUS Release 55AC CHARACTERISTICS QQ 10MHz * No Symbol Parameter Min Max Notes 1 TsRXD(RXCr) RxD to /(RxCT Setup Time (x1 mode) 0 [1] 2 ThRXD(RXCr) RxD to /RxCT Hold Time (x1 mode) 150 [1] 3 TsRXD(RXCf) RxD to /RxCL Setup Time (x1 mode) QO [1,5] 4 ThRXD(RXCf) RxD to /RxCL Hold Time (x1 mode) 150 {1,5} 5 TsSY(RXC) ISYNC to /RxCT Setup Time -200 [1] 6 ThSY(RXC) ISYNC to RxCT Hold Time 5TcPc {1} 7 TsTXC(PC) [TxC to PCLK Setup Time 0 [2,4] 8 TATXC(TXD) {TxCl to TxD Delay (x1 mode) 150 [2] 9 TdTxCr(TXD) TxCT to TxD Delay (x1 mode) 150 [2,5] 10 TdTXD(TRX) TxD to /TRXC Delay (Send Clock Echo) 200 1 TwRTXh /RTxC High Width 150 [6] 12 TwRTXI /RTxC Low Width 150 [6] 13 TcRTX /RTxC Cycle Time (RxD, TxD) 400 [6,7] 14 TcRTXX Crystal Oscillator Period 100 1000 [3} 15 TwIRXh /TAxC High Width 150 [6] 16 TwTRxXl /TRxC Low Width 150 [6] 17 TcTRX /TRxC Cycle Time (RxD, TxD) 400 [6,7] 18 TwWEXT /DCD or /CTS Pulse Width 200 19 TwSY /SYNC Pulse Width 200 * Units in nanoseconds. Notes: [1] /RXxC is /RTxC or /TRxC, whichever is supplying the receive clock. {2] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock. {3] Both /RTxC and /SYNC have 30 pf capacitors to ground connected to them. [4] Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between /RxC and PCLK or/TxC and PCLK is required. [5] Parameter applies only to FM encoding/decoding. [6] Parameter applies onty for transmitter and receiver; DPLL and baud rate generator requirements are identical to case PCLK requirements. [7] The maximum receive or transmit data rate is one-fourth PCLK. 56ARTxC, /TRxC (Receive) RxD TRxC, RTxC (Transmit) TxD (Input) Figure 50. Z16C35 General Timing 57stintabnaal ain lapinKeds- Suits AC CHARACTERISTICS System Timing 10MHz No Symbol Parameter Min Max Notes + 1 TdRXC(SY) IRxCT to /SYNC 4 7 1 TdRXC(INT) RxCT to /INT Valid Delay 10 16 1 3 TdTXC(INT) [TxCL to /INT Valid Delay 6 10 4 TdSY(INT) /SYNC Transition to /INT Valid Delay 2 6 5 TdEXT(INT) [DCD or /CTS Transition to /INT Valid Delay 2 6 t Units equal to TcPc. Notes: , 1. (AXC is (RTXC or /TRxC, whichever is supplying the receive clock. 2. [TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.IATxC, /TRxC (Receive) {SYNC (Output) ANT IRTxC, /TRxC (Transmit) ANT CTS, (OCD SYNC (Input) ANT Figure 51. Z16C35 System Timing 59 a,EE RCP IN Copa Ctra sangeet te tte TESS we ig et PACKAGE INFORMATION C 8 045 X 45MAX 2010 X 45 MAX 3 PL _- x + 4 4. 7p J H 028 qat 3D 3-002 q t D gas OA 3p +390 ad. D 6953. 010 gee pg 4b 4.003 q re qs? q 6D) qsa D os q . sy ( qat D d B20) G43 D 4 4 846) 6061] 53 55 87 so Wwouutd vouyuvuuuuusa. we . $53 4.003: - 7 & 990 4.010 a 045 x 45 S NOMINAL Te Lo tt. 0231403} o.. O18 t.002 -926 toto DIMENSION FROM LOWEST POINT TO LOWEST POINT OF J LEADS. 68-Lead Plastic Chip Carrier 60ORDERING INFORMATION Z16C35 ISCC 10 MHz 68-Pin PLCC Z16C3510VSC CODES PACKAGE ENVIRONMENTAL Preferred Preferred V = Plastic Chip Carrier C = Plastic Standard E = Hermetic Standard Longer Lead Time F = Plastic Quad Flat Pack Longer Lead Time G = Ceramic PGA (Pin Grid Array) D = Plastic Stressed L = Ceramic LCC Q = Ceramic Quad-in-Line TEMPERATURE Preferred S$ = 0C to +70C Longer Lead Time E = -40C to +85C Example: Z16C3510VSC 16C35, 10MHz, Plastic PLCC, 0C to 70C, Plastic Standard Flow Z 16035 10 V S C | L__. Environmental Flow Temperature Package Speed Product Number Zilog Prefix 61Soe FO I EA VEN rete Sine ZILOG DOMESTIC SALES OFFICES AND TECHNICAL CENTERS CALIFORNIA AQOULE noes e cece cteteeteeecesteseeteeesestereaees 818-707-2160 CAMPDEll 0... cceccrccceeseeseeeeeeessteseesccesenees 408-370-8120 TUSUIN oo eee ccc ceneccesenseeecescesstnnueveveaveeas 714-838-7800 COLORADO BOUIGEE ooo eee cece cetececeestesececctstcnseeseeens 303-494-2905 FLORIDA LAT QO ooo eee ec eceeeeteeeesetesstsesesscsesscseessaeess 813-585-2533 GEORGIA NOPCIOSS 00... eececcsccsseeceteeteceetsesertatesenees 404-448-9370 ILLINOIS SCNAUMDULG 0.0... ceeeccesccesesesesestetetetsesteees 708-5 17-8080 NEW HAMPSHIRE NASNUA oo... eee ccceecececcsctsteseeeerssereneees 603-888-8590 NEW JERSEY CLK ooo ceeetecteesetessensescsscesecnscstesasenssente 201-382-5700 NORTH CAROLINA RAICIQD oo. eeecccc ccc ceeccscesecsesstsetesteneesersees 919-790-7706 OHIO SeVEN Hills oo. ccsccecseccerseereneeeenaes 216-447-1480 PENNSYLVANIA AMIEL ooo. eee e cece cc cccccececcececcetesstsessevae 215-653-0230 TEXAS DAW AS oo cceeteeccsectesseeesessssesvescessesees 214-987-9987 WASHINGTON Seattle occ cesses ccsscscescsecseseenstees 206-523-3591 1990 by Zilog, Inc. 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No patent licenses, industrial property rights, or other rights are implied. 00-2515-03 INTERNATIONAL SALES OFFICES CANADA TOPOMO 00... cecceccccccecceeeeteesesseceseecntseennreeeens 416-673-0634 GERMANY MUNICH 00... ccceececcececesseceeteeeaeeeeeenne 49-89-672-045 JAPAN TOKYO ooeecccececcceeccesessessesecsesecsscessessestaneevaees 81-3-587-0528 HONG KONG KOWIOON 0.0. cece ccc cece ccc cneececcseceeeneeerevesesaee 852-7 238979 KOREA S@OUI oo... eee ccesecccsseccsssersesesueessessecesessenes 82-2-552-5401 SINGAPORE SINQADOLE ose eee eee eeteteeeeeneeeeeeeecteeeteteeetiens 65-2357 155 TAIWAN TAIDOE oo e ec cececsccsesceesecnseesssensasessece 886-2-7 41-3125 UNITED KINGDOM Maidenhead 1.0.0.0... ccc eecccsececeseceenreee 44-628-392-00 Zilog will not be responsible for any damage to the user that may result from accidents or any other reasons during operations of the products described herein. All specifications (parameters) are subject to change without notice. Zilog will not be responsible for any such changes. Zilog will not be responsible for notifying any user of changes. The ap- plicable Zilog test documentation will specify which parameters are tested. Zilog, Inc. 210 Hacienda Ave., Campbell, CA 95008-6609 Telephone (408) 370-8000 TWX 910-338-7621 C) G