COP224C/COP225C/COP226C/COP244C/COP245C National Semiconductor COP224C/COP225C/COP226C/COP244C/COP245C Single-Chip 1k and 2k CMOS Microcontrollers General Description The COP224C, COP225C, COP226C, COP244C and COP245C fully static, Single-Chip CMOS Microcontroilers are members of the COPST family, fabricated using dou- ble-poly, silicon gate microCMOS technology. These Con- troller Oriented Processors are complete microcomputers containing ail system timing, internal logic, ROM, RAM, and I/O necessary to implement dedicated control functions in a variety of applications. Features include single supply oper- ation, a variety of output configuration options, with an in- struction set, internal architecture and I/O scheme de- signed to facilitate keyboard input, display output and BCD data manipulation. The COP224C and COP244C are 28 pin chips. The COP225C and COP245C are 24-pin versions (4 inputs removed) and COP226C is 20-pin version with 15 I/O lines. Standard test procedures and reliable high-density techniques provide the medium to large volume customers with a customized microcontroller at a low end-product cost. These microcontrollers are appropriate choices in many de- manding control environments especially those with human interface. Features @ Lowest power dissipation (600 .W typical) @ Fully static (can turn off the clock) @ Power saving IDLE state and HALT mode @ 4.4 us instruction time @ 2k x 8 ROM, 126 x 4 RAM (COP244C/COP245C) m 1k x 8 ROM, 64 x 4 RAM (COP224C/COP225C/ COP226C) @ 23 1/0 lines (COP244C and COP224C} @ True vectored interrupt, plus restart @ Three-level subroutine stack a Single supply operation (4.5V to 5.5V) @ Programmable read/write 8-bit timer/event counter g nternal binary counter register with MICROWIRET serial |/O capability @ General purpose and TAI-STATE outputs m LSTTL/CMOS output compatible @ Software/hardware compatible with COP400 family w@ Military temperature { 55C to + 125C) operation Block Diagram } } Ce cao W 1 3 t T COUNTER + WAL +256 +4 Orvigen centanton CONTROL, DISTRUCTION CLOCK aEsEY a LoGic nent ROM 1024 x8 224C 2088 x 8 2446 nA " 646 2246 on] 00 12042440 aa " Ene 0; C4 a 0 ite 0; 7 c REGIETER Die 93k u A 78 2 tok $A msTRUucTiON be ee ee we DEEODE " _ CARRY 1 " ' aL Of breeds 63 _ ote ee el q a 1 pe $0! aICROWRE 1/0 By Sy 5) ly - SERIAL 1/0 REGITER u MO CONTAOLS ; La -- a ea venom , mciTEN Hog 4 23 | : AUGHTER ots * It. I LORIVERS 4 7 un $F au. 4 fox +> 2 & & | r | l rele ie fe bie REP Ep * Not available on COP226C Wy IMy My I by Lp te te bp bg br te TL/DOD/8422-1 FIGURE 1 1-20Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. 55C to + 126C 65C to + 150C Operating Temperature Range Storage Temperature Range Supply Voltage (Vcc) Voltage at any Pin Total Allowable Source Current Total Allowable Sink Current Total Adowable Power Dissipation 0.3V to Voc + 0.3V Lead Temperature ev (soldering, 10 seconds) 25 mA 25 mA 150 mW vice at absolute maximum ratings. 300C Note: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electri- cal specifications are not ensured when operating the d- DC Electrical Characteristics -ssc<t,< +125c, +4.5V<Vocs +5.5V unless otherwise specified Parameter Conditions Min Max Units Operating Voltage 45 5.5 Vv Power Supply Ripple (Note 5} Peak to Peak 0.25 Voc Vv Supply Current Voc= 5.0V, tc=4.4 ps 5 mA (Note 1) (tc is instruction cycle time) HALT Mode Current {Note 2) Voc= 5.0V, Fin=0 kHz 200 pA Input Voltage Levels AESET, CKI, Dg (clock input) Logic High 0.9 Voc Vv Logic Low 0.1 Voc v All Other inputs Logie High 0.7 Voc Vv Logic Low 0.2 Vcc v Hi-Z Input Leakage 10 +10 pA Input Capacitance (Note 4) 7 pF Output Voltage Levels (except CKO) Standard Outputs LSTTL Operation Vec=5.0V+ 10% Logic High lon= 100 A 27 Vv Logic Low lol = 400 pA 0.6 Vv CMOS Operation Logic High loH= 10 pA Voco0.2 Vv Logic Low loL= 10 pA 0.2 Vv CKO Current Levels (As Clock Out} Sink +4 0.2 mA +8 CKI=Vec, Vout= Voc 0.4 mA +16 0.8 mA Source +4 -0.2 mA +8 CKI= OV, VouT=9V ~0.4 mA +16 0.8 mA Allowable Sink/Source Current per Pin 5 mA (Note 6) Allowable Loading on CKO (as HALT} 50 pF Current Needed to Over-Ride HALT (Note 3) To Continue Vin =9.2 Vcc 2.0 mA To Halt Vin =0.7 Voc 3.0 mA TRI-STATE or Open Drain Leakage Current 10 +10 pA 1-21 DSPZdOD/DHHedOD/D97T7dOID/DS27%dO9/DPezedO9COP224C/COP225C/COP226C/COP244C/COP245C AC Electrical Characteristics ssc<t,< + 125C, +4.5V<Voc< +5.5V unless otherwise specified. Parameter Conditions Min Max Units Instruction Cycle Time (te) 4.4 DC ps Operating CKI +4 mode DC 0.9 MHz Frequency +8 mode DC 1.6 MHz +16 mode oc 3.6 MHz Duty Cycle (Note 4) fy = 3.6 MHz 40 60 % Rise Time (Note 4) fy =3.6 MHz External Clock 60 ns Fall Time (Note 4) ft, =3.6 MHz External Clock 40 ns Instruction Cycle Time R=30k +5% RC Oscillator (Note 4) C=82 pF +5% (+4 Mode) 6 18 ps Inputs: (See Figure 7) (Note 4) tsETUP G inputs tce/4+0.8 ps SI Input 0.33 us All Others 1.9 ys tHOLD 0.4 ps Output Propagation Delay Vout = 1.5V, G_= 100 pF, RL=5k tep1 tppo 1.4 Bs Note 1: Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI, CKO open, and all other pins pulled up to Voc with 5k resistors. See current drain equation on page 13. Note 2: The HALT mode will stop CKi from oscillating in the RC and crystal configurations. Test conditions: all inputs tied to Vcc, L lines in TRI-STATE mode and tied to ground, all outputs low and tied to ground. Note 3: When forcing HALT, current is only neaded for a short time {approx. 200 ng) to flip the HALT flip-fiop. Note 4: This parameter is not tested but guaranteed by design. Variation due to the device included. Note 5: Voltage change must be jess than 0.25 volts in a 1 ms period. Note 6: SO output sink current must be limited to keep Vo, less than 0.2 Voc when part is running in order to prevent entering test mode. 1-22Connection Diagrams S.0. Wide and DIP $.0. Wide and DIP CKi =a] 2 19 == 02 RESET =a 3 18/3 L7 wound] 4 17 ae 63 LG oo 16} 62 COoP226C. U5 omy 15 foe SK L mooll 7 14 f 50 Vcc wall 8 13 I SI L3=4 9 12 f= LO L2 =a 10 NIL Top View TL/DD/6422-2 Order Number COP226C-XXX/N See NS Molded Package Number N20A Order Number COP226C-XXX/D See NS Hermetic Package Number D20A Order Number COP226C-XXX/WM See NS Surface Mount Package Number M20B DIP OND 1 28 = 00 CKO | 2 27 ) 1 cu 43 26 F 02 WESET ] 4 25 = 03 LT 15 24 63 L6 "7 6 23 - 42 L617 = copzzag 22 fo 1 taja = COPZAAG ys b cy Imi 19 20 IN3 In2 =I 10 19 mo Veo = O01 er SK L3 ] 12 17 30 2 7 13 er si Li] 15 fF Lo Top View TL/DD/8422-4 Order Number COP224C-XXX/N or COP244C-XXX/N See NS Molded Package Number N28B Order Number COP224C-XXX/D or COP244C-XXX/D See NS Hermetic Package Number D28C GND ] 1 24 a DO CKO =m 2 23 fame 11 cxt 4 3 22 f pz ESET ] 4 21 03 T45 20 63 6 4| 6 COP226C 19 = G2 ti _ 7 | COP245C ag Le Gy use 17 == 60 Vcc "19 16 Fe SK L3 1 10 15 so L2 4 11 4 sI ui 12 13 = Lo Top View TL/DD/8422-3 Order Number COP225C-XXX/N or COP245C-XXX/N See NS Molded Package Number N24A Order Number COP225C-XXX/D or COP245C-XXX/D See NS Hermetic Package Number D24C + D3 G3 G2 GI GO IN3 INO La | ed 3358 % TL/OD/8422-13 Order Number COP224C-XXX/V or COP244C-XXX/V See NS PLCC Package Number V28A FIGURE 2 1-23 IS2dOO/DPZdO9/D9Z7d09/9S%7d09/DrzzdO9COP224C/COP225C/COP226C/COP244C/COP245C Pin Descriptions Pin Description Pin Description L7-LO 8-bit bidirectional SK Logic controlied port with TRI-STATE clock output G3-GO0 4-bit bidirectional CKI Chip oscillator input 1/0 port CKO Oscillator output, D3-Do 4-bit output port HALT I/O port or INS-ING 4-bit input port general purpose input (28 pin package onty) RESET Reset input Si Serial input or Voc Most positive counter input power supply so Serial or general GND Ground purpose output Functional Description The internal architecture is shown in Figure 1. Data paths are illustrated in simplified form to depict how the various logic elements communicate with each other in implement- ing the instruction set of the device. Positive logic is used. When a bit is set, it is a logic 1, when a bit is reset, it is a logic 0. Caution: The output options available on the COP224C/225C/226C and COP244C/245C are not the same as those available on the COP324C/325C/326C, COP344C/345C, COP424C/ 425C/426C and COP444C/445C. Options not available on the COP224C/225C/226C and COP244C/245C are: Option 2 value 2: Option 4 value 0; Option 5 value 1; Option 9 value 0: Option 17 value 1; Option 30, Dual Clock, all values; Op- tion 32, Microbus, all values; Option 33 values 2, 4, and 6; Option 34 all values; and Option 35 ail values. PROGRAM MEMORY Program Memory consists of ROM, 1024 bytes for the COP224C/225C/226C and 2048 bytes for the COP244C/ 245C. These bytes of ROM may ba program instructions, constants or ROM addressing data. ROM addressing is accomplished by an 11-bit PC register which selects one of the 6-bit words contained in ROM. A new address is loaded into the PC register during each in- struction cycle. Unless the instruction is a transfer of contro! instruction, the PC register is loaded with the next sequen- tial 11-bit binary count value. Three levels of subroutine nesting are implemented by a three level deep stack. Each subroutine call or interrupt pushes the next PC address into the stack. Each return pops the stack back into the PC register. DATA MEMORY Data memory consists of a 512-bit RAM for the COP244C/ 245C, organized as 8 data registers of 16 x 4-bit digits. RAM addressing is implemented by a 7-bit B register whose upper 3 bits (Br) select 1 of 6 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. Data memory consists of a 256-bit RAM for the COP224C/ 225C/226C, organized as 4 data registers of 16 x 4-bits digits. The B register is 6 bits long. Upper 2 bits (8r) select 1 of 4 data registers and lower 4 bits (Bd) select 1 of 16 4-bit digits in the selected data register. While the 4-bit contents of the selected RAM digit (M) are usually loaded into or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the Q latches or T counter or loaded from the L ports. RAM addressing may also be performed directly by the LDD and XAD instructions based upon the immediate operand field of thase instructions. The Bd register also serves as a source register for 4-bit data sent directly to the D outputs. INTERNAL LOGIC The processor contains its own 4-bit A register (accumula- tor) which is the source and destination register for most I/O, arithmetic, logic, and data memory access operations. It can also be used to load the Br and Bd portions of the B regis- ter, to load and input 4 bits of the 8-bit Q latch or T counter, to input 4 bits of L I/O ports data, to input 4-bit G, or IN ports, and to perform data exchanges with the SIO register. A 4-bit adder performs the arithmetic and logic functions, storing the results in A. It also outputs a carry bit to the 1-bit C register, most often employed to indicate arithmetic over- flow. The G register in conjunction with the XAS instruction and the EN register, also serves to control the SK output. The 8-bit T counter is a binary up counter which can be loaded to and from M and A using CAMT and CTMA instruc- tions. This counter may be operated in two modes depend- ing on a mask-programmable option: as a timer or as an external event counter. When the T counter overflows, an 1-24Functional Description (continued) overflow flag will be set (see SKT and IT instructions below). The T counter is cleared on reset. A functional block dia- gram of the timer/counter is illustrated in Figure 7. Four general-purpose inputs, IN3-INOQ, are provided. The D register provides 4 general-purpose outputs and is used as the destination register for the 4-bit contents of Bd. The G register contents are outputs to a 4-bit general-pur- pose bidirectional I/O port. The Q register is an internal, latched, 8-bit register, used to hold data loaded to or from M and A, as well as 8-bit data from ROM. Its contents are outputted to the L I/O ports when the L drivers are enabled under program control. The 8 L drivers, when enabled, output the contents of latched Q data to the L 1/0 port. Also, the contents of L may be read directly into A and M. The SIO register functions as a 4-bit serial-in/serial-out shift register for MICROWIRE t/O and COPS peripherals, or as a binary counter (depending on the contents of the EN regis- ter). Its contents can be exchanged with A. The XAS instruction copies C into the SKL latch. In the counter mode, SK is the output of SKL; in the shift register mode, SK outputs SKL ANDed with the clock. EN is an internal 4-bit register loaded by the LEI instruction. The state of each bit of this register selects or deselects the particular feature associated with each bit of the EN regis- ter: 0. The least significant bit of the enable register, ENO, se- lects the SIO register as either a 4-bit shift register or a 4-bit binary counter. With ENO set, SIO is an asynchro- nous binary counter, decrementing its value by one upon each low-going pulse (1 to 0") occurring on the SI input. Each pulse must be at least two instruction cycles wide. SK outputs the value of SKL. The SO output equals the value of EN3. With ENO reset, SID is a serial shift register left shifting 1 bit each instruction cycle time. The data present at SI goes into the least significant bit of SIO. SO can be enabied to output the most significant bit of SIO each cycle time. The SK outputs SKL ANDed with the instruction cycle clock. 1. With EN1 set, interrupt is enabled. Immediately following an interrupt, EN1 {s reset to disable further interrupts. 2. With EN2 set, the L drivers are enabled to output the data in Q to the L I/O port. Resetting EN2 disables the L driv- ers, placing the L I/O port in a high-impedance input state. 3. EN3, in conjunction with ENO, affects the SO output. With ENO set (binary counter option selected) SO will output the value loaded into ENS. With ENO reset (serial shift register option selected), setting EN3 enables SO as the output of the SIO shift register, outputting serial shifted data each instruction time. Resetting EN3 with the serial shift register option selected disabies SO as the shift reg- ister output; data continues to be shifted through SIO and can be exchanged with A via an XAS instruction but SO remains set to '0. INTERRUPT The following features are associated with interrupt proce- dure and protocol and must be considered by the program- mer when utilizing interrupts. a. The interrupt, once recognized as explained below, pushes the next sequential program counter address {PC + 1) onto the stack. Any previous contents at the bot- tom of the stack are lost. The program counter is set to hex address OFF (the iast word of page 3) and EN1 is reset. b. An interrupt will be recognized only on the following con- ditions: 1. EN1 has been set. 2. A low-going pulse (1 to 0) at least two instruction cycles wide has occurred on the IN, input. 3. A currently executing instruction has been completed. INSTRUCTION CYCLE TIME -| SK (AS A wa ba G3-Go, t7-ig, y Y CKO & SI INPUTS fen1 | j~ town |< tppp-> G3-Go. D3-Do. t7-Lo, $0, SK i Von Vou OUTPUTS TL/DD/8422-5 FIGURE 3. Input/Output Timing Diagrams (divide by mode) TABLE I. Enable Register Modes Bits ENO and EN3 ENO|EN3|/ SIO sl so SK 0 0 | Shift Input to Shift} O lf SKL=1,SK=clock Register| Register If SKL=0,SK=0 QO 1. | Shit Input to Shift | Serial | lf SKL=1,SK=clock Register| Register out | lf SKL=0,SK=0 1 Q | Binary Input to 0 SK=SKL Counter | Counter 1 1 | Binary Input to 1 SK=SKL Counter | Counter 1-25 DSPZdOD/Db7dO9/D9Z7dOD/DSZ7dO9/DPe7dODCOP224C/COP225C/COP226C/COP244C/COP245C Functional Description (Continued) 4. All successive transfer of contro! instructions and suc- cessive LBIs have been completed (e.g. if the main program is executing a JP instruction which transfers program contrel to another JP instruction, the interrupt will not be acknowledged until the second JP instruc- tion has been executed). c. Upon acknowledgement of an interrupt, the skip logic status is saved and later restored upon popping of the stack. For example, if an interrupt occurs during the exe- cution of ASC (Add with Carry, Skip on Carry) instruction which results in carry, the skip logic status is saved and program control is transferred to the interrupt servicing routine at hex address OFF. At the end of the interrupt routine, a RET instruction is executed to pop the stack and return program control to the instruction following the original ASC. At this time, the skip logic is enabled and skips this instruction because of the previous ASC carry. Subroutines should not be nested within the interrupt service routine, since their popping of the stack will en- able any previously saved main program skips, interfering with the orderly execution of the interrupt routine. d. The instruction at hex address OFF must be a NOP. e. An LEI instruction may be put immediately before the RET instruction to re-enable interrupts. INITIALIZATION The internal reset logic will initialize the device upon power- up if the power supply rise time is less than 1 ms and if the operating frequency at CKI is greater than 32 kHz, other- wise the external RC network shown in Figure 4 must be connected to the RESET pin (the conditions in Figure 4 must be met). The RESET pin is configured as a Schmitt trigger input. if not used, it should be connected to Vcc. Initialization will occur whenever a logic 0 is applied to the RESET input, providing it stays low for at least three instruc- tion cycle times. Note: If CKI clock is less than 32 kHz, the internal reset logic (option #29 = 1) MUST be disabled and the externa! RC circuil must be used. <r eVeMm wNSsov ____> + pg 3 Bs RC>5X POWER SUPPLY RISE TIME AND RC>100X CKI PERIOD. TL/OD/8422-6 FIGURE 4. Power-Up Circult Upon initialization, the PC register is cleared to 0 (ROM ad- dress 0) and the A, B, C, D, EN, IL, T and G registers are cleared. The SKL latch is set, thus enabling SK as a clock output. Data Memory (RAM) is not cleared upon initializa- tion. The first instruction at address 0 must be a CLRA (clear A register). TIMER There are two modes selected by mask option: a. Time-base counter. In this mode, the instruction cycle fre- quency generated from CKI passes through a 2-bit divide- by-4 prescaler. The output of this prescaler increments the 8-bit T counter thus providing a 10-bit timer. The pre- scaler is cleared during execution of a CAMT instruction and on reset. For example, using a 3.58 MHz crystal with a divide-by-16 option, the instruction cycle frequency of 223.70 kHz in- crements the 10-bit timer every 4.47 is. By presetting the counter and detecting overflow, accurate timeouts be- tween 17.88 ys (4 counts) and 4.577 ms (1024 counts} are possible. Longer timeouts can be achieved by accu- mulating, under software control, multiple overflows. b. External event counter. In this mode, a low-going pulse (1 to 0) at least 2 instruction cycles wide on the IN2 input will increment the 8-bit T counter. Note: The IT instruction is not allowed in this mode. A CKI cxo A R2 7 AAA vvv Sir HALT eee . GENERAL PURPOSE 3 RI CLOS! INPUT | c C2 shes = = cKI cKO rr Vee | : HALT C On = GENERAL PURPOSE INPUT TL/OD/6422-7 Crystal or Resonator Crystal Component Values Value R1 R2 | CtpF) | c2(pF) 32 kHz 220k 20M 30 6-36 455 kHz 5k 10M 80 40 2.096 MHz 2k 1M 36 6-36 3.6 MHz 1k 1M 30 6-236 RC Controlled Oscillator Cycle R c Time Vec 30k 82 pF 6-18 ps 24.5V Note: 15k<R< 150k 50 pF << 150 pF FIGURE 5. Oscillator Component ValuesFunctional Description (continued) HALT MODE The COP244C/245C/224C/225C/226C is a FULLY STAT- IC circuit; therefore, the user may stop the system oscillator at any time to halt the chip. The chip may also be halted by the HALT instruction or by forcing CKO high when it is mask-programmed as a HALT I/O port. Once in the HALT mode, the internal circuitry does not receive any clock sig- nal and is therefore frozen in the exact state it was in when halted. All information is retained until continuing. The chip may be awakened by one of two different methods: Continue function: by forcing CKO low, if it mask-pro- grammed as a HALT I/O port, the system clock is re-en- abied and the circuit continues to operate from the point where it was stopped. * Restart: by forcing the RESET pin low (see Initializa- tion). The HALT mode is the minimum power dissipation state. CKO PIN OPTIONS a. Two-pin oscillator(Crystal}. See Figure 6a. In a crystal controlled oscillator system, CKO is used as an output to the crystal network. The HALT mode may be entered by program control (HALT instruction) which forces CKO high, thus inhibiting the crystal network. The circuit can be awakened only by forcing the RESET pin to a logic O (restart). b. One-pin oscillator(RC or external). See Figure 6b. if a one-pin oscillator system is chosen, two options are available for CKO: CKO can be selected as the HALT !/O port. In that case, it is an 1/0 flip-flop which is an indicator of the HALT status. An external signal can over-ride this pin to start and stop the chip. By forcing a high level to CKO, the chip will stop as soon as CKI is high and CKO output will stay high to keep the chip stopped if Block Diagram CKi HALT INSTRUCTION the external driver returns to high impedance state. By forcing a low level to CKO, the chip will continue and CKO will stay low. As another option, CKO can be a general purpose in- put, read into bit 2 of A (accumulator) upon execution of an INIL instruction. OSCILLATOR OPTIONS There are three basic clock oscillator configurations avail- able as shown by Figure 5. a. Crystal Controlled Oscillator. CKI and CKO are connect- ed to an external crystal. The instruction cycle time equals the crystal frequency optionally divided by 4, 8 or 16. b. External Oscillator. The external frequency is optionally divided by 4, 8 or 16 to give the instruction cycle time. CKO is the HALT 1/O port or a general purpose input. c. AC Controlled Oscillator. CKI is configured as a single pin RG controlled Schmitt trigger oscillator. The instruction cycle equals the oscillation frequency divided by 4. CKO is the HALT 1/0 port or a general purpose input. Figure 7 shows the clock and timer diagram. COP245C AND COP225C 24-PIN PACKAGE OPTION If the COP244G/224C is bonded in a 24-pin package, it be- comes the COP245C/225C, illustrated in Figure 2, Connec- tion diagrams. Note that the COP245C/225C does not con- tain the four general purpose IN inputs (INS-INO). Use of this option precludes, of course, use of the IN options, inter- tupt feature, external event counter feature. Note: If user selects the 24-pin package, options 9, 10, 19 and 20 must be selected as a 2. See option list. COP226C 20-PIN PACKAGE OPTION If the COP225C is bonded as 20-pin device it becomes the COP226C. Note that the COP226C contains all the COP225C pins except Dp, Dy, Gg, and Gj. CKO nomenmge FQ) CLOCK GENERATOR TL/DD/8422-8 FIGURE 6a. Halt ModeTwe-Pin Oscillator IShZdOD/DHFHedOD/D9Z7dOD/DSeedO39/DvezdO9COP224C/COP225C/COP226C/COP244C/COP245C Block Diagrams (Continued) HALT INSTRUCTION } vec HALT 1/0 PORT = INPUT TO ACCUMULATOR Oana RESET LaTcH RUN EWABLE on TO CLOCK GENERATOR TL/DD/8422-9 FIGURE 6b. Halt ModeOne-Pin Oscillator INg if osciiLaroa +? +? V TIMER :. FL 2 tp a HALT +4 +16 T COUNTER INSTRUCTION +4 crcie clock 4 LE (T gs Q [* TL/DD/8422-10 FIGURE 7. Clock and Timer 1-28instruction Set Table II is a symbol table providing internal architecture, in- struction operand and operation symbols used in the in- Instruction Operand Symbols struction set table. d 4-bit operand field, 0-15 binary (RAM digit select) TABLE Hi. Instruction Set Table Symbols r 3(2)-bit operand field, 0-7(3) binary Symbot | Definition (RAM register select) a 11-bit operand field, O-2047 (1023) Internal Architecture Symbols y 4-bit operand field, 0-15 (immediate data) A 4-bit accumulator RAM(x) RAM addressed by variable x B 7-bit RAM address register (6-bit for COP224C) ROM(x) ROM addressed by variable x Br Upper 3 bits of B (register address) (2-bit for COP224C) Bd Lower 4 bits of B (digit address) Operational Symbols c {-bit carry register + Plus D 4-bit data output port - Minus EN 4-bit enable register Replaces G 4-bit general purpose I/O port < Is exchanged with IL two 1-bit (INO and iN3} latches = is equal to iN 4-bit input port A Ones complement of A L 8-bit TRI-STATE I/O port Exclusive-or M 4-bit contents of RAM addressed by B : Range of values PC 11-bit ROM address program counter Table III provides the mnemonic, operand, machine code Q 8-bit latch for L port data flow, skip conditions and description of each instruc- SA,SB,SC ! 11-bit 3-ievel subroutine stack tion. SIO 4-bit shift register and counter SK Logic-controlled clock output SKL 1-bit latch for SK output T 8-bit timer TABLE Ili. COP244C/245C Instruction Set Machine Hex Language Skip Mnemonic Operand Code Code Data Flow Conditions Description (Binary) ARITHMETIC INSTRUCTIONS ASC 30 0011 | 0000 A+C+RAM(B) > A Carry Add with Garry, Skip on Carry > C Carry ADD 31 0011 | 0001 A+RAM(B) A None Add RAMto A ADT 4A 0100/1010 At10i9 7A None Add Ten to A AISC y 5- o101| y AtyA Carry Add Immediate. Skip on Carry (y # 0) CASG 10 0001 | co00 A+RAM(B})+C > A Carry Complement and Add with Carry ~> C Carry, Skip on Carry CLRA 00 0000 | 0000 O>A None Clear A COMP 40 0100] 0000 AA None Ones complement of A to A NOP 44 0100 | 0100 None None No Operation AC 32 0011 |0010 ov > C None Reset C sc 22 0010/0010 woe None Set C XOR 02 0000/0010 A@RAM(B) A None Exclusive-OR RAM with A ISPEdOI/IbPTdOD/99ZZdO9/IS77dOD/DPeedOOCOP224C/COP225C/COP226C/COP244C/COP245C Instruction Set (continues) TABLE IH. COP244C/245C Instruction Set (Continued) Machine Hex Language Skip Mnemonic Operand Code Code Data Fiow Conditions Description (Binary) TRANSFER CONTROL INSTRUCTIONS JID FF 1411/1111 ROM (PC10.3 AM) > PC7. None Jump Indirect (Notes 1, 3) JMP a 6 0110/0 |ajos8 aPC None Jump -- 47.0 JP a {1 ago | a PCE None Jump within Page (Note 4) (pages 2, 3 only) or -- 11 | as. a-> PC5.0 (all other pages) JSRP a -- 10 | a5-9 PC+1->SASBSC None Jump to Subroutine Page 00010 PCio.5 (Note 5) a PC5.9 JSR a 6- 10110! 1 | aio-8 PC+1->SASB--SC_ None Jump to Subroutine -- a7:0 a-> PC RET 48 0100 1000 Sc SB SA> PC None Return from Subroutine RETSK 49 0100/1004 SC SB SA PC Always Skip Return from Subroutine on Return then Skip HALT 33 0011 [0011 None HALT Processor 38 0011 | 1000 IT 33 0011 | 0011 IDLE till Timer 39 0011 | 1001 None Overfiows then Continues MEMORY REFERENCE INSTRUCTIONS CAMT 33 0011/0011 A Tr-4 3F 0011 | 1141 RAMI(B) T3-0 None Copy A, RAM to T CTMA 33 0011/0011 T7.4 RAM(B) 2F 0040/4111 T3.9 > A None Copy T to RAM, A CAMQ 33 0011|0011 A> Qrz4 None Copy A, RAM to @ 3C 0011 | 1100 RAM(B) Q3:9 CQMA 33 0011/0011 Q7.4 > RAMIB) None Copy Q to RAM, A 2c {0010/1100 Q3:0 2 A LD r -5 00 |r |0101 RAM(B) A None Load RAM into A, (r=90:3) Br@r > Br Exciusive-OR Br with r LDD rd 23 (G010|0011 RAM(r,d)} A None Load A with RAM pointed = O(r| d to directly by r,d LQID BF 1011 | 1111) ROM(PC}0-8,A,M) Q@ None Load @ Indirect (Note 3) SB -> SC RMB oO 4 0100 | 1100) 0 > RAMEB)o None Reset RAM Bit 1 45 0100 | 0101 | 0 RAM(B), 2 42 0100/0010 0 RAM(B)> 3 43 0100/0011 0 RAM(B)3 SMB 0 4D [0100 | 1104 1-> RAM(B)p None Set RAM Bit 1 47 [0100/0111 1 RAM(B), 2 46 [9100|0110 1 RAM(B)o 3 4B {0100| 10114 1 RAM(B)3 1-30Instruction Set (Continued) TABLE Ill. COP244C/245C Instruction Set (Continued) Machine Hex Language Skip Mnemonic Operand Code Code Data Fiow Conditions Description (Binary) MEMORY REFERENCE INSTRUCTIONS (Continued) STi y 7- o111] y y RAM(B) None Stora Memory Immediate Bd + 1 Bd 1 and Increment Bd xX r -6 00O| r (0110 RAM(B) <> A None Exchange RAM with A, (r=0:3) Bro r Br Exclusive-OR Br with r XAD rd 23 0010/0011 RAM(r,d) <> A None Exchange A with RAM -- ijr| d Pointed to Directly by r,d XDS r -7 OO |r;0111 RAM(B) <> A Bd Exchange RAM with A (r=0:3) Bd-1 Bad decrements and Decrement Bd. Bre r -> Br past 0 Exclusive-OFR Br with r xIS r 4 00 | r [0100] RAM(B) <> A Bd Exchange RAM with A (r= 0:3) Bd+1 8d increments and increment Bd, Br@r Br past 15 Exclusive-OR Br with r REGISTER REFERENCE INSTRUCTIONS CAB 50 0101 | C000 A Bd None Copy A to Bd CBA 4E 0100/1110 Bd A None Copy Bd to A LBI rd - 00 |r| (d-1) rd>B Skip until Load B Immediate with r,d (r=0:3: not a LB (Note 6) d=0,9:15) or 33 0011/0011 -- ij r|d {any r, any d) LEI y 33 0011 |00114 y EN None Load EN Immediate (Note 7) 6- 0110/ y XABR 12 0001 |0010 A< Br None Exchange A with Br (Note 8} TEST INSTRUCTIONS SKC 20 0010 | 0000} c="1" Skip if C is True SKE 21 0010 | 0001 A=RAM(B) Skip if A Equals RAM SKGZ 33 0011 |0011 Gg.o=0 Skip if Gis Zera 21 0010 |0001 (all 4 bits) SKGBZ 33 0011 |0011 1st byte Skip if G Bit is Zero 0 01 0000 | 0001 Gop=0 1 11 0001 |0001 G,=0 2 03 0000/0011 end byte Go=0 3 13 0001 |0011 Gg=0 SKMBZ 0 01 0000 | 0001 RAM{B})=0 Skip if RAM Bit is Zero 1 11 0001 | 0001 RAM{B), =0 2 03 0000 | 0011 RAM(B)2=0 3 13 0001 | 0011 RAM(B)3=0 SKT 41 0100 | 0001 A time-base Skip on Timer counter carry (Note 3) has occurred since ast test 1-31 DSPSdOD/OrFedO9/997T7TdOI/NS77dOD/DeeZdODCOP224C/COP225C/COP226C/COP244C/COP245C Instruction Set (continued) TABLE lil. COP244C/245C Instruction Set (Continued) Machine Hex Language Skip Mnemonic Operand Code Code Data Flow Conditions Description (Binary) INPUT/OUTPUT INSTRUCTIONS ING 33 0011/0011 GA None Input G Ports to A 2A 0010| 1040 ININ 33 {0011/0041 IN>A None Input IN Inputs to A 268 [0010] 1000 (Note 2) INIL 33 [0011 |0011 ILg, CKO,"0", [Lg > A None input IL Latches to A 29 [0010| 1001 (Note 3) INL 33 jeo11 {0011 L7.4 RAM(B) None Input L Ports to RAM,A 2E 0010} 1110 L3:0 > A OBD 33 [0011 | 0011 Bd->D None Qutput Bd to D Outputs 3E [0011/1110 OGi y 33 0617 ;0011 yo aq None Output to G Ports 5- [O101; oy immediate OMG 33 [0011 {0011 RAM(B) > G None Output RAM to G Ports 3A 0011} 1010 XAS 4F [0100] 1111 A< > SIO, C SKL None Exchange A with SIO {Note 3) Note 1: All subscripts for alphabetical symbols indicate bit numbers unless explicitly defined (e.g., 8r and Bd are explicitly defined). Bits are numbered 0 to N where 0 signifies the least significant bit (ow-order, right-most bit). For example, Ag indicates the most significant (left-most) bit of the 4-bit A register. Note 2: The ININ instruction is not available on the 24-pin packages since these devices do not contain the IN inputs. Note 3: For additional information on the operation of the XAS, JID, LOID, INIL, and SKT instructions, see below. Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of pages 2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last word of a page. Note 5: A JSAP transfers program control to subroutine page 2 (0010 is loaded into the upper 4 bits of P). A JSRP may not be used when in pages 2 or 3. JSAP Thay not jump to the last word in page 2. Note 6: LBI is a single-byte instruction if d = 0, 8, 10, +1, 12, 13, 14, or 15. The machine code for the lower 4 bits equals the binary value of the d data minus 1, @.g., to load the lower four bits of B(Bd) with tha value 9 (10012), the lower 4 bits of the LB! instruction equal 8 (10003). To load 0, the lower 4 bits of the LBI instruction should equal 15 (11119). Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a '1 cr O" in each bit of EN corresponds with the selection or deselection of a particular function associated with each bit. (See Functional Description, EN Register.) Note &: For 2K ROM devices, A <> Br (0 > A3). For 1K ROM devices, A <> Br (0,0 Aa, Az). 1-32Description of Selected Instructions XAS INSTRUCTION XAS (Exchange A with SIC) copies C to the SKL latch and exchanges the accumulator with the 4-bit contents of the SIO register. The contents of SIO will contain serial-in/seri- al-out shift register or binary counter data, depending on the value of the EN register. if SIO is selected as a shift register, an XAS instruction can be performed once every 4 instruc- tion cycles to effect a continuous data stream. LQID INSTRUCTION LQID (Load Q Indirect) loads the 8-bit Q register with the contents of ROM pointed to by the 11-bit word PC10:PC8,A,M. LQID can be used for table lookup or code conversion such as BCD to seven-segment. The LOID in- struction pushes the stack (PC + 1 SA SB SC) and replaces the least significant 8 bits of the PC as follows: A PC7:4, RAM(B) PC3:0, leaving PC10, PC9 and PC8 unchanged. The ROM data pointed to by the new ad- dress is fetched and loaded into. the Q latches. Next, the stack is popped (SC SB SA > PC}, restoring the saved value of PC to continue sequential program execu- tion. Since LOID pushes SB > SC, the previous contents ot SC are lost. Note: LOQID uses 2 instruction cycies if executed, one if skipped. JID INSTRUCTION JID (Jump Indirect) is an indirect addressing instruction, transferring program control to a new ROM location pointed to indirectly by A and M. It loads the lower 8 bits of the ROM address register PC with the contents of ROM addressed by the 11-bit word, PC10:8,A,M. PC10,PC9 and PC8 are not affected by JID. Note: JID uses 2 instruction cycles if executed, one if skipped. SKT INSTRUCTION The SKT (Skip On Timer) instruction tests the state of the T counter overflow latch (see internal logic, above), executing the next program instruction if the latch is not set. If the latch has been set since the previous test, the next program instruction is skipped and the latch is reset. The features associated with this instruction allow the processor to gen- erate its own time-base for real-time processing, rather than relying on an external input signal. Note: If the most significant bit of the T counter is a 1 when a CAMT instruc- tion loads the counter, the overflow flag will ba set. The following sampie of codes should be used when loading the counter: CAMT ; load T counter SKT __ ; skip if overflow flag is set and reset it NOP IT INSTRUCTION The IT (idle till timer) instruction halts the processor and puts it in an idle state until the time-base counter overflows. This idle state reduces current drain since all logic (except the oscillator and time base counter) is stopped. iT instruc- tion is not allowed if the T counter is mask-programmed as an external event counter (option #31 = 1). INIL INSTRUCTION INIL {Input IL Latches to A) inputs 2 latches, IL3 and ILO, CKO and 0 into A. The iL3 and ILO latches are set if a low- going pulse (1 to 0") has occurred on the IN3 and INO inputs since the last INIL instruction, provided the input pulse stays low for at least two instruction cycles. Execution of an INIL inputs IL3 and ILO into A3 and AO respectively, and resets these latches to allow them to raspond to subse- quent low-going pulses on the IN3 and INO lines. If CKO is mask programmed as a general purpose input, an INIL will input the state of CKO into A2. If CKO has not been so programmed, a 1 will be placed in A2. AO is input into A1. iL latches are cleared on reset. IL latches are not available on the COP245C/225C, and COP226C. INSTRUCTION SET NOTES a. The first word of a program (ROM address 0} must be a GLRA (Clear A) instruction. b. Although skipped instructions are not executed, they are still fetched from the program memory. Thus program paths take the same number of cycles whether instruc- tions are skipped or executed except for JID, and LOQID. c. The ROM is organized into pages of 64 words each. The Program Counter is a 11-bit binary counter, and will count through page boundaries. If a JP, JSRP, JID, or LQID is the last word of a page, it operates as if it were in the next page. For example: a JP located in the last word of a page will jump to a focation in the next page. Also, a JID or LQID located in the last word of every fourth page (i.e. hex address OFF, 1FF, 2FF, 3FF, 4FF, etc.) will access data in the next group of four pages. Note: The COP224C/225C/226C needs only 10 bits te addrass its ROM. Therefore, the eleventh bit (P10) is ignored. Power Dissipation The lowest power drain is when the clock is stopped. As the frequency increases so does current. Current is also lower at lower operating voltages. Therefore, the user should run at the lowest speed and voltage that his application will al- iow. Tha user should take care that all pins swing to full supply levels to insure that outputs are not loaded down and that inputs are not at some intermediate level which may draw current. Any input with a slow rise or fall time will draw additional current. A crystal or resonator generated clock input will draw additional current. For example, a 500 kHz crystal input will typically draw 100 A more than a square- wave input. An R/C oscillator will draw even more current since the input is a slow rising signal. If using an external squarewave oscillator, the following equation can be used to calculate operating current drain. log =lq+ VX 70x Fi+ Vx 2400 x Fi/Dv where: Ico = chip operating current drain in microamps lg= quiescent leakage current (from curve) Fi=CKI frequency in MegaHertz V=chip Vcc in volts Dv = divide by option selected For example at 5 volts Voc and 400 kHz (divide by 4} loo = 120+ 5 700.44 5 X2400 X0.4/4 Igo = 120+ 140+ 1200= 1460 pA DS2dO9/DPPedOD/D9Z7dOD/ISE7dOD/IPZ7dODCOP224C/COP225C/COP226C/COP244C/COP245C Power Dissipation (continued) If an IT instruction is executed, ihe chip goes into the IDLE mode until the timer overflows. In IDLE mode, the current drain can be calculated from the following equation: lci=Igt VX 70 FI For exampie, at 5 volts Vor and 400 kHz Ici=120+5 70X0.4= 260 pA The total average currant will then be the weighted average of the operating current and the idie current: To Ita = Ico X + Ici x 00 * To+Ti Tot+Ti where: lta=total average current loco = operating current Ici=idle current To=operating time Ti=idle time ole a. Standard Push-Pull Output a Bd . Standard TRI-STATE L Output od d. Open Drain TRI-STATE L Output 1/0 OPTIONS Outputs have the following optional configurations, illustrat- ed in Figure 8: a. Standard A CMOS push-pull buffer with an N-channei device to ground in conjunction with a P-channel device to Vcc, compatible with CMOS and LSTTL. b. Open Drain An N-channel device to ground only, al- lowing external pull-up as required by the users applica- tion. c. Standard TRI-STATE L Output A CMOS output buffer similar to a. which may be disabled by program control. d. Open-Drain TRI-STATE L Output This has the N-chan- nel device to ground only. All inputs have the following option: 8. Hi-Z input which must be driven by the users logic. All output drivers use two common devices numbered 1 to 2. Minimum and maximum current (lout and Vout) curves are given in Figure 9 for each of these devices to allow the designer to effectively use these I/O configurations. Vee Doc b. Open-Drain Output Vcc -o = TL/DD/8422-11 e. Hi-Z Input FIGURE 8. Input/Output Configurations 1-34Power Dissipation (Continued) Minimum Sink Current oa (Except CKO) 2.0 1.0 16 _ 08 g 12 g 0.6 0 10 20 30 40 5.0 6.0 a Vou. (VOLTS) Minimum Source Current 12 (Except CKO) Maximum Quiescent Current 1 10 2.0 30 40 #50 69 4.0 5.0 6.0 You (VOLTS) Veg (VOLTS) TL/DD/8422-12 FIGURE 9. Input/Output Characteristics Option List The COP244C/245C/224C/225C/COP226C + mask-pro- grammable options are assigned numbers which corre- spond with the COP244C/224C pins. The following is a list of options. The options are pro- grammed at the same time as the ROM pattern to provide the user with the hardware flexibility to interface to various 10 components using little or no external circuitry. Caution: The output options available on the COP224C/225C/226C and COP244C/245C are not the same as those available on the COP324G/325C/326C, COP344C/345C6, COP424C/ 425C/426C and COP444C/445C. Options not available on the COP224C/225C/226C and COP244C/245C are: Option 2 value 2; Option 4 value 0; Option 5 value 1; Option 9 value 0; Option 17 value 1; Option 30, Dual Clock, all values; Op- tion 32, Microbus, all values; Option 33 values 2 4, and 6; Option 34 all values; and Option 35 all values. PLEASE FILL OUT THE OPTION TABLE on the next page. Photocopy the option data and send it in with your disk or EPROM. Option 1=0: Ground Pin - no options available Option 2: CKO Pin =0: clock generator output to crystal/resonator =1: HALT I/O port =3: general purpose input, high-Z Option 3: CKI input =0: Crystal controiled oscillator input divide by 4 =1: Crystal controlled oscillator input divide by 6 =2: Crystal controlled oscillator input divide by 16 =4: Single-pin RC controlled oscillator (divide by 4) =5: External oscillator input divide by 4 =6: External oscillator input divide by 8 =7: External oscillator input divide by 16 Option 4: RESET input =1: Hi-Z input Option 5: L7 Driver =0: Standard TRI-STATE push-pull output = 2: Open-drain TRI-STATE output Option 6: L6 Driver {same as option 5) Option 7: L5 Driver {same as option 5) Option 8. L4 Driver (same as option 5) Option 9: IN1 input =1: Hi-Z input, mandatory for 28 Pin Package =2: Mandatory for 20 and 24 Pin Packages Option 10: IN2 input (same as option 9) Option 11=0: Voc Pin no option available Option 12: L3 Driver (same as option 5) Option 13: L2 Driver (same as option 5) Option 14: L1 Driver (same as option 5) Option 15: LO Driver (same as option 5) Option 16: SI input (same as option 4) Option 17: SO Driver =0: Standard push-pull output =2: Open-drain output Option 18: SK Driver (same as option 17) Option 19: INO Input (same as option 9) Option 20: IN3 Input (same as option 9) Option 21: GO I/O Port (same as option 17) Option 22: G1 !/O Port (same as option 17) Option 23: G2 |/O Port (same as option 17) Option 24: G3 1/O Port (same as option 17) Option 25: D3 Output (same as option 17) Option 26: D2 Output (same as option 17) Option 27: D1 Output (same as option 17) 1-35 DGbedOD/DPPedOD/D97Z7dOI/IDS77dOD/DPeTdODCOP224C/COP225C/COP226C/COP244C/COP245C Option List (continued) Option 28: DO Output (same as option 17) Option 29: Internal Initialization Logic =0: Normal operation = 1; No internal initialization logic Option 30=0: No Option Available Option 31: Timer =0: Time-base counter =1: External event counter Option 32=0: No Option Available Option 33: COP bonding. See note. (1k and 2k Microcontroller) =0: 28-pin package =1: 24-pin package (1k Microcontroller only) =3: 20-pin package =5: 24- and 20-pin package Note:If opt. #33=0 then opt #9, 10, 19, and 20 must= 1. If opt. #33=1 then opt. #9, 10, 19 and 20 must=2, and option #31 must=0. If opt. #33=3 or 5 then opt. #9, 10, 19, 20 must=2 and opt. #21, 22, 31 must=0. Option 34=0: No Option Available Option 35=0: No Option Available OPTION DATA OPTION 19 VALUE = IS: INO INPUT OPTION 20 VALUE = 1S: IN3 INPUT OPTION 21 VALUE = IS: GO 1/0 PORT OPTION 22 VALUE = IS: G1 1/0 PORT OPTION 23 VALUE = IS: G2 1/0 PORT OPTION 24 VALUE = IS: G3 YO PORT OPTION 25 VALUE = IS: D3 OUTPUT OPTION 26 VALUE = IS: D2 OUTPUT OPTION 27 VALUE = 1S: D1 OUTPUT OPTION 28 VALUE = 1S: DO OUTPUT OPTION 29 VALUE = IS: INT INIT LOGIC OPTION 30VALUE = ___@ 1S: N/A OPTION 31 VALUE = iS: TIMER OPTION 32VALUE = 09s IS: N/A OPTION 33 VALUE = |S: COP BONDING OPTION 34VALUE = ss IS: N/A OPTION 35VALUE = ___90 IS: N/A Option Table The following option information is to be sent to National along with the EPROM. OPTION DATA OPTION +VALUE= _9.__ 1S: GROUND PIN OPTION 2VALUE = IS: CKO PIN OPTION 3 VALUE = IS: CKI INPUT OPTION 4VALUE= 1 _ 1S: RESET INPUT OPTION 5 VALUE = IS: L7 DRIVER OPTION 6 VALUE = IS: L6 DRIVER OPTION 7 VALUE = IS: L5 DRIVER OPTION 8 VALUE = IS: L4 DRIVER OPTION 9 VALUE = IS: IN4 INPUT OPTION 10 VALUE = IS: IN2 INPUT OPTION 11 VALUE= 0 1S: VCC PIN OPTION 12 VALUE = IS: L3 DRIVER OPTION 13 VALUE = (S: L2 DRIVER OPTION 14 VALUE = iS: L1 DRIVER OPTION 15 VALUE = IS: LO DRIVER OPTION 16VALUE = 1 __ IS: SIINPUT OPTION 17 VALUE = IS: SO DRIVER OPTION 18 VALUE = IS: SK DRIVER 1-36