“The new 0.8
µ
m Standard Cell family from AMI
delivers
superior performance and flexibility
. . . one of
the lowest cost and highest performance 0.8
µ
m standard
cell ASIC products available today . . .
”
■
Designed for 3V, 5V, or 3V/5V mixed supplies
■
205 ps gate delays (fanout = 2)
■
Double and Triple Metal Interconnect; up to 700,000 gate
designs using megacells, ROM, RAM, and logic.
■
Complete package lineup
quad flatpack (QFP), LCC, DIP, grid array . . .
■
Usable megacells
Families of single and dual port RAMs, ROMs,
microprocessors, controllers, datapath functions . . .
■
“Made in America”
engineering, manufacturing, and support
No ‘overseas’ delays to your important questions; we’re
right here, ready to help.
Table of Contents
Features…………………………………………………………………………… 1
AMI8Sx Standard Cell Family Overview …………………………………… 1
Architectural Overview ………………………………………………………… 2
Product Applications…………………………………………………………… 3
ASIC Design Tools and Methodology ……………………………………… 3
The Design Library……………………………………………………………… 5
DC Specifications ……………………………………………………………… 6
Library Cell Selection Guide …………………………………………… 8 - 21
Delay Derating Information …………………………………………………… 22
Packaging ………………………………………………………………………… 23
1
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993
Products and Services
AMI8S Standard Cell Family Overview
Note 1: Compact memory arrays greatly increase gate count on an equivalent gate basis.
Feature Description Comment
Complexity
Up to 700,000 gates
1
Up to 410,000 gates 50% memory, 50% megacell and user defined logic
100% user defined logic
I/O Count
Up to 512 pins
Up to 585 pins Test equipment limit; signal pins only
Die size limit; includes power supply pins
Delay
Time
Internal Gate
169ps (Fanout=1, L=0mm)
205ps (Fanout=2, L=2mm) 2 input NAND gate, T=25
o
C , Vdd=5V
Input Buffer
725ps (Fanout=2, L=2mm) CMOS Input buffer, T=25
o
C , Vdd=5V
Output Buffer
1.17ns (C
L
=15pf) CMOS Output buffer,T=25
o
C , Vdd=5V
Megacells
MG29C01,MG29C10,MG65C02,
MG80C85, MG82Cxx, MGMC51 Functionally compatible with popular standard
designs; soft macrocells allow user modifications
Datapath Synthesizers
xx by yy multipliers, adders, subtracters,
FIFOs, barrel shifters,... See page 5 for complete list and details
Memory Compilers
sync. single port RAM (over 4000 sizes)
sync. dual port RAM (over 2000 sizes)
sync ROM (over 8000 sizes)
asynchronous single port RAM
asynchronous dual port RAM
See page 5 for complete list and details
Under development
Under development
AMI’s “AMI8S” standard cell family continues the AMI
leadership tradition of combining true compact building
block standard cells and megacells with high speed
memory and datapath functions. Using a 0.8
µ
m high
performance CMOS process, the AMI8S product can
off er a lo w er cost alternative to gate array for high v olume
applications.
Features
•
3V, 5V, and combined 3V/5V operation:
Each individ-
ual pad cell can be driven independently b y a 3V or 5V
supply. 3V to 5V and 5V to 3V level shift is available in
the I/O cells. The core can be either 3V f or lo w power or
5V for high speed.
•
Operating Temperature equals -55 to 125
o
C:
Few
competing products allow this range.
•
Excellent performance:
- 310 MHz maximum toggle rate on clocked flip-flops
(T
J
= 135
o
C).
- 205 ps delay (FO=2; l=2mm) for a 2-input NAND
gate.
•
Clock tree generation:
≤ 400
ps clock sk e w (fan out =
3500 at 80 MHz).
•
1 to 8 mA drive per single I/O cell:
Slew rate limiting
available for 8mA drive. Custom configurations for I/O
drive up to 96mA can be supported.
•
JTAG Boundary Scan macro support
•
Cost driven architecture:
- Offers both 2 and 3 level metal interconnect to
provide the lowest user cost for the number of
gates and pads required.
- Compiled memory blocks are compacted pre-
cisely to parameters. No leaf cell overhead.
•
Extensive library for quick design:
- 100% compatible with AMI’s proven ASIC Standard
Library.
•
Wide range of packaging:
Full QFP and LCC line,
DIPs and PGAs, individual die , (ball grid arra y package
under study). Burn-in capability as needed.
•
A utomatic Test Program Generation:
Includes scan
macros (NETSCAN
TM
) for high fault coverage.
•
Full operating voltage range from 2.7V to 5.5V
•
ESD protection > 2kV; latchup > 100mA
•
Power is 3.1
µ
W/MHz/gate (FO=2; VDD=5V)
2
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993
Products and Services
Architectural Overview
Some important elements of the AMI8S standard cell
family are:
• Drawn gate length of 0.8 micron; 2 or 3 level metal
interconnect selectable.
•
[Note 1]
Each cell function is tightly compacted to a
fixed bus height. Cells are then placed in rows allowing
Vdd and Vss supplies to feed through the cells. Since
some functions require more gates than others, their
widths and heights ma y increase to allo w f or the added
gates. Transistor sizes and routing are optimized for
their function, giving a much tighter cell design than
with gate arrays or fixed pad ring embedded array
products.
•
[Note 2]
Rows of cells can be placed adjacently if little
routing is required between them, or largely separated
to allow a large data bus to route through. Tracks of
ROM
BLOCK
RAM
BLOCK
MG29C01
Soft Megacell
NA21
DF101
Individually compacted cells [note 1]
Fixed bus height, variable height
Power pad placement
Routing channel width varies with
local cell routing requirements [note 2]
Megacells and datapath functions
are built from standard library cells [note 4]
Compiled memory blocks are
individually compacted to
minimize area [note 5] Vdd,Vss
as required [note 3]
and width design
unused channels are not lost as in gate array or
embedded array products. For 3 level metal, this
feature can combine with routing over cells to give a
very area efficient design.
•
[Note 3]
P o wer pads are placed as required among I/O
cells and can be placed in corners. Core power can be
either 3V or 5V. Each individual I/O can be powered to
3V or 5V. Operating voltage range is 2.7V to 5.5V.
•
[Note 4]
AMI’s megacells and compiled datapath
functions are soft cells. The y are placed as if part of the
customer defined logic. Full netlists are provided
allowing modification by the customer for his design.
•
[Note 5]
Compiled memory blocks are tightly
compacted to the customers’ defined parameters.
FIGURE 1: STANDARD CELL ARCHITECTURE
3
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993
Products and Services
4
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993
Products and Services
AMI Design Flow (cont)
Working with an AMI design center, the customer is
responsible for capturing and verifying the design using
the AMI ASIC Standard Library. He is also responsible for
creating the test vectors that will eventually serve as the
logical par t of the manufactur ing test. Software aids such
as logic synthesis, megacells, automatic test program
generation, netlist rule check ers, etc. can greatly speed up
this process. (A fault coverage check of the test vector set
is optional and can be done as an additional service.)
When the design is received by the factory, the “Design
Start Package” is reviewed by AMI engineers. This start
package, which is completed by the customer, contains
the device specification, netlist, critical timing paths, and
test vectors. The design is pre-screened on the Enhanced
Design Utilities (EDU) and then resimulated on IKOS,
AMI’s sign-off simulator. The results are compared to the
customer’s simulation from the third-party CAE tool.
Once the design has passed the initial screening it is then
ready for placement and routing. The layout proceeds by
first placing memory and megacells, assigning priority to
critical paths, and designing the distribution and buffer ing
of clocks. Next, the layout is completed with automatic
place-and-route on the balance of the circuit.
After layout has been completed the interconnect data is
extracted from the physical layout to be fed back to the
sign-off simulator for final circuit verification. This post
layout interconnect data can be sent to the customer for
final validation on his simulator. When the post-layout
simulation has been completed and approved by the
customer the design is then released for mask and wafer
fabrication.
The test program is developed in parallel using internal
automatic test program generation software. Prototypes
can then be tested before they are shipped.
Figure 3 outlines a typical software environment when
using third party tools. AMI uses EDIF to speed ports
between various software products.
AMI’s Enhanced Design Utilities Tools are intended to be
used interactively at each stage of the design. EDU
software is a set of design analysis tools that check both
the design and test vectors for correctness and
compatibility with in-house ASIC testers, and analyz e the
design for inefficiencies and possible flaws that could
cause problems in manufacturing the device.
AMI Environment
Memory
Compiler
Models &
Symbols
Physical Data
Design
Verification
Place and Route
Post Route
Verification
ATPG
AMI ASIC
Std. Library
Synthesis T ool
Logic Synthesis
Schematic
Translation
HDL
VHDL
Schematic
Entry
Design
Database
Timing
Simulation
Estimated
Delays
Vector
Generation
Enhanced
Design Utilities
Netlist
Translation
AMI ASIC
Stnd. Library
Optional
Third Party
Environment
FIGURE 3: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE
in AMI Design Kit
**
**
**
Elements supplied
**
**
**
5
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993
Products and Services
The Design Library
AMI provides a robust collection of building blocks for the
AMI8S standard cell family. A broad range of primary
cells is complemented with memory cell compilers and
useful megafunctions. With such broad, US-based design
talent, AMI can quickly design specific cells that
customers need to add an edge in customization.
The AMI ASIC Standard Library
The AMI ASIC Standard Library contains a rich set of
core and pad cells which allow great flexibility in building
competitive devices for customer applications . The libr ary
is portable across all AMI’s gate array and standard cell
families. The ASIC Standard Library is listed in detail on
pages 9 to 21.
Soft Datapath Library (xx by yy)
Name Function
MGAxxyyDv Adder
MGAxxyyEv Adder-subtracter
MGBxxyyAv Arithmetic/barrel shifter
MGBxxBv Barrel shifter
MGBxxCv Arithmetic shifter
MGCxxAv 2-function binary comparator
MGCxxBv 6-function binary comparator
MGDxxAv Decrementer
MGFxxyyC1 Latch-based FIFO
MGIxxAv Incrementer
MGIxxBv Incrementer/decrementer
MGMxxyyDv Signed/unsigned multiplier
MGMxxyyEv Multiplier-accumulator
MGSxxyyAv Signed/unsigned subtracter
Memory Compilers
The AMI8S family includes the line of memor y compilers
shown abo v e . Each of the thousands of possible memory
blocks is optimized precisely to the customers’
parameters rather than built from a presized leaf cell that
covers a range of sizes. This yields a better size and
performance match for each application.
Upon supplying the cell specification to AMI, the
customer can receive an accurate simulation timing
specification overnight by facsimile and a full simulation
model f or any AMI supported software environment within
five working days.
Datapath Synthesizers
AMI8S also supports the complex datapath functions
listed here. These functions are synthesized from an
input set of design parameters, and can be optimized for
either minimum delay, minimum area or a compromise
between the two. Contact AMI for the size range and
parameter set for any desired functions.
These logic synthesizers produce soft megacell
schematics in the ASIC Standard Library, and a
schematic symbol for incorporation and simulation with
the design netlist.
Megacells
The AMI8S standard cell family supports soft megacell
versions of many popular architectures. These products
are listed on the following page.
Soft megacells are functionally and logically compatible
with the standard products of similar names, but are
captured in the AMI ASIC Standard Library and are
placed and routed with the user’s defined logic.
AMI supplies an actual gate le v el netlist and schematic of
the soft megacell to the customer allowing him to make
design changes or remove unneeded features as
required. Test vectors are provided and can be used
directly or incorporated into the overall design test. All
soft megacells are static designs and use AMI’s ASIC
Standard Library to ensure portability.
Memory Compiler Library
Memory Compiler Size Increment Comments
min. max.
SRAM (single-port, synchronous) 32 x 1 2K x 32 16 words, 1 bit 7 ns typical access time on 1Kx16
11 ns typical cycle time on 1Kx16
SRAM (dual-port, synchronous) 32 x 1 1K x 32 16 words, 1 bit 8 ns typical access time on 1Kx16
ROM (synchronous) 64 x 1 16K x 32 64 words, 1 bit 4.5 ns typical access time on 256x16
SRAM (single-port, asynchronous) 32 x 1 2K x 32 16 words, 1 bit Under development
SRAM (dual-port, asynchronous) 32 x 1 1K x 32 16 words, 1 bit Under development
6
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
MG82C50A Asynchronous comm. element
MG82C54 Programmable interval timer
MG82C55A Programmable peripheral interface
MG82C59A Programmable interrupt controller
MGMC51 8-bit microcontroller, 8051 compatible
MGMC51FB 8-bit microcontroller, 8051 compatible
Name Function
Soft Megacell Library
Name Function
MG1468C18 Real-time clock
MG29C01 4-bit microprocessor slice
MG29C10 Microprogram controller/sequencer
MG65C02 8-bit microprocessor
MG80C85 8-bit microprocessor
MG82C37A Programmable DMA controller
DC Specifications
Operating Specifications
Parameter Minimum Maximum Units
VDD, Supply Voltage 2.7 5.5 Volts
Ambient Temperature - Military -55 125 °C
- Commercial 0 70 °C
CMOS Input Specifications (4.5V<VDD<5.5V; -55oC<T<125oC)
Vil Low Level Input Voltage 0.3*VDD Volts
Vih High Level Input Voltage 0.7*VDD Volts
Iil Low Level Input Current -1.0 µA
Iih High Level Input Current 1.0 µA
Iil Input Pull-Up Current -30 -140 µA
Iih Input Pull-Down Current 30 185 µA
Vt- Schmitt Negative Threshold 0.2*VDD Volts
Vt+ Schmitt Positive Threshold 0.8*VDD Volts
Vh Schmitt Hysteresis 1.0 Volts
TTL Input Specifications (4.5V<VDD<5.5V; -55oC<T<125oC)
Vil Low Level Input Voltage 0.8 Volts
Vih High Level Input Voltage 2.0 Volts
Iil Low Level Input Current -1.0 µA
Iih High Level Input Current 1.0 µA
Iil Input Pull-Up Current -30 -140 µA
Iih Input Pull-Down Current 30 185 µA
Vt- Schmitt Negative Threshold 0.7 Volts
Vt+ Schmitt Positive Threshold 2.1 Volts
Vh Schmitt Hysteresis 0.4 Volts
7
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Output Operating Specifications (4.5V<VDD<5.5V;0°C<T<70°C)
Absolute Maximum Ratings
Note that these specifications are to indicate levels where permanent damage to the device may occur. Functional
operation is not guaranteed under these conditions. Further, operation at absolute maximum conditions for extended
periods may adversely affect the long term reliability of the device.
Parameter Minimum Maximum Units
1.0 mA Driver
Vol Low Level Output Voltage 0.4 Volts
Voh High Level Output Voltage 2.4 Volts
Iol Low Level Output Current 1.0 mA
Ioh High Level Output Current -1.0 mA
2.0 mA Driver
Vol Low Level Output Voltage 0.4 Volts
Voh High Level Output Voltage 2.4 Volts
Iol Low Level Output Current 2.0 mA
Ioh High Level Output Current -2.0 mA
4.0 mA Driver
Vol Low Level Output Voltage 0.4 Volts
Voh High Level Output Voltage 2.4 Volts
Iol Low Level Output Current 4.0 mA
Ioh High Level Output Current -4.0 mA
8.0 mA Driver
Vol Low Level Output Voltage 0.4 Volts
Voh High Level Output Voltage 2.4 Volts
Iol Low Level Output Current 8.0 mA
Ioh High Level Output Current -8.0 mA
Parameter Minimum Maximum Units
VDD, Supply Voltage -0.3 7.0 Volts
Input Pin Voltage -0.3 VDD+0.3 Volts
Input Pin Current -10.0 10.0 mA
Storage Temperature - Plastic Packages -55 125 °C
- Ceramic Packages -65 150 °C
Lead Temperature 300 °C for 10 sec.
8
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Library Cell Selection Guide
This selection guide outlines the basic perfor mance of each cell in the AMI ASIC Standard Librar y. Other custom cells
can be created f or specific needs. For detailed design analysis please contact an AMI ASIC Design Center f or a software
design kit and more detailed data sheets.
An explanation of the information contained in the selection guide is listed below:
Eq. Gates This column lists the equivalent gates of each core cell. It is a measure of the cell size normalized
to the area of a 2-input NAND gate. A 2-input NAND gate (NA21) requires f our transistors and is an
industry standard for comparing gate array and standard cell products.
I/O Cells This column lists the number of I/O sites (or pad sites) required to implement the listed I/O cell.
Parameters The parameters column lists the mnemonics for the propagation delay or timing parameter whose
values are given under “Propagation Delay”:
tPLH Input to output propagation delay for a rising edge on the output
tPHL Input to output propagation delay for a falling edge on the output
tZH High impedance to high level delay
tZL High impedance to low level delay
tsu Input setup time with respect to clock
th Input hold time
tPZ Valid to high impedance state on the output
Propagation This column shows the values of the delay parameter for three different loads. For output pad cells,
Delay 25pf, 50pf, and 75pf loads are used. For core cells and input pad cells, fanouts of two, four, and
eight gates are used. A fanout consists of that number of NA21 input capacitive loads and an aver-
age interconnect capacitance based on past layout experience. Delays are in nanoseconds.
Description This final column gives a short textual description of the cell.
9
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Simple Gates
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
AA21 1.3 tPLH 0.39 0.50 0.73 2-input AND gate
tPHL 0.42 0.52 0.70
AA22 1.7 tPLH 0.39 0.45 0.57 2-input AND gate
tPHL 0.42 0.48 0.59
AA31 1.7 tPLH 0.50 0.63 0.87 3-input AND gate
tPHL 0.54 0.64 0.83
AA32 2.3 tPLH 0.52 0.59 0.71 3-input AND gate
tPHL 0.55 0.62 0.73
AA41 2.0 tPLH 0.58 0.70 0.94 4-input AND gate
tPHL 0.62 0.74 0.94
AA42 2.3 tPLH 0.59 0.66 0.79 4-input AND gate
tPHL 0.63 0.70 0.82
EN21 2.1 tPLH 0.50 0.69 1.15 Exclusive NOR
tPHL 0.47 0.59 0.83
EO21 2.1 tPLH 0.62 0.83 1.27 Exclusive OR
tPHL 0.60 0.70 0.88
NA21 1.0 tPLH 0.28 0.40 0.65 2-input NAND gate
tPHL 0.23 0.35 0.58
NA22 1.7 tPLH 0.22 0.28 0.41 2-input NAND gate
tPHL 0.19 0.25 0.37
NA31 1.4 tPLH 0.37 0.51 0.79 3-input NAND gate
tPHL 0.32 0.46 0.74
NA32 2.2 tPLH 0.28 0.35 0.50 3-input NAND gate
tPHL 0.23 0.30 0.44
NA41 1.7 tPLH 0.47 0.62 0.93 4-input NAND gate
tPHL 0.41 0.57 0.90
NA42 3.0 tPLH 0.37 0.45 0.61 4-input NAND gate
tPHL 0.30 0.39 0.55
NA51 2.0 tPLH 0.73 0.91 1.26 5-input NAND gate
tPHL 0.66 0.84 1.21
NA52 3.7 tPLH 0.46 0.55 0.73 5-input NAND gate
tPHL 0.38 0.48 0.66
NA61 3.8 tPLH 0.74 0.85 1.07 6-input NAND gate
tPHL 0.78 0.89 1.09
NA81 4.7 tPLH 0.86 0.97 1.21 8-input NAND gate
tPHL 0.87 0.98 1.18
NO21 1.0 tPLH 0.38 0.58 0.98 2-input NOR gate
tPHL 0.24 0.34 0.53
NO22 1.7 tPLH 0.27 0.37 0.58 2-input NOR gate
tPHL 0.18 0.23 0.33
NO31 1.4 tPLH 0.61 0.89 1.45 3-input NOR gate
tPHL 0.29 0.40 0.62
NO32 2.2 tPLH 0.45 0.59 0.88 3-input NOR gate
tPHL 0.23 0.29 0.41
NO41 1.8 tPLH 0.84 1.18 1.88 4-input NOR gate
tPHL 0.34 0.48 0.74
10
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
NO42 2.5 tPLH 0.62 0.80 1.14 4-input NOR gate
tPHL 0.27 0.35 0.49
NO51 2.1 tPLH 1.12 1.53 2.36 5-input NOR gate
tPHL 0.40 0.57 0.87
NO52 3.7 tPLH 0.85 1.06 1.47 5-input NOR gate
tPHL 0.31 0.40 0.56
OR21 1.7 tPLH 0.40 0.52 0.75 2-input OR gate
tPHL 0.51 0.62 0.82
OR22 1.8 tPLH 0.39 0.46 0.57 2-input OR gate
tPHL 0.55 0.62 0.74
OR31 1.8 tPLH 0.47 0.58 0.80 3-input OR gate
tPHL 0.71 0.83 1.05
OR32 2.0 tPLH 0.47 0.54 0.66 3-input OR gate
tPHL 0.80 0.88 1.02
OR41 2.2 tPLH 0.53 0.65 0.88 4-input OR gate
tPHL 0.94 1.07 1.31
OR42 2.5 tPLH 0.54 0.61 0.73 4-input OR gate
tPHL 1.03 1.12 1.27
Complex Gates
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
AN11 1.7 tPLH 0.57 0.78 1.19 Two 2-input ANDs into 2-input NOR
tPHL 0.46 0.61 0.91
AN31 1.8 tPLH 0.69 0.95 1.48 2-input AND into 3-input NOR
tPHL 0.48 0.65 1.08
AU11
6.0 A to S tPLH 1.39 1.51 1.74 One-bit full adder
tPHL 1.33 1.46 1.70
B to S tPLH 1.49 1.62 1.86
tPHL 1.31 1.44 1.67
CI to S tPLH 1.27 1.39 1.63
tPHL 1.29 1.42 1.65
ON11 1.8 tPLH 0.55 0.76 1.16 Two 2-input ORs into 2-input NAND
tPHL 0.48 0.63 0.94
ON31 1.7 tPLH 0.50 0.72 1.19 2-input OR into 3-input NAND
tPHL 0.45 0.61 0.94
Simple Gates (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
11
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Inverting Drivers
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
INV1 1.0 tPLH 0.22 0.33 0.56 Inverter
tPHL 0.19 0.29 0.47
INV2 1.0 tPLH 0.16 0.21 0.33 Inverter
tPHL 0.14 0.19 0.29
INV3 1.3 tPLH 0.13 0.17 0.24 Inverter
tPHL 0.11 0.15 0.22
INV4 1.5 tPLH 0.12 0.15 0.21 Inverter
tPHL 0.11 0.14 0.19
INV5 1.8 tPLH 0.11 0.13 0.18 Inverter
tPHL 0.09 0.12 0.16
INV6 2.1 tPLH 0.10 0.12 0.17 Inverter
tPHL 0.09 0.11 0.15
Internal 3-State Drivers
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
ITA1
2.0 A to Q tPLH 0.50 0.69 1.08 Internal non-inverting tri-state buffer
tPHL 0.45 0.60 0.90
EN to Q tZH 0.30 0.49 0.88
tZL 0.31 0.46 0.76
ITA2
2.9 A to Q tPLH 0.43 0.50 0.63 Internal non-inverting tri-state buffer
tPHL 0.41 0.47 0.58
EN to Q tZH 0.15 0.22 0.35
tZL 0.22 0.27 0.38
ITB1
1.4 A to QN tPLH 0.42 0.61 1.01 Internal inverting tri-state buffer
tPHL 0.33 0.48 0.78
EN to QN tZH 0.32 0.51 0.91
tZL 0.33 0.48 0.77
ITB2
2.5 A to QN tPLH 0.28 0.35 0.50 Internal inverting tri-state buffer
tPHL 0.22 0.27 0.38
EN to QN tZH 0.18 0.25 0.39
tZL 0.24 0.30 0.41
ITD1
1.4 A to QN tPLH 0.43 0.62 1.03 Internal inverting tri-state buffer
tPHL 0.33 0.48 0.78
E to QN tZH 0.42 0.62 1.02
tZL 0.23 0.38 0.68
ITD2
2.5 A to QN tPLH 0.28 0.36 0.50 Internal inverting tri-state buffer
tPHL 0.20 0.25 0.36
E to QN tZH 0.32 0.40 0.54
tZL 0.11 0.17 0.27
ITE1
1.3 A to QN tPLH 0.42 0.62 1.02 Internal inverting tri-state buffer
tPHL 0.33 0.48 0.77
EN to QN tZH 0.37 0.57 0.97
E to QN tZL 0.31 0.46 0.75
12
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Clock Drivers
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
IID2 1.7 tPLH 0.26 0.31 0.43 Non-inverting clock driver
tPHL 0.27 0.32 0.42
IID4 2.3 tPLH 0.28 0.32 0.38 Non-inverting clock driver
tPHL 0.31 0.34 0.40
IID6 2.7 tPLH 0.33 0.35 0.40 Non-inverting clock driver
tPHL 0.36 0.39 0.43
Muxes and Decoders
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
DC24
6.3 Sx to QN tPLH 0.53 0.67 0.95 2:4 line decoder
tPHL 0.52 0.66 0.94
EN to QN tPLH 0.70 0.84 1.12
tPHL 0.64 0.78 1.12
DC38
15.2 Sx to QN tPLH 0.73 0.83 1.03 3:8 line decoder
tPHL 0.66 0.77 0.98
EN to QN tPLH 1.05 1.21 1.52
tPHL 0.91 1.08 1.41
MX21
2.5 Ix to Q tPLH 0.55 0.66 0.89 2:1 digital multiplexer
tPHL 0.55 0.67 0.89
S to Q tPLH 0.74 0.86 1.08
tPHL 0.77 0.88 1.08
MX41
6.0 Ix to Q tPLH 1.15 1.29 1.53 4:1 digital multiplexer
tPHL 1.04 1.22 1.51
S to Q tPLH 1.14 1.28 1.52
tPHL 1.19 1.35 1.62
MX81
13.9 Ix to Q tPLH 1.29 1.41 1.64 8:1 digital multiplexer
tPHL 1.25 1.37 1.59
S to Q tPLH 1.27 1.39 1.62
tPHL 1.27 1.39 1.61
13
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Sequential Logic
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
DF081
4.3 C to Q tPLH 0.60 0.79 1.18 D-type F/F without set or reset
tPHL 0.33 0.47 0.78
D Setup tsu 0.59
D Hold th0.00
DF091
4.9 C to Q tPLH 0.68 0.81 1.07 D-type F/F with active low set
tPHL 0.91 1.05 1.30
D Setup tsu 0.57
D Hold th0.00
DF0A1
5.5 C to Q tPLH 0.82 1.01 1.41 D-type F/F with active low reset
tPHL 0.90 1.02 1.24
D Setup tsu 0.63
D Hold th0.00
DF0B1
6.5 C to Q tPLH 0.70 0.83 1.09 D-type F/F with active low set and reset
tPHL 0.96 1.10 1.35
D Setup tsu 0.69
D Hold th0.00
DF101
5.8 C to Q tPLH 0.55 0.69 0.95 D-type buffered F/F with active low set
tPHL 0.76 0.88 1.10
D Setup tsu 0.56
D Hold th0.00
DF111
6.9 C to Q tPLH 0.54 0.66 0.90 D-type buffered F/F with active low reset
tPHL 0.78 0.91 1.12
D Setup tsu 0.62
D Hold th0.00
DF121
7.6 C to Q tPLH 0.58 0.71 0.95 D-type buffered F/F with active low set
and reset
tPHL 0.83 0.96 1.18
D Setup tsu 0.68
D Hold th0.00
DL531
2.2 D to Q tPLH 0.70 0.81 1.04 D-type latch without set or reset
tPHL 0.75 0.86 1.07
GN to Q tPLH 0.81 0.93 1.16
tPHL 0.66 0.77 0.98
D Setup tsu 0.77
D Hold th0.00
DL541
3.4 D to Q tPLH 0.80 1.00 1.40 D-type latch with active low reset
tPHL 0.66 0.77 0.98
GN to Q tPLH 0.86 1.06 1.46
tPHL 0.57 0.68 0.88
D Setup tsu 1.00
D Hold th0.00
DL551
3.0 D to Q tPLH 0.65 0.77 1.02 D-type latch with active low set
tPHL 0.69 0.82 1.06
GN to Q tPLH 0.71 0.84 1.09
tPHL 0.60 0.72 0.97
D Setup tsu 0.82
D Hold th0.00
14
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
DL561
3.7 D to Q tPLH 0.80 0.94 1.20 D-type latch with activ e lo w set and reset
tPHL 0.78 0.91 1.16
GN to Q tPLH 0.84 0.97 1.24
tPHL 0.66 0.79 1.04
D Setup tsu 0.93
D Hold th0.00
DL641
4.6 D to Q tPLH 1.11 1.22 1.44 D-type buffered latch with active low
reset
tPHL 0.99 1.08 1.27
GN to Q tPLH 1.17 1.28 1.50
tPHL 0.90 1.00 1.18
D Setup tsu 0.71
D Hold th0.00
DL651
4.0 D to Q tPLH 0.99 1.10 1.32 D-type buffered latch with active low set
tPHL 1.04 1.14 1.33
GN to Q tPLH 1.05 1.17 1.39
tPHL 0.95 1.05 1.23
D Setup tsu 0.63
D Hold th0.00
DL661
4.7 D to Q tPLH 1.09 1.20 1.42 D-type buffered latch with active low set
and reset
tPHL 1.15 1.24 1.43
GN to Q tPLH 1.13 1.24 1.47
tPHL 1.01 1.11 1.30
D Setup tsu 0.73
D Hold th0.00
DLZ01
3.1 D to Q tPLH 0.78 0.89 1.12 D-type latch without set or reset and a
dual-enable tri-state output
tPHL 0.87 1.00 1.22
GN to Q tPLH 0.89 1.01 1.23
tPHL 0.78 0.90 1.13
D Setup tsu 0.90
D Hold th0.00
DLZ11
4.3 D to Q tPLH 1.07 1.21 1.46 D-type latch with active low reset and a
dual-enable tri-state output
tPHL 0.93 1.06 1.29
GN to Q tPLH 1.15 1.28 1.53
tPHL 0.84 0.97 1.20
D Setup tsu 1.11
D Hold th0.00
JK091
6.9 C to Q tPLH 0.87 1.01 1.28 JK-type F/F with active low set
tPHL 1.14 1.29 1.57
J Setup tsu 1.03
J Hold th0.00
K Setup tsu 0.85
K Hold th0.00
Sequential Logic (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
15
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
JK0A1
7.3 C to Q tPLH 1.01 1.21 1.61 JK-type F/F with active low reset
tPHL 1.10 1.24 1.48
J Setup tsu 1.08
J Hold th0.00
K Setup tsu 0.95
K Hold th0.00
JK0B1
9.3 C to Q tPLH 0.89 1.03 1.30 JK-type F/F with activ e low set and reset
tPHL 1.16 1.31 1.59
J Setup tsu 1.10
J Hold th0.00
K Setup tsu 0.96
K Hold th0.00
JKBB1
10.4 C to Q tPLH 0.75 0.89 1.14 JK-type buffered F/F with active low set
and reset
tPHL 1.05 1.19 1.43
J Setup tsu 1.18
J Hold th0.00
K Setup tsu 0.96
K Hold th0.00
Sequential Logic (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
16
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Special Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
BL02 2.0 tPLH 0.33 Tri-state bus latch
tPHL 0.42
QD01X1 2 I/O QO to QC tPLH 0.69 0.73 0.80 3.58MHz (1MHz - 10MHz) crystal oscil-
lator
tPHL 0.65 0.69 0.76
QD03X1 2 I/O QO to QC tPLH 0.82 0.85 0.91 20MHz (10MHz - 32MHz) cyrstal oscilla-
tor
tPHL 0.85 0.88 0.95
QD11X1 2 I/O QO to QC tPLH 2.17 2.23 2.33 32KHz (1KHz - 1MHz) crystal oscillator
with Schmitt Trigger
tPHL 1.61 1.64 1.74
TD08 5.9 tPLH 8.18 8.25 8.37 Time delay cell, non-inverting
tPHL 8.34 8.42 8.56
PORA 120.2 RST to
POR tPLH 4089.35 4089.38 4089.47 Power-on-reset
tPHL 11.13 11.17 11.28
PORB 155.2 RST to
POR tPLH 1142.64 1142.79 1143.10 Power-on-reset for 3 volt operation
tPHL 21.85 22.39 23.51
Input Pad Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
IB01X1 1 I/O tPLH 0.62 0.66 0.73 CMOS input buffer
tPHL 0.84 0.88 0.95
IB03X1 1 I/O tPLH 0.61 0.65 0.73 CMOS input buffer with pull-up
tPHL 0.83 0.88 0.95
IB05X1 1 I/O tPLH 0.61 0.65 0.73 CMOS input buffer with pull-down
tPHL 0.83 0.87 0.95
IB07X1 1 I/O tPLH 0.69 0.73 0.80 TTL input buffer
tPHL 1.01 1.06 1.15
IB09X1 1 I/O tPLH 0.69 0.73 0.80 TTL input buffer with pull-up
tPHL 1.01 1.06 1.15
IB0BX1 1 I/O tPLH 0.69 0.73 0.80 TTL input buffer with pull-down
tPHL 1.01 1.06 1.15
IB0DX1 1 I/O tPLH 2.24 2.29 2.39 CMOS Schmitt trigger input buffer
tPHL 1.77 1.82 1.91
IB30X1 1 I/O tPLH 1.23 1.28 1.36 TTL Schmitt trigger input buffer
tPHL 2.52 2.60 2.72
17
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Output Pad Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
OB01X1 1 I/O tPLH 3.77 6.70 9.63 TTL output buffer, 1mA
tPHL 5.63 10.02 14.44
OB01X2 1 I/O tPLH 2.07 3.54 5.01 TTL output buffer, 2mA
tPHL 5.55 9.94 14.35
OB01X3 1 I/O tPLH 1.35 2.09 2.83 TTL output buffer, 4mA
tPHL 3.12 5.33 7.54
OB01X5 1 I/O tPLH 1.12 1.62 2.12 TTL output buffer, 8mA
tPHL 1.85 2.95 4.05
OB03X1 1 I/O tPLH 6.59 12.02 17.45 CMOS output buffer, 1mA
tPHL 3.77 6.52 9.28
OB03X2 1 I/O tPLH 3.50 6.22 8.95 CMOS output buffer, 2mA
tPHL 3.66 6.43 9.18
OB03X3 1 I/O tPLH 2.08 3.45 4.81 CMOS output buffer, 4mA
tPHL 2.18 3.56 4.95
OB03X5 1 I/O tPLH 1.62 2.54 3.46 CMOS output buffer, 8mA
tPHL 1.37 2.07 2.76
OB06X1 1 I/O tPLH 5.41 10.82 16.23 CMOS P-channel, open drain, inverting
output buffer, 1mA
tPZ 0.66
OB06X2 1 I/O tPLH 3.09 5.80 8.50 CMOS P-channel, open drain, inverting
output buffer, 2mA
tPZ 0.74
OB06X3 1 I/O tPLH 1.93 3.29 4.66 CMOS P-channel, open drain, inverting
output buffer, 4mA
tPZ 0.94
OB07X1 1 I/O tPZ 0.41 TTL N-channel, open drain output b uffer ,
1mA
tPHL 4.42 8.81 13.20
OB07X2 1 I/O tPZ 0.29 TTL N-channel, open drain output b uffer ,
2mA
tPHL 4.30 8.70 13.11
OB07X3 1 I/O tPZ 0.36 TTL N-channel, open drain output b uffer ,
4mA
tPHL 2.32 4.52 6.73
OB09X1
1 I/O A to Q tPLH 6.53 11.96 17.38 CMOS tri-state output buffer, 1mA
tPHL 3.80 6.56 9.32
EN to Q tZH 6.65 12.09 17.52
tZL 3.82 6.58 9.34
OB09X2
1 I/O A to Q tPLH 3.71 6.43 9.16 CMOS tri-state output buffer, 2mA
tPHL 3.81 6.58 9.34
EN to Q tZH 3.84 6.57 9.30
tZL 3.81 6.58 9.34
OB09X3
1 I/O A to Q tPLH 2.18 3.56 4.92 CMOS tri-state output buffer, 4mA
tPHL 2.23 3.62 5.00
EN to Q tZH 2.38 3.75 5.12
tZL 2.22 3.61 4.99
OB15X1
1 I/O A to Q tPLH 3.70 6.63 9.56 TTL tri-state output buffer, 1mA
tPHL 5.68 10.05 14.47
EN to Q tZH 3.83 6.76 9.69
tZL 5.69 10.07 14.48
18
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
OB15X2
1 I/O A to Q tPLH 2.26 3.74 5.21 TTL tri-state output buffer, 2mA
tPHL 5.68 10.07 14.47
EN to Q tZH 2.40 3.87 5.34
tZL 5.68 10.07 14.47
OB15X3
1 I/O A to Q tPLH 1.45 2.20 2.93 TTL tri-state output buffer, 4mA
tPHL 3.18 5.37 7.58
EN to Q tZH 1.64 2.39 3.13
tZL 3.17 5.37 7.58
OB81X5 1 I/O tPLH 1.37 2.11 2.85 TTL output buffer, 8mA, with controlled
slew rate output
tPHL 3.12 5.21 7.26
OB83X5 1 I/O tPLH 2.10 3.47 4.83 CMOS output buffer with controlled sle w
rate output, 8mA
tPHL 2.21 3.59 4.97
OB86X5 1 I/O tPLH 2.38 3.75 5.11 CMOS inverting open drain P-channel
output buffer with controlled slew rate
output, 8mA
tPZ 1.10
OB87X5 1 I/O tPZ 0.53 TTL open drain N-channel output buffer
with controlled slew rate output, 8mA
tPHL 2.78 4.85 6.91
OB89X5
1 I/O A to Q tPLH 2.22 3.59 4.96 CMOS tri-state output buffer with con-
trolled slew rate output, 8mA
tPHL 2.26 3.64 5.02
EN to Q tZH 2.52 3.89 5.25
tZL 2.22 3.61 5.00
OB95X5
1 I/O A to Q tPLH 1.48 2.23 2.96 TTL tri-state output buff er with controlled
slew rate output, 8mA
tPHL 3.19 5.33 7.43
EN to Q tZH 1.77 2.52 3.26
tZL 3.16 5.31 7.41
Input/Output Pad Cells
Name Eq
Gates Parameters Propagation Delay (nS) Description
25pF 50pF 75pF
IO01X1
1 I/O A to IO tPLH 3.72 6.65 9.58 TTL I/O buffer, 1mA
tPHL 5.66 10.07 14.48
EN to IO tZH 3.85 6.79 9.72
tZL 5.68 10.09 14.50
IO01X2
1 I/O A to IO tPLH 2.27 3.74 5.22 TTL I/O buffer, 2mA
tPHL 5.68 10.10 14.50
EN to IO tZH 2.40 3.88 5.35
tZL 5.68 10.10 14.51
IO01X3
1 I/O A to IO tPLH 1.45 2.20 2.94 TTL I/O buffer, 4mA
tPHL 3.18 5.38 7.59
EN to IO tZH 1.65 2.40 3.14
tZL 3.17 5.38 7.59
Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
19
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
IO03X1
1 I/O A to IO tPLH 6.55 11.98 17.41 CMOS I/O buffer, 1mA
tPHL 3.81 6.56 9.33
EN to IO tZH 6.68 12.11 17.54
tZL 3.82 6.58 9.35
IO03X2
1 I/O A to IO tPLH 3.71 6.44 9.17 CMOS I/O buffer, 2mA
tPHL 3.81 6.58 9.34
EN to IO tZH 3.85 6.58 9.31
tZL 3.81 6.58 9.35
IO03X3
1 I/O A to IO tPLH 2.19 3.56 4.93 CMOS I/O buffer, 4mA
tPHL 2.24 3.62 5.00
EN to IO tZH 2.38 3.75 5.12
tZL 2.22 3.61 5.00
IO3CX1
1 I/O A to IO tPLH 6.60 12.05 17.49 CMOS I/O buffer with pull-down, 1mA
tPHL 3.80 6.54 9.28
EN to IO tZH 6.73 12.18 17.63
tZL 3.84 6.59 9.35
IO3CX2
1 I/O A to IO tPLH 3.73 6.47 9.20 CMOS I/O buffer with pull-down, 2mA
tPHL 3.81 6.55 9.30
EN to IO tZH 3.88 6.61 9.34
tZL 3.82 6.56 9.32
IO3CX3
1 I/O A to IO tPLH 1.92 3.26 4.58 CMOS I/O buffer with pull-down, 4mA
tPHL 1.90 3.24 4.57
EN to IO tZH 2.09 3.42 4.75
tZL 1.90 3.24 4.57
IO3FX1
1 I/O A to IO tPLH 3.74 6.68 9.61 TTL I/O buffer with pull-down, 1mA
tPHL 5.67 10.05 14.43
EN to IO tZH 3.87 6.81 9.74
tZL 5.71 10.10 14.50
IO3FX2
1 I/O A to IO tPLH 2.27 3.75 5.23 TTL I/O buffer with pull-down, 2mA
tPHL 5.67 10.06 14.44
EN to IO tZH 2.41 3.89 5.36
tZL 5.67 10.07 14.46
IO3FX3
1 I/O A to IO tPLH 1.46 2.21 2.94 TTL I/O buffer with pull-down, 4mA
tPHL 3.19 5.39 7.59
EN to IO tZH 1.65 2.40 3.14
tZL 3.18 5.39 7.59
IO41X1
1 I/O A to IO tPLH 3.69 6.59 9.49 TTL I/O buffer with pull-up, 1mA
tPHL 5.68 10.11 14.53
EN to IO tZH 3.83 6.75 9.66
tZL 5.70 10.13 14.55
IO41X2
1 I/O A to IO tPLH 2.26 3.73 5.19 TTL I/O buffer with pull-up, 2mA
tPHL 5.71 10.13 14.55
EN to IO tZH 2.41 3.88 5.35
tZL 5.70 10.13 14.55
Input/Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (nS) Description
25pF 50pF 75pF
20
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
IO41X3
1 I/O A to IO tPLH 1.46 2.20 2.94 TTL I/O buffer with pull-up, 4mA
tPHL 3.19 5.39 7.60
EN to IO tZH 1.65 2.40 3.14
tZL 3.18 5.39 7.59
IO42X1
1 I/O A to IO tPLH 6.50 11.88 17.27 CMOS I/O buffer with pull-up, 1mA
tPHL 3.82 6.59 9.35
EN to IO tZH 6.64 12.03 17.43
tZL 3.84 6.61 9.37
IO42X2
1 I/O A to IO tPLH 3.70 6.41 9.13 CMOS I/O buffer with pull-up, 2mA
tPHL 3.84 6.60 9.37
EN to IO tZH 3.84 6.56 9.28
tZL 3.84 6.60 9.37
IO42X3
1 I/O A to IO tPLH 2.19 3.55 4.92 CMOS I/O buffer with pull-up, 4mA
tPHL 2.24 3.62 5.01
EN to IO tZH 2.38 3.75 5.12
tZL 2.23 3.62 5.00
IO51X1
1 I/O A to IO tPLH 6.54 11.97 17.40 CMOS I/O buffer with Schmitt trigger
input, 1mA
tPHL 3.81 6.57 9.33
EN to IO tZH 6.67 12.10 17.53
tZL 3.82 6.59 9.35
IO51X2
1 I/O A to IO tPLH 3.71 6.44 9.17 CMOS I/O buffer with Schmitt trigger
input, 2mA
tPHL 3.83 6.59 9.36
EN to IO tZH 3.85 6.58 9.31
tZL 3.83 6.59 9.36
IO51X3
1 I/O A to IO tPLH 1.92 3.25 4.58 CMOS I/O buffer with Schmitt trigger
input, 4mA
tPHL 1.91 3.24 4.58
EN to IO tZH 2.08 3.41 4.74
tZL 1.90 3.24 4.58
IO81X5
1 I/O A to IO tPLH 1.48 2.23 2.97 TTL I/O tri-state buffer with controlled
slew rate output, 8mA
tPHL 3.20 5.35 7.45
EN to IO tZH 1.78 2.53 3.27
tZL 3.17 5.32 7.43
IO83X5
1 I/O A to IO tPLH 2.22 3.59 4.96 CMOS I/O tri-state buffer with controlled
slew rate output, 8mA
tPHL 2.26 3.64 5.02
EN to IO tZH 2.52 3.89 5.26
tZL 2.23 3.62 5.00
IOBCX5
1 I/O A to IO tPLH 2.23 3.61 4.97 CMOS I/O tri-state buffer with pull-down
and controlled slew rate output, 8mA
tPHL 2.26 3.64 5.02
EN to IO tZH 2.53 3.90 5.27
tZL 2.23 3.62 5.00
IOBFX5
1 I/O A to IO tPLH 1.49 2.23 2.97 TTL I/O tri-state buffer with pull-down
and controlled slew rate output, 8mA
tPHL 3.21 5.35 7.45
EN to IO tZH 1.78 2.53 3.27
tZL 3.18 5.33 7.43
Input/Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (nS) Description
25pF 50pF 75pF
21
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
IOC1X5
1 I/O A to IO tPLH 1.48 2.23 2.96 TTL I/O tri-state buffer with pull-up and
controlled slew rate output, 8mA
tPHL 3.21 5.36 7.46
EN to IO tZH 1.78 2.52 3.26
tZL 3.18 5.34 7.44
IOC2X5
1 I/O A to IO tPLH 2.22 3.60 4.96 CMOS I/O tri-state buffer with pull-up,
and controlled slew rate output, 8mA
tPHL 2.27 3.65 5.04
EN to IO tZH 2.52 3.90 5.26
tZL 2.24 3.63 5.01
IOD1X5
1 I/O A to IO tPLH 2.22 3.60 4.96 CMOS I/O tri-state buffer with Schmitt
trigger and controlled slew rate output,
8mA
tPHL 2.26 3.65 5.03
EN to IO tZH 2.52 3.89 5.26
tZL 2.23 3.62 5.00
Power Cells
Name Eq
Gates Description
CVDD 1.0 Core cell input resistive tie-up to core
Vdd bus
CVSS 1.0 Core cell input resistive tie-down to core
Vss bus
PP01X 1 I/O Vss power pad for core and pad cells
PP02X 1 I/O Vdd power pad for core and pad cells
PP04X 1 I/O Optional power pad pin for additional
busess
PPC1X 1 I/O Vss power pad pin for input buffers and
core cells only
PPP1X 1 I/O Vss power pad pin for output buffers
only
Input/Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (nS) Description
25pF 50pF 75pF
22
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993 Products and Services
Delay Derating Information
The propagation delays listed in the Selection Guide (pages 9 to 21) are for typical temperature, 25 oC, typical supply
voltage, 5.0V., and typical processing conditions. To calculate the delay at other conditions (including Vdd equals 3.0V)
the following equation can be used: Tpdx = Tpdx(typ)*KP*KV*KT
where Tpdx(typ) is given in the Selection Guide. KP
, the process derating coefficient, KT, the temperature derating
coefficient, and KV, the supply voltage derating coefficient are described below.
Delay Variations with Temperature (KT)
Delay varies linearly with temperature. The following formulas and common operating points can be used.
Temp. Range KT Formula
-55oC to 25oCK
T
=1.0-(25-TJoC )*2.58 x 10-3
25oC to 140oCK
T
=1.0+(TJoC-25)*2.58 x 10-3
Temp KT
-55 oC 0.79
-25 oC 0.87
0 oC 0.94
25 oC 1.00
70 oC 1.11
100 oC 1.19
125 oC 1.26
Where TJ oC is the temperature at the silicon junction.
Delay Variations with Process (KP)
Delay variations with process are given as fixed constants determined at the limits of acceptable manufacturing of the
process. These are described below.
Derating Coefficient ( Kp ) Process Variation Point
1.40 Delay increase due to “Worst Case Speed” (WCS) fabrication
1.00 Typical delay; fabrication target
0.61 Delay reduction due to “Worst Case Power” (WCP) fabrication
Delay V ariations with V oltage (KV)
Delay varies nonlinearly with voltage. Some common operating points and a characteristic curve are shown.
VDD KV
2.7 V 1.74
3.0 V 1.54
3.3 V 1.39
4.5 V 1.07
4.75 V 1.03
5.0 V 1.00
5.25 V 0.97
5.5 V 0.94 2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.9
1.2
1.5
1.8
Supply Voltage (volts)
Derating Coefficient,KV
23
0.8 micron CMOS
Standard Cells
Digital ASICs
August 1993
Products and Services
Packaging
The AMI8S standard cell family can be packaged in a variety of popular packages.
New packages are in development which will extend the package offering. Some special packages or packaging
requirements can be supplied if requested. More details on special packages are available from an AMI sales
representative.
Available Packages
( ) =
Lead time required
Note 1: The 304 pin PowerQuad2
package has an added heat slug to improve power dissipation.
Note 2: The 256 and 304 pin packages are supplied in a TapePak
molded carrier ring.
Copyright®1997, American Microsystems, Inc.
De vices sold b y AMI are cov ered b y the w arranty and patent indemnification pro visions appearing in its Terms of Sale only. AMI mak es
no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any pur poses. AMI reser ves the
right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended fo r
use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without
additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796
Package Type Pin Count
Plastic Quad Flatpack (PQFP) 44, 52, 64, 80, 100, 120, 128, 144, 160, 208, 256
2
, 304
1,2
Thin Quad Flatpack (TQFP) (48), 64, (80), 100, (128), (144), (176)
Metal Quad Flatpack (MQUAD
®
) 128, 144
Ceramic Quad Flatpack (CQFP) 40, 44, 132, 144
Plastic Leaded Chip Carrier (PLCC) 20, 28, 44, 68, 84
Ceramic Leaded Chip Carrier (JLDCC) 28, 44, 68, 84
Ceramic Leadless Chip Carrier (CLCC) 20, 24, 28, 36, 40, 44, 48, 52, 68, 84
Plastic Dual In-line Package (PDIP) 8, 14, 16, 18, 20, 22, 24, 28, 40, 48
Plastic Pin Grid Array (PPGA) 69, 85, 101, 109, 121, 132, 145, 180
Ceramic Pin Grid Array (CPGA) (65), 68, 69, 84, 85, 101, 109, 121, 132, 145, 177, 181, 208, 476
Ball Grid Array (BGA) (169), (225), (313)
