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FEATURES
DPower Monitoring and Switching for
Non-Volatile Control of SRAMs
DInput Decoder Allows Control of 1 or 2 Banks
of SRAM
DWrite-Protect Control
D3-V Primary Cell Input
D3.3-V Operation
DReset Output for System Power-On Reset
DLess than 20-ns Chip Enable Propagation
Delay
DSmall 16-Lead TSSOP Package
APPLICATIONS
DNVSRAM Modules
DPoint-of-Sale Systems
DFacsimile, Printers and Photocopiers
DInternet Appliances
DServers
DMedical Instrumentation and Industrial
Products
DESCRIPTION
The CMOS bq2205 SRAM non-volatile controller
with reset provides all the necessary functions for
converting one or two banks of standard CMOS
SRAM into non-volatile read/write memory.
A precision comparator monitors the 3.3-V VCC
input for an out-of-tolerance condition. When
out-of-tolerance is detected, the two conditioned
chip-enable outputs are forced inactive to
write-protect both banks of SRAM.
Power for the external SRAMs, VOUT, is switched
from the VCC supply to the battery-backup supply
as VCC decays. On a subsequent power-up, the
VOUT supply is automatically switched from the
backup supply to the VCC supply. The external
SRAMs are write-protected until a power-valid
condition exists. The reset output provides
power-fail and power-on resets for the system.
During power-valid operation, the input decoder, A ,
selects one of two banks of SRAM.
UDG−03129
VCC
VSS
RST
CECON2
CECON1
VCC
VCC
CE
CE CE
12
1
4
13
10
VOUT
VCC
A
bq2205LYPW
11
9
14
16
VCC
SRAM Bank 2
VCC
SRAM Bank 1
To Microprocessor15
VDC
GND
Backup Supply
VDC
GND
Main Supply
5
8
Pushbutton
Reset
(Optional)
BW
VSS
VSS
BCP
From Address
Selector
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Copyright 2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty , and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
SLUS581 − FEBRUAR Y 2004
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TAOPERATION PART NUMBER(1) SYMBOL
−20°C to 70°C3.3 V bq2205LYPW bq2205LY
(1) The PW package is available taped and reeled. Add an R suffix to the device type (i.e. bq2205LYPWR) to order quantities of 2,000 devices
per reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(2)
bq2205LY UNIT
VCC, (wrt VSS)−0.3 to 6.0
Input voltage range BCP, (wrt VSS)−0.3 to 4.5 V
Input voltage range
all other pins, (wrt VSS)−0.3 to VCC + 0.3
V
Operating temperature range, TA−20 to 70
Storage temperature, Tstg −55 to 125
°C
Temperature under bias, TJbias −40 to 85 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
(2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
Supply voltage, VCC 3.0 3.6
Supply voltage from backup cell, VBC 2.0 4.0
Low-level input voltage, VIL −0.3 0.8
V
High-level input voltage, VIH 2.2 VCC + 0.3 V
RST low-level input voltage, VIL −0.3 0.4
RST high-level input voltage, VIH 2.2 VCC + 0.3
Operating temperature range, TA−20 70 °C
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ELECTRICAL CHARACTERISTICS
(TA = 25°C, VCC(min) ≤ VCC ≤VCC(max) unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC supply current, ICC(vcc) VCC > VCC(MIN)
CE = low
CECONX = 0 mA 210 500 µA
Backup Battery Supply Current, ICC(BC) VBC > VBC(MIN), VCC = 0 V
CE = low
CECONX = 0 mA 50 150 nA
Output voltage (VOUT)
I(VOUT) = 80 mA, VCC > V(SO) Vcc−0.3
Output voltage (VOUT) I(VOUT)= 100µ A, VCC < V(SO) VBC−0.3
Power fail detect voltage, VPFD 2.85 2.9 2.95
Supply switch-over voltage, VSO
VBC > V(PFD) VPFD V
Supply switch-over voltage, VSO VBC < V(PFD) VBC
V
RST output voltage I(RST) = 1 mA 0.4
BW output voltage I(BW)= 1 mA 0.4
Input leakage current on A and CE pins −1 1 µA
Voh CEcon1,2 Ioh = 0.5 mA 2.4
Vol CEcon1,2 Iol = 2.0 mA 0.4 V
Battery warning level VBW (1) 0.677xVCC
V
Capacitance
Output capacitance VOUT = 0 V 7
pF
Input capacitance VOUT = 0 V 5pF
Power-Down and Power-Up Timing, Refer to Figure 1 through 3
VCC slew rate fall time, tF3.0 V to 0.0 V 300
s
VCC slew rate rise time, tRVSO to VPFD(max) 100 µs
VPFD to RST active, tRST
(reset active timeout period) 30 85
ms
Chip-enable recovery time, tCER (2) 30 85
ms
Chip-enable propagation delay time to external
SRAM, tCED See Figure 2 15 25 ns
Push-button low time, tPBL RST pin 1µs
(1) Battery warning level is detected on power up and the BW pin is latched at tCER time after VCC passes through VPFD on power up.
(2) Time during which external SRAM is write protected after VCC passes through VPFD on power up.
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AC TEST CONDITIONS, INPUT PULSE LEVELS 0 V ≤ VIN ≤ 3 V, tR = tF = 5 NS
Figure 1. Output Load
CL
TTL
(including scope
and JIG)
CECONX
VCC
VCC
VPFD
VSO
tF
VSO
VPFD
VPFD(max)
tR
CE
CECONX
tCED
tRST
tCER tCED
RST
Figure 2. Power-Down/Power-Up Timing Diagram
VPBRL
RST tPBL tRST
VPBRH
Figure 3. Push-Button Reset Timing
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TERMINAL FUNCTIONS
NAME
TERMINAL
I/O
DESCRIPTION
NAME
bq2205LY
I/O
DESCRIPTION
A 1 I SRAM bank select input
BCP9 I Backup supply input
BW 15 O Battery warning output (open-drain)
CE 11 IChip enable input (active low)
CECON1 10 O Conditioned chip enable output 1
CECON2 14 O Conditioned chip enable output 2
N/C 2, 3, 6, 7 −No connect. These pins must be left floating.
RST 16 O Power-up reset to system CPU output (open-drain)
VCC 12 I Main supply input
VOUT 13 O SRAM supply output
VSS 4, 5, 8 −Ground input
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
N/C
N/C
VSS
VSS
N/C
N/C
VSS
RST
BW
CECON2
VOUT
VCC
CE
CECON1
BCP
PW PACKAGE
(TOP VIEW)
N/C no connection
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FUNCTIONAL DESCRIPTION
Two banks of CMOS static RAM can be battery-backed using the VOUT and conditioned chip-enable output
pins from the bq2205. As the voltage input VCC slews down during a power failure, the two-conditioned chip
enable outputs, CECON1 and CECON2, are forced inactive independent of the chip enable input, CE. This activity
unconditionally write-protects the external SRAM as VCC falls to an out-of-tolerance threshold VPFD. As the
supply continues to fall past VPFD, an internal switching device forces VOUT to the backup energy source.
CECON1 and CECON2 are held high by the VOUT energy source.
During power-up, VOUT is switched back to the 3.3-V supply as VCC rises above the backup cell input voltage
sourcing VOUT. Outputs CECON1 and CECON2 are held inactive for time tCER after the power supply has reached
VPFD, independent of the CE input, to allow for processor stabilization.
During power-valid operation, the CE input is passed through to one of the two CECONx outputs with a
propagation delay of less than tCED. The CE input is output on one of the two CECONx output pins; depending
on the level of bank select input A. See truth table below.
Table 1. Truth Table
INPUT OUTPUT
CE A CECON1 CECON2
H x H H
L L L H
L H H L
Bank select input A is usually tied to a high-order address pin so that a large nonvolatile memory can be
designed using lower-density memory devices. Non-volatility and decoding are achieved by hardware hookup
as shown in the application diagram.
The RST output can be used as the power-on reset for a microprocessor . Access to the external RAM may begin
when RST returns inactive.
BATTERY BACKUP INPUT
Backup energy source, BCP, input is provided on the bq2205 for use with an external primary cell. The primary
cell input is designed to accept any 3-V primary battery (non-rechargeable), typically some type of lithium
chemistry.
Power-Down and Power-Up Cycle
The bq2205 continuously monitors VCC for out-of-tolerance. During a power failure, when VCC falls below
VPFD, the bq2205 write-protects the external SRAM. The power source is switched to BCP when VCC is less
than V PFD and BCP is greater than VPFD, or when VCC is less than BCP and BCP is less than VPFD. When VCC
is above VPFD, the power source is VCC. Write-protection continues for tCER time after VCC rises above VPFD.
An external CMOS static RAM is battery-backed using the VOUT and chip enable output pins from the bq2205.
As the voltage input VCC slews down during a power failure, the chip enable output, CECONx, is forced inactive
independent of the chip enable input CE.
As the supply continues to fall past VPFD, an internal switching device forces VOUT to the external backup
energy source. CECONx is held high by the VOUT energy source.
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FUNCTIONAL DESCRIPTION
During power up, VOUT is switched back to the main supply as VCC rises above the backup cell input voltage
sourcing VOUT. If VPFD < BCP on the bq2205 the switch to the main supply occurs at VPFD. CECONx is held
inactive for time tCER after the power supply has reached VPFD, independent of the CE input, to allow for
processor stabilization.
Power-On Reset
The bq2205 provides a power-on reset, which pulls the RST pin low on power down and remains low on power
up for tRST after VCC passes VPFD. With valid battery voltage on BCP, RST remains valid for VCC = VSS. The
pull-up resistor on this pin should not exceed 10 kΩ if a push button reset is used.
Battery Low Warning
The bq2205 checks the battery voltage on power-up. The threshold for the battery warning comparator is VBW,
and a low level is sensed after power valid on each power up and latched after tCER time. The latched value
is presented at BW pin where a low indicates a low battery.
APPLICATION INFORMATION
PCB LAYOUT INFORMATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
DTo obtain optimal performance, the decoupling capacitor from input terminals to VSS should be placed as
close as possible to the bq2205, with short trace runs to both signal and VSS pins.
DAll low-current VSS connections should be kept separate from the high-current paths from the inputs
supplies. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
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MECHANICAL DATA
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°−ā8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
BQ2205LYPW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
BQ2205LYPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
BQ2205LYPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
BQ2205LYPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ2205LYPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ2205LYPWR TSSOP PW 16 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2009
Pack Materials-Page 2
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