©2009 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
SPM
October 2009
TM
FSB67508
Smart Power Module (SPM®)
Features
•R
DS(ON).MAX=11mΩ @ ID=38A,TJ=25°C a half-bridge FRFET
inverter including high voltage integrated circuit (HVIC)
Negative dc-link terminals for inverter current sensing appli-
cations
HVIC for gate driving and protection functions
3/5V CMOS/TTL compatible, active-high interface
Isolation voltage rating of 1500Vrms for 1min.
Embedded bootstrap diode in the package
General Description
FSB67508 is a smart power module (SPM®) as a compact
solution for small power motor drive applications such as E-
bike. It is composed of 2 MOSFET, and 1 half-bridge HVIC for
gate driving. This offers an extremely compact, high
performance half-bridge inverter in a single isolated package .
The package is optimized for the thermal performance and
compactness for the use in the built-in motor application and
any other application where the assembly space is concerned.
Absolute Maximum Ratings
*Repetitive rating : Pulse width limited by maximum junction temperature
Symbol Parameter Conditions Rating Units
VPN DC Link Input Voltage,
Drain-source Voltage of each FET 75 V
ID25 Each FET Drain Current, Continuous TC = 25°C 38 A
ID80 Each FET Drain Current, Continuous TC = 80°C 28 A
IDP Each FET Drain Current, Peak TC = 25°C, Pulsed* 95 A
PDMaximum Power Dissipation TC = 25°C, Each 32 W
VCC Control Supply Voltage Applied between VCC and COM 20 V
VBS High-side Bias Voltage Applied between VB and U 20 V
VIN Input Signal Voltage Applied between IN and COM -0.3 ~ VCC V
TJOperating Junction Temperature -40 ~ 150 °C
TSTG Storage Temperature -50 ~ 150 °C
RθJC Junction to Case Therma l Resistance Each under inverter operating condition
(Note 1) 3.9 °C/W
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FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
Pin Descriptions
Note:
Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in
Figure2.
Figure 1. Internal Block Diagram
Pin Number Pin Name Pin Description
1 P Positive DC–Link Input
2VS Bias Voltage Ground for High Side MOSFET Driving
3VB High-side Bias Voltage for MOSFET Driving
4VCC Bias Voltage for IC and Low side MOSFET Driving
5 HIN Signal Input for High-side
6LIN Signal Input for Low-side
7COM Common Supply Ground
8NC No connection
9 N Negative DC-Link Input
10 UOutput
COM
VCC
LIN
HIN
VB
HO
LO
(4) VCC
(5) HIN
(6) LIN
(1) P
(10) U
(9) N
(7) COM
(3) VB
VS
NC(8) NC
(2) VS
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FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Inverter Part (Each MOSFET Unless Otherwise Specified)
Control Part (Each HVIC Unless Otherwise Specified)
Note:
1. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FET inside SPM®. VPN sho uld be sufficiently less than this value considering the
effect of the stray inductance so that VDS should not exceed BVDSS in any case.
2. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 3 for the switching time definition with the switching test circuit of Figure 4.
3. The peak current and vol t a ge of ea ch FET dur i ng the switching opera tion sh oul d be incl u ded in the safe o per a ti ng a re a (SOA ). Please see Figure 4 for the RBSOA test circuit
that is same as the switching test circuit.
Package Marking & Ordering Information
Symbol Parameter Conditions Min Typ Max Units
BVDSS Drain-Source Breakdown
Voltage VIN= 0V, ID = 250μA (Note 2) 75 - - V
ΔBVDSS/
ΔTJ
Breakdown Voltage Tem-
perature Coefficient ID = 250μA, Referenced to 25°C -0.6 - V
IDSS Zero Gate Voltage
Drain Current VIN= 0V, VDS = 75V - - 250 μA
RDS(on) Static Drain-Source
On-Resistance VCC = VBS = 15V, VIN = 5V, ID = 15A -9.4 11 mΩ
VSD Drain-Source Diode
Forward Voltage VCC = VBS = 15V, VIN = 0V, ID = 15A - - 1.2 V
tON
Switching Times
VPN = 48V, VCC = VBS = 15V, ID = 15A
VIN = 0V 5V
Inductive load L=3mH
High- and low-side FET switching
(Note 3)
-550 -ns
tOFF -2000 -ns
trr -100 -ns
EON -40 -μJ
EOFF -190 -μJ
RBSOA Reverse-bias Safe Oper-
ating Area
VPN = 55V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS,
TJ = 150°C
High- and low-side FET switching (Note 3) Full Square
Symbol Parameter Conditions Min Typ Max Units
IQCC Quiescent VCC Current VCC=15V, VIN=0V Applied between VCC and COM - - 160 μA
IQBS Quiescent VBS Current VBS=15V, VIN=0V Applied between VB(U)-U,
VB(V)-V, VB(W)-W - - 100 μA
UVCCD Low-side Undervoltage
Protection (Figure 6) VCC Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVCCR VCC Undervoltage Protection Reset Level 8.0 8.9 9.8 V
UVBSD High-side Undervoltage
Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVBSR VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V
VIH ON Threshold Voltage Logic High Level Applied between IN and COM 3.0 - - V
VIL OFF Threshold Voltage Logic Low Level - - 0.8 V
IIH Input Bias Current VIN = 5V Applied between IN and COM -10 20 μA
IIL VIN = 0V - - 2 μA
Device Marking Device Package Reel Size Tape Width Quantity
FSB67508 FSB67508 SPM10-AA _ _ 19
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FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
Recommended Operating Conditions
Note:
(1) The snubber capacitor, C3, should be placed near SPM®
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of paramete rs is sho wn above .
(3) RC coupling (R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM® is compatible with
standard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
Bootstrap Diode Part
Symbol Parameter Conditions Value Units
Min. Typ. Max.
VPN Supply Voltage Applied between P and N -48 60 V
VCC Control Supply Voltage Applied between VCC and COM 13.5 15 16.5 V
VBS High-side Bias Voltage Applied between VB and output 13 15 16.5 V
VIN(ON) Input ON Threshold Voltage Applied between IN and COM 3.0 -VCC V
VIN(OFF) Input OFF Threshold Voltage 0 - 0.6 V
tdead Blanking Time for Preventing
Arm-short VCC=VBS=13.5 ~ 20V, TJ 150°C 1.0 - - μs
fPWM PWM Switching Frequency TJ 150°C -15 -kHz
Symbol Parameter Conditions Rating Units
VRRM Maixmum Repetitive Reverse Voltage 75 V
IFForward Current TC = 25°C 0.5 A
IFP Forward Current (Peak) TC = 25°C, Under 1ms Pulse Width 2 A
TJOperating Junction Temperature -40 ~ 150 °C
RBEquivalent Bootstrap Resistance TC = 25°C 15 Ω
R3
Inverter
Output
C3
C1
Micom
15-V
Line
10μF
These values depend on
PWM control algorithm
* Example of bootstrap paramters:
C 1 = C2 = 1μF ceramic capacitor,
R5
C5
VDC
C2
COM
VCC
LIN
HIN
VB
HO
LO
P
U
N
VS
NC
VS P
N
HIN LIN
0 0
0 1
1 0
1 1
Open Open
Output
Z
0
VDC
Forbidden
Z
Note
B o th FET O ff
Low -side FET O n
High-side FET On
Shoot-through
S a me a s (0 , 0 )
FO
1
1
1
1
1
x x Z Same as (0, 0)
0
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FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
Figure 3. Switching Time Definition
Figure 4. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Figure 5. Undervoltage Prot ection (Low-side)
Figure 6. Undervoltage Protection (High-side)
tON trr
Irr
100% of ID120% of ID
(a) Turn -on
tOFF
(b) Tu rn -o ff
ID
VDS
VDS
ID
VIN VIN
10% of ID
ID
VCC
LVDC
+
VDS
-
COM
VCC
LIN
HIN
VB
HO
LO
P
U
N
VS
NC
VS
CBS
O ne-le g Diagram of SP M
UVCCD
UVCCR
Input Signal
UV Protection
Status
Low-side Supply, VCC
MOSFET Current
RESET DETECTION RESET
UVBSD
UVBSR
Input Signal
UV Protection
Status
High-si de Supply, VBS
MOSFET Current
RESET DETECTION RESET
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FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
Fig. 7. Example of Application Circuit
Note:
Built in bootstrap diode includes around 15resistance characteristic.
Figure 8. Built in Bootstrap Diode Characteristics
(4) VCC
(5) HIN
(6) LIN
(1) P
(7) CO M
(3) VB
(8) NC
(10) U
(9) N
COM
VCC
LIN
HIN
VB
HO
LO
VS
NC
(2) VS
(4) VCC
(5) HIN
(6) LIN
(1) P
(7) CO M
(3) VB
(8) NC
(10) V
(9) N
COM
VCC
LIN
HIN
VB
HO
LO
VS
NC
(2) VS
(4) VCC
(5) HIN
(6) LIN
(1) P
(7) CO M
(3) VB
(8) NC
(10) W
(9) N
COM
VCC
LIN
HIN
VB
HO
LO
VS
NC
(2) VS
Micom
M
C3VDC
R3
R4
C4
R5
C5
For 3-phase current sensing and protection
C2
C2
C2
+15V
Supply
0123456789101112131415
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0 Built in Bootstrap Dio d e VF-IF Characteristic
TC=25
IF [A]
VF [V]
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FSB67508 Rev. A
FSB67508 Smart Power Module (SPM®)
Detailed Package Outline Drawings
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
AccuPower
Auto-SPM
Build it Now
CorePLUS
CorePOWER
CROSSVOLT
CTL™
Current Transfer Logic™
EcoSPARK®
EfficentMax™
EZSW ITCH™*
™*
®
Fairchild®
Fairchild Semiconductor®
FACT Quiet Series™
FACT®
FAST®
FastvCore
FETBench
FlashWriter®*
FPS
F-PFS
FRFET®
Global Power ResourceSM
Green FPS
Green FPS e-Series
Gmax
GTO
IntelliMAX
ISOPLANAR
MegaBuck™
MICROCOUPLER
MicroFET
MicroPak
MillerDrive™
MotionM ax
Motion-SPM™
OPTOLOGIC®
OPTOPLANAR®
®
PDP SPM™
Power-SPM
PowerTrench®
PowerXS™
Programmable Active Droop
QFET®
QS
Quiet Series
RapidConfigure
Saving our world, 1mW/W/kW at a time™
SmartMax™
SMART START
SPM®
STEALTH™
SuperFET
SuperSOT-3
SuperSOT-6
SuperSOT-8
SupreMOS™
SyncFET™
Sync-Lock™ ®*
The Power Franchise®
TinyBoost
TinyBuck
TinyCalc
TinyLogic®
TINYOPTO
TinyPower
TinyPWM
TinyWire
TriFault Detect
TRUECURRENT*
μSerDes
UHC®
Ultra FRFET
UniFET
VCX
VisualMax
XS™
* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
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The datasheet is for reference information only. Rev. I41