16-Bit 100 kSPS PulSARTM
Unipolar ADC with Reference
AD7651
FEATURES
Throughput: 100 kSPS
16-bit resolution
Analog input voltage range: 0 V to 2.5 V
No pipeline delay
Parallel and serial 5 V/3 V interface
SPI®/QSPITM/MICROWIRETM/DSP compatible
Single 5 V supply operation
Power dissipation
16 mW typ, 160 µW @ 1 kSPS without REF
38 mW typ with REF
48-lead LQFP and 48-lead LFCSP packages
Pin-to-pin compatible with PulSAR ADCs
APPLICATIONS
Data acquisition
Instrumentation
Digital signal processing
Spectrum analysis
Medical instruments
Battery-powered systems
Process control
GENERAL DESCRIPTION
The AD7651 is a 16-bit, 100 kSPS, charge redistribution SAR
analog-to-digital converter that operates from a single 5 V
power supply. The part contains a high speed 16-bit sampling
ADC, an internal conversion clock, internal reference, error
correction circuits, and both serial and parallel system inter-
face ports.
The AD7651 is fabricated using Analog Devices’ high perform-
ance, 0.6 micron CMOS process, with correspondingly low cost,
and is available in a 48-lead LQFP and a tiny 48-lead LFCSP
with operation specified from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
02964-0-001
SWITCHED
CAP DAC
16
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
CLOCK
AD7651
DATA[15:0]
BUSY
RD
CS
SER/P A R
OB/2C
OGND
OVDD
DGNDDVDD
AVDD
AGND
REF REFGND
IN
INGND
PD
RESET
SERIAL
PORT
PARALLEL
INTERFACE
CNVST
REF
REFBUFIN
PDBUF
PDREF
BYTESWAP
Figure 1. Functional Block Diagram
Table 1. PulSAR Selection
Type/kSPS 100–250 500–570
800–
1000
Pseudo-
Differential
AD7651
AD7660/AD7661
AD7650/AD7652
AD7664/AD7666
AD7653
AD7667
True Bipolar AD7663 AD7665 AD7671
True
Differential
AD7675 AD7676 AD7677
18-Bit AD7678 AD7679 AD7674
Multichannel/
Simultaneous
AD7654
AD7655
PRODUCT HIGHLIGHTS
1. Fast Throughput.
The AD7651 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Internal Reference.
The AD7651 has an internal reference with a typical
temperature drift of 7 ppm/°C.
3. Single-Supply Operation.
The AD7651 operates from a single 5 V supply. Its power
dissipation decreases with throughput.
4. Serial or Parallel Interface.
Versatile parallel or 2-wire serial interface arrangement is
compatible with both 3 V and 5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
AD7651
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
Definitions of Specifications ......................................................... 11
Typical Performance Characteristics ........................................... 12
Circuit Information........................................................................ 15
Converter Operation.................................................................. 15
Typical Connection Diagram.................................................... 17
Power Dissipation versus Throughput .................................... 19
Conversion Control.................................................................... 19
Digital Interface .......................................................................... 20
Parallel Interface......................................................................... 20
Serial Interface ............................................................................ 20
Master Serial Interface............................................................... 21
Slave Serial Interface .................................................................. 22
Microprocessor Interfacing....................................................... 24
Application Hints............................................................................ 25
Bipolar and Wider Input Ranges.............................................. 25
Layout .......................................................................................... 25
Evaluating the AD7651’s Performance .................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide........................................................................... 26
REVISION HISTORY
Revision 0, Initial Version.
Rev. 0 | Page 2 of 28
AD7651
SPECIFICATIONS
Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range VIN – VINGND 0 VREF V
Operating Input Voltage VIN –0.1 +3 V
V
INGND –0.1 +0.5 V
Analog Input CMRR fIN = 10 kHz 65 dB
Input Current 100 kSPS Throughput 1.1 µA
Input Impedance1
THROUGHPUT SPEED
Complete Cycle 10 µs
Throughput Rate 0 100 kSPS
DC ACCURACY
Integral Linearity Error –6 +6 LSB2
No Missing Codes 15 Bits
Differential Linearity Error –2 +3 LSB
Transition Noise 0.7 LSB
Unipolar Zero Error, TMIN to TMAX3 ±5 LSB
Unipolar Zero Error Temperature Drift3 ±0.25 ppm/°C
Full-Scale Error, TMIN to TMAX 3 REF = 2.5 V ±0.12 % of FSR
Full-Scale Error Temperature Drift ±0.6 ppm/°C
Power Supply Sensitivity AVDD = 5 V ± 5% ±2 LSB
AC ACCURACY
Signal-to-Noise fIN = 45 kHz 86 dB4
Spurious Free Dynamic Range fIN = 45 kHz 98 dB
Total Harmonic Distortion fIN = 10 kHz –98 dB
f
IN = 45 kHz –98 dB
Signal-to-(Noise + Distortion) fIN = 45 kHz 86 dB
–60 dB Input, fIN = 45 kHz 30 dB
–3 dB Input Bandwidth 800 kHz
SAMPLING DYNAMICS
Aperture Delay 2 ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 8.75 µs
REFERENCE
Internal Reference Voltage VREF @ 25°C 2.48 2.5 2.52 V
Internal Reference Temperature Drift –40°C to +85°C ±7 ppm/°C
Line Regulation AVDD = 5 V ± 5% ±24 ppm/V
Turn-On Settling Time CREF = 10 µF 5 ms
Temperature Pin
Voltage Output @ 25°C 300 mV
Temperature Sensitivity 1 mV/°C
Output Resistance 4.3 kΩ
External Reference Voltage Range 2.3 2.5 AVDD – 1.85 V
External Reference Current Drain 100 kSPS Throughput 35 µA
Rev. 0 | Page 3 of 28
AD7651
Parameter Conditions Min Typ Max Unit
DIGITAL INPUTS
Logic Levels
VIL –0.3 +0.8 V
VIH 2.0 DVDD + 0.3 V
IIL –1 +1 µA
IIH –1 +1 µA
DIGITAL OUTPUTS
Data Format5
Pipeline Delay6
VOL I
SINK = 1.6 mA 0.4 V
VOH I
SOURCE = –500 µA OVDD – 0.6 V
POWER SUPPLIES
Specified Performance
AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.257 V
Operating Current 100 kSPS Throughput
AVDD8 With Reference and Buffer 6.2 mA
AVDD9 Reference and Buffer Alone 3 mA
DVDD10 1.5 mA
OVDD10 18 µA
Power Dissipation without REF10 100 kSPS Throughput 16 25 mW
1 kSPS Throughput 160 µW
Power Dissipation with REF10 100 kSPS Throughput 38 45 mW
TEMPERATURE RANGE11
Specified Performance TMIN to TMAX –40 +85 °C
1See section. Analog Input
2LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV.
3See section. These specifications do not include the error contribution from the external reference. Definitions of Specifications
4All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.
5Parallel or Serial 16-Bit.
6Conversion results are available immediately after completed conversion.
7 The max should be the minimum of 5.25 V and DVDD + 0.3 V.
8 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH.
9 With PDREF, PDBUF LOW and PD HIGH.
10 Tested in Parallel Reading Mode
11Consult factory for extended temperature range.
Rev. 0 | Page 4 of 28
AD7651
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted
Parameter Symbol Min Typ Max Unit
Refer to Figure 26 and Figure 27
Convert Pulse Width t1 10 ns
Time between Conversions t2 10 µs
CNVST LOW to BUSY HIGH Delay t3 35 ns
BUSY HIGH All Modes Except Master Serial Read after Convert t4 1.25 µs
Aperture Delay t5 2 ns
End of Conversion to BUSY LOW Delay t6 10 ns
Conversion Time t7 1.25 µs
Acquisition Time t8 8.75 µs
RESET Pulse Width t9 10 ns
Refer to Figure 28, Figure 29, and (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t10 1.25 µs
DATA Valid to BUSY LOW Delay t11 12 ns
Bus Access Request to DATA Valid t12 45 ns
Bus Relinquish Time t13 5 15 ns
Refer to Figure 32 and Figure 33 (Master Serial Interface Modes)1
CS LOW to SYNC Valid Delay t14 10 ns
CS LOW to Internal SCLK Valid Delay1 t15 10 ns
CS LOW to SDOUT Delay t16 10 ns
CNVST LOW to SYNC Delay t17 525 ns
SYNC Asserted to SCLK First Edge Delay t18 3 ns
Internal SCLK Period2 t19 25 40 ns
Internal SCLK HIGH2 t20 12 ns
Internal SCLK LOW2 t21 7 ns
SDOUT Valid Setup Time2 t22 4 ns
SDOUT Valid Hold Time2 t23 2 ns
SCLK Last Edge to SYNC Delay2 t24 3 ns
CS HIGH to SYNC HI-Z t25 10 ns
CS HIGH to Internal SCLK HI-Z t26 10 ns
CS HIGH to SDOUT HI-Z t27 10 ns
BUSY HIGH in Master Serial Read after Convert2 t28 See Table 4
CNVST LOW to SYNC Asserted Delay t29 1.25 µs
SYNC Deasserted to BUSY LOW Delay t30 25 ns
Refer to and (Slave Serial Interface Modes)1
External SCLK Setup Time t31 5 ns
External SCLK Active Edge to SDOUT Delay t32 3 18 ns
SDIN Setup Time t33 5 ns
SDIN Hold Time t34 5 ns
External SCLK Period t35 25 ns
External SCLK HIGH t36 10 ns
External SCLK LOW t37 10 ns
Figure 30
Figure 34 Figure 35
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert Mode. See Table 4 for serial master read after convert mode.
Rev. 0 | Page 5 of 28
AD7651
Table 4. Serial Clock Timings in Master Read after Convert
DIVSCLK[1] 0 0 1 1
DIVSCLK[0] Symbol 0 1 0 1 Unit
SYNC to SCLK First Edge Delay Minimum t18 3 17 17 17 ns
Internal SCLK Period Minimum t19 25 50 100 200 ns
Internal SCLK Period Maximum t19 40 70 140 280 ns
Internal SCLK HIGH Minimum t20 12 22 50 100 ns
Internal SCLK LOW Minimum t21 7 21 49 99 ns
SDOUT Valid Setup Time Minimum t22 4 18 18 18 ns
SDOUT Valid Hold Time Minimum t23 2 4 30 80 ns
SCLK Last Edge to SYNC Delay Minimum t24 3 55 130 290 ns
BUSY HIGH Width Maximum t24 2 2.5 3.5 5.75 µs
Rev. 0 | Page 6 of 28
AD7651
ABSOLUTE MAXIMUM RATINGS
Table 5. AD7651 Stress Ratings1
IN2, TEMP2,REF, REFBUFIN,
INGND, REFGND to AGND
AVDD + 0.3 V to
AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND ±0.3 V
Supply Voltages
AVDD, DVDD, OVDD –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD ±7 V
DVDD to OVDD –0.3 V to +7 V
Digital Inputs –0.3 V to DVDD + 0.3 V
PDREF, PDBUF3 ±20 mA
Internal Power Dissipation4 700 mW
Internal Power Dissipation5 2.5 W
Junction Temperature 150°C
Storage Temperature Range –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec)
300°C
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
2See section.
3See section.
4Specification is for the device in free air:
48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W
5Specification is for the device in free air:
48-Lead LFCSP; θJA = 26°C/W.
Analog Input
Voltage Reference Input
I
OH
500µA
1.6mA I
OL
TO OUTPUT
PIN 1.4V
C
L
60pF*
* IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
02964-0-006
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs CL = 10 pF
0.8V
2V
2V
0.8V
0.8V
2V
tDELAY tDELAY
02965-0-007
Figure 3. Voltage Reference Levels for Timing
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD7651
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44 39 38 3743 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
AGND
AVDD
NC
BYTESWAP
OB/2C
NC
NC
NC = NO CONNECT
SER/PAR
D0
D1
BUSY
D15
D14
D13
AD7651
D3/DIVSCLK1 D12
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
PDBUF
PDREF
REFBUFIN
TEMP
AVDD
IN
AGND
AGND
NC
INGND
REFGND
REF
02965-0-002
D2/DIVSCLK0
Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48)
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1, 36,
41, 42
AGND P Analog Power Ground Pin.
2, 44 AVDD P Input Analog Power Pin. Nominally 5 V.
3, 6,
7, 40
NC No Connect.
4 BYTESWAP DI Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on
D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;
when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift
register.
8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial
interface mode is selected and some bits of the DATA bus are used as a serial port.
9, 10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high
impedance.
11, 12 D[2:3]or
DIVSCLK[0:1]
DI/O When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.
When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),
these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that
clocks the data output. In other serial modes, these pins are not used.
13 D4 or
EXT/INT
DI/O When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing
the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected
on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input.
14 D5 or
INVSYNC
DI/O When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC
signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
15 D6 or
INVSCLK
DI/O When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active
in both master and slave modes.
Rev. 0 | Page 8 of 28
AD7651
Pin No. Mnemonic Type1 Description
16 D7 or
RDC/SDIN
DI/O When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA
with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data
is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.
17 OGND P Input/Output Interface Digital Power Ground.
18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V).
19 DVDD P Digital Power. Nominally at 5 V.
20 DGND P Digital Power Ground.
21 D8 or
SDOUT
DO When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7651 provides the
conversion result, MSB first, from its internal shift register. The DATA format is determined by the
logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In
serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and
valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and
valid on the next rising edge.
22 D9 or
SCLK
DI/O When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
23 D10 or
SYNC
DO When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW
while the SDOUT output is valid.
24 D11 or
RDERROR
DO When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When
SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error
flag. In slave mode, when a data read is started and not complete when the following conversion is
complete, the current data is lost and RDERROR is pulsed HIGH.
25–28 D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
state of SER/PAR.
29 BUSY DO Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is
complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
30 DGND P Must Be Tied to Digital Ground.
31 RD DI Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32 CS DI Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock.
33 RESET DI Reset Input. When set to a logic HIGH, this pin resets the AD7651 and the current conversion, if any,
is aborted. If not used, this pin could be tied to DGND.
34 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
35 CNVST DI Start Conversion. If CNVST is HIGH when the acquisition phase (t8) is complete, the next falling edge
on CNVST puts the internal sample/hold into the hold state and initiates a conversion. The mode is
most appropriate if low sampling jitter is desired. If CNVST is LOW when the acquisition phase (t8) is
complete, the internal sample/hold is put into the hold state and a conversion is immediately
started.
37 REF AI/O Reference Input Voltage. On-chip reference output voltage.
38 REFGND AI Reference Input Analog Ground.
39 INGND AI Analog Input Ground.
Rev. 0 | Page 9 of 28
AD7651
Pin No. Mnemonic Type1 Description
43 IN AI Primary Analog Input with a Range of 0 V to 2.5 V.
45 TEMP AO Temperature Sensor Voltage Output.
46 REFBUFIN AI/O Reference Input Voltage. The reference output and the reference buffer input.
47 PDREF DI This pin allows the choice of internal or external voltage references. When LOW, the on-chip
reference is turned on. When HIGH, the internal reference is switched off and an external reference
must be used.
48 PDBUF DI This pin allows the choice of buffering an internal or external reference with the internal buffer.
When LOW, the buffer is selected. When HIGH, the buffer is switched off.
1AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.
Rev. 0 | Page 10 of 28
AD7651
DEFINITIONS OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Full-Scale Error
The last transition (from 011…10 to 011…11 in twos
complement coding) should occur for an analog voltage 1½ LSB
below the nominal full scale (2.49994278 V for the 0 V to 2.5 V
range). The full-scale error is the deviation of the actual level of
the last transition from the ideal level.
Unipolar Zero Error
The first transition should occur at a level ½ LSB above analog
ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero
error is the deviation of the actual transition from that point.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number Of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the AD7651 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Overvoltage Recovery
Overvoltage recovery is the time required for the ADC to
recover to full accuracy after an analog input signal 150% of the
full-scale value is reduced to 50% of the full-scale value.
Reference Voltage Temperature Coefficient
Reference voltage temperature coefficient is the change of
internal reference voltage output voltage V over the operating
temperature range and normalized by the output voltage at
25°C, expressed in ppm/°C. The equation follows:
6
12
12 10
)–()C25(
)(–)(
)/( ×
×°
=° TTV
TVTV
CppmTCV
where:
V(25°C) = V at +25°C
V(T2) = V at Temperature 2 (+85°C)
V(T1) = V at Temperature 1 (–40°C)
Rev. 0 | Page 11 of 28
AD7651
Rev. 0 | Page 12 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL (LSB)
0
–4
–3
–1
–2
0
3
2
1
4
16384 32768 65536
49152
02964-0-026
Figure 5. Integral Nonlinearity vs. Code
CODE IN HEX
COUNTS
7FFB
0
20000
60000
40000
80000
140000
120000
8000 8001 80038002
02964-0-027
80047FFC 7FFD 7FFE 7FFF
100000
10822
00 00
137
479
20890
114686
114156
Figure 6. Histogram of 261,120 Conversions of a
DC Input at the Code Transition
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
0
–180
–160
–120
–140
–100
–60
–80
0
20 30 5040
02964-0-029
10
–40
–20
fS = 100kSPS
fIN = 45.7kHz
SNR = 86.7dB
THD = 102.5dB
SFDR = 103.6dB
S/[N+D] = 86.6dB
Figure 7. FFT Plot
CODE
DNL (LSB)
0
–1.0
–0.5
0
1.5
1.0
0.5
2.0
16384 32768 65536
49152
02964-0-023
Figure 8. Differential Nonlinearity vs. Code
CODE IN HEX
COUNTS
0
20000
80000
40000
100000
180000
120000
8000 8001 80038002
02964-0-028
80047FFC 7FFD 7FFE 7FFF
019
2896 1903 50
60000
155528
49184
51585
140000
160000
Figure 9. Histogram of 261,120 Conversions of a
DC Input at the Code Center
FREQUENCY (kHz)
SNR, S/[N+D] (dB)
1
80
85
87
86
88
90
100
02964-0-030
1000
10
89
ENOB (Bits)
15.5
13.0
13.5
14.0
14.5
15.0
ENOB
SNR
S/[N+D]
81
83
82
84
Figure 10. SNR, S/(N+D), and ENOB vs. Frequency
AD7651
Rev. 0 | Page 13 of 28
FREQUENCY (kHz)
THD, HARMONICS (dB)
1
–120
–100
–90
–70
100
02964-0-031
1000
10
–80
SFDR (dB)
120
100
20
40
60
80
SECOND
HARMONIC
SFDR
THIRD
HARMONIC
THD
110
90
30
50
70
–105
–95
–75
–85
–115
–110
Figure 11. THD, Harmonics, and SFDR vs. Frequency
INPUT LEVEL (dB)
SNR, S/[N+D] REFERRED TO FULL SCALE (dB)
–60
85
90
02964-0-032
0–50 –40 –30 –20 –10
86
87
88
89
SNR
S/[N+D]
Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale)
15.5
13.5
14.0
14.5
15.0
TEMPERATURE (dB)
SNR, S/[N+D] (dB)
–55
85
89
02964-0-033
125–35 –15 5 25 45
86
87
88
SNR
65 10585
S/[N+D]
ENOB (Bits)
Figure 13. SNR, S/(N+D), and ENOB vs. Temperature
TEMPERATURE (°C)
THD, HARMONICS (dB)
–55
–120
–100
02964-0-034
125–35 –15 25 45 65
–115
–105
SECOND
HARMONIC
585
105
THIRD
HARMONIC
THD
–110
Figure 14. THD and Harmonics vs. Temperature
SAMPLE RATE (SPS)
02964-0-035
100 10000 100000
1
100
1000
10
1000
10000
0.001
0.1
0.01
OPERATING CURRENT (µA)
DVDD
PDREF = PDBUF = HIGH
10
AVDD
OVDD
Figure 15. Operating Current vs. Sample Rate
TEMPERATURE (°C)
ZERO ERROR, FULL SCALE (LSB)
–55
6
02964-0-036
–35 5 25 45 65–15 85 125
4
5
2
3
0
1
–4
–3
–6
–5
105
FULL SCALE
ZERO ERROR
–2
–1
Figure 16. Zero Error, Full Scale with Reference vs. Temperature
AD7651
Rev. 0 | Page 14 of 28
TEMPERATURE (°C)
VREF (V)
–40
2.5042
02964-0-037
0204060–20 80 120
2.5028 100
2.5030
2.5032
2.5034
2.5036
2.5038
2.5040
Figure 17. Typical Reference Output Voltage vs. Temperature
REFERENCE DRIFT (ppm/°C)
NUMBER OF UNITS
–30
0
10
25
02965-0-040
–26 –22 –18 –14
15
–10 –6 –2 2 3026221814106
5
20
Figure 18. Reference Voltage Temperature Coefficient Distribution (100 Units)
C
L
(pF)
t
12
DELAY (ns)
0
0
50
02964-0-039
20050 100 150
10
30
40
20 OVDD = 5V @ 25°C
OVDD = 5V @ 85°C
OVDD = 2.7V @ 25°C
OVDD = 2.7V @ 85°C
Figure 19. Typical Delay vs. Load Capacitance CL
AD7651
CIRCUIT INFORMATION
SW
A
COMP
SW
B
IN
REF
REFGND
LSB
MSB
32,768C
INGND
16,384C 4C 2C C C
65,536C
CONTROL
LOGIC
SWITCHES
CONTROL
BUSY
OUTPUT
CODE
02964-0-005
CNVST
Figure 20. ADC Simplified Schematic
igure 20
The AD7651 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC).
During the acquisition phase, the common terminal of the array
tied to the comparator's positive input is connected to AGND
via SWA. All independent switches are connected to the analog
input IN. Thus, the capacitor array is used as a sampling
capacitor and acquires the analog signal on IN. Similarly, the
dummy capacitor acquires the analog signal on INGND.
The AD7651 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any
pipeline or latency, making it ideal for multiple multiplexed
channel applications.
When CNVST goes LOW, a conversion phase is initiated. When
the conversion phase begins, SWA and SWB are opened. The
capacitor array and dummy capacitor are then disconnected
from the inputs and connected to REFGND. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs,
causing the comparator to become unbalanced. By switching
each element of the capacitor array between REFGND and REF,
the comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4, …VREF/65536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition.
The AD7651 can be operated from a single 5 V supply and can
be interfaced to either 5 V or 3 V digital logic. It is housed in
either a 48-lead LQFP or a 48-lead LFCSP that saves space and
allows flexible configurations as either a serial or parallel inter-
face. The AD7651 is pin-to-pin compatible with PulSAR ADCs.
CONVERTER OPERATION
The AD7651 is a successive-approximation ADC based on a
charge redistribution DAC. F shows a simplified sche-
matic of the ADC. The capacitive DAC consists of an array of 16
binary weighted capacitors and an additional LSB capacitor. The
comparator’s negative input is connected to a dummy capacitor
of the same value as the capacitive DAC array. After this process is completed, the control logic generates the
ADC output code and brings the BUSY output LOW.
Rev. 0 | Page 15 of 28
AD7651
Transfer Functions
Using the OB/2C digital input, the AD7651 offers two output
codings: straight binary and twos complement. The LSB size is
VREF/65536, which is about 38.15 µV. The AD7651’s ideal
transfer characteristic is shown in and . Figure 21
Figure 21. ADC Ideal Transfer Function
Table 7
Table 7. Output Codes and Ideal Input Voltages
000...000
000...001
000...010
111...101
111...110
111...111
ADC CODE (Straight Binary)
ANALOG INPUT
V
REF
– 1.5 LSB
V
REF
– 1 LSB
1LSB0V
0.5 LSB
1 LSB = V
REF
/65536
02964-0-003
Digital Output Code (Hex)
Description
Analog
Input
Straight
Binary
Twos
Complement
FSR –1 LSB 2.499962 V FFFF1 7FFF1
FSR – 2 LSB 2.499923 V FFFE 7FFE
Midscale + 1 LSB 1.250038 V 8001 0001
Midscale 1.25 V 8000 0000
Midscale – 1 LSB 1.249962 V 7FFF FFFF
–FSR + 1 LSB 38 µV 0001 8001
–FSR 0 V 00002 80002
1This is also the code for overrange analog input (VIN – VINGND above
VREF – VREFGND).
2This is also the code for underrange analog input (VIN below VINGND).
NOTES
1
THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER.
2
THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.
3
OPTIONAL LOW JITTER.
4
A 10
µ
F CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).
SEE VOLTAGE REFERENCE INPUT SECTION.
AD7651
D
3
CLOCK
µC/µP/DSP
SERIAL
PORT
DIGITAL SUPPLY
(3.3V OR 5V)
DVDD
100nF +
10
µ
F
100nF
+
10
µ
F
20
Ω
100nF
+
10
µ
F
ANALOG
SUPPLY
(5V)
C
C
A
NALOG INPU
T
(0V TO 2.5V)
PD RESET
SER/PAR
OB/2C
BUSY
SDOUT
SCLK
INGND
IN
REFGND
REF
AGND
AVDD DGND DVDD OVDD OGND
02964-0-004
U1
2
PDREF PDBUF RD
CS
CNVST
REFBUFIN
1
100nF
BYTESWAP
C
R4
Figure 22. Typical Connection Diagram
Rev. 0 | Page 16 of 28
AD7651
Driver Amplifier Choice
TYPICAL CONNECTION DIAGRAM
Although the AD7651 is easy to drive, the driver amplifier needs
to meet the following requirements:
Figure 22 shows a typical connection diagram for the AD7651.
Analog Input
• The driver amplifier and the AD7651 analog input circuit
must be able to settle for a full-scale step of the capacitor
array at a 16-bit level (0.0015%). In the amplifier’s data
sheet, settling at 0.1% to 0.01% is more commonly speci-
fied. This could differ significantly from the settling time at
a 16-bit level and should be verified prior to driver
selection. The tiny op amp OP184, which combines ultra
low noise and high gain-bandwidth, meets this settling
time requirement.
Figure 23
Figure 23. Equivalent Analog Input Circuit
shows an equivalent circuit of the input structure of
the AD7651.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN and INGND. Care must be taken to ensure
that the analog input signal never exceeds the supply rails by
more than 0.3 V. This will cause these diodes to become
forward-biased and start conducting current. These diodes can
handle a forward-biased current of 100 mA maximum. For
instance, these conditions could eventually occur when the
input buffer’s (U1) supplies are different from AVDD. In such a
case, an input buffer with a short-circuit current limitation can
be used to protect the part.
• The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7651. The noise
coming from the driver is filtered by the AD7651 analog
input circuit 1-pole low-pass filter made by R1 and C2 or
by the external filter, if one is used.
C2
R1
D1
D2
C1
IN
O
R INGND
AGND
AV D D
02965-0-008
• The driver needs to have a THD performance suitable to
that of the AD7651.
The OP184, OP162 or AD8519 meet these requirements and are
usually appropriate for almost all applications. As an alternative,
in very high speed and noise-sensitive applications, the AD8021
with an external 10 pF compensation capacitor can be used.
This capacitor should have good linearity as an NPO ceramic or
mica type. Moreover, the use of a noninverting +1 gain
arrangement is recommended and helps to obtain the best
signal-to-noise ratio.
This analog input structure allows the sampling of the
differential signal between IN and INGND. Unlike other
converters, INGND is sampled at the same time as IN. By using
this differential input, small signals common to both inputs are
rejected. For instance, by using INGND to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated. The AD8022 could also be used if a dual version is needed and
gain of 1 is present. The AD829 is an alternative in applications
where high frequency (above 100 kHz) performance is not
required. In gain of 1 applications, it requires an 82 pF
compensation capacitor. The AD8610 is an option when low
bias current is needed in low frequency applications.
During the acquisition phase, the impedance of the analog input
IN can be modeled as a parallel combination of capacitor C1
and the network formed by the series connection of R1 and C2.
C1 is primarily the pin capacitance. R1 is typically 3250 Ω and is
a lumped component made up of some serial resistors and the
on resistance of the switches. C2 is typically 60 pF and is mainly
the ADC sampling capacitor. During the conversion phase,
where the switches are opened, the input impedance is limited
to C1. R1 and C2 make a 1-pole low-pass filter that reduces
undesirable aliasing effect and limits the noise.
When the source impedance of the driving circuit is low, the
AD7651 can be driven directly. Large source impedances will
significantly affect the ac performance, especially total
harmonic distortion.
Rev. 0 | Page 17 of 28
AD7651
Voltage Reference Input
The AD7651 allows the choice of either a very low temperature
drift internal voltage reference or an external 2.5 V reference.
For applications that use multiple AD7651s, it is more effective
to use the internal buffer to buffer the reference voltage.
Unlike many ADCs with internal references, the internal
reference of the AD7651 provides excellent performance and
can be used in almost all applications.
Care should be taken with the voltage reference’s temperature
coefficient, which directly affects the full-scale accuracy if this
parameter matters. For instance, a ±15 ppm/°C temperature
coefficient of the reference changes full scale by ±1 LSB/°C.
To use the internal reference along with the internal buffer,
PDREF and PDBUF should both be LOW. This will produce a
1.207 V voltage on REFBUFIN which, amplified by the buffer,
will result in a 2.5 V reference on the REF pin.
Note that VREF can be increased to AVDD – 1.85 V. Since the
input range is defined in terms of VREF, this would essentially
increase the range to 0 V to 3 V with an AVDD above 4.85 V.
The AD780 can be selected with a 3 V reference voltage.
The output impedance of REFBUFIN is 11 kΩ (minimum) when
the internal reference is enabled. It is useful to decouple
REFBUFIN with a 100 nF ceramic capacitor. Thus, the 100 nF
capacitor provides an RC filter for noise reduction.
The TEMP pin, which measures the temperature of the AD7651,
can be used as shown in . The output of TEMP pin is
applied to one of the inputs of the analog switch (e.g., ADG779),
and the ADC itself is used to measure its own temperature. This
configuration is very useful for improving the calibration
accuracy over the temperature range.
Figure 24
Figure 24. Temperature Sensor Connection Diagram
To use an external reference along with the internal buffer,
PDREF should be HIGH and PDBUF should be LOW. This
powers down the internal reference and allows the 2.5 V
reference to be applied to REFBUFIN.
ADG779
AD8021 C
C
02964-0-024
ANALOG INPUT
(UNIPOLAR)
AD7651
IN
TEMPERATURE
SENSOR
TEMP
To use an external reference directly on REF pin, PDREF and
PDBUF should both be HIGH.
PDREF and PDBUF respectively power down the internal
reference and the internal reference buffer. Note that the PDREF
and PDBUF input current should never exceed 20 mA. This
could eventually occur when input voltage is above AVDD (for
instance at power up). In this case, a 100 Ω series resistor is
recommended.
Power Supply
The AD7651 uses three power supply pins: an analog 5 V supply
AVDD, a digital 5 V core supply DVDD, and a digital input/
output interface supply OVDD. OVDD allows direct interface
with any logic between 2.7 V and DVDD + 0.3 V. To reduce the
supplies needed, the digital core (DVDD) can be supplied
through a simple RC filter from the analog supply, as shown in
. The AD7651 is independent of power supply
sequencing once OVDD does not exceed DVDD by more than
0.3 V, and is thus free of supply voltage induced latch-up.
The internal reference is temperature compensated to 2.5 V ±
20 mV. The reference is trimmed to provide a typical drift of 7
. This typical drift characteristic is shown in .
For improved drift performance, an external reference such as
the AD780 can be used.
ppm/°C Figure 17
Figure 22
The AD7651 voltage reference input REF has a dynamic input
impedance; it should therefore be driven by a low impedance
source with efficient decoupling between the REF and REFGND
inputs. This decoupling depends on the choice of the voltage
reference but usually consists of a low ESR tantalum capacitor
connected to REF and REFGND with minimum parasitic
inductance. A 10 µF (X5R, 1206 size) ceramic chip capacitor (or
47 µF tantalum capacitor) is appropriate when using either the
internal reference or one of these recommended reference
voltages:
• The low noise, low temperature drift ADR421 and AD780
• The low power ADR291
• The low cost AD1582
Rev. 0 | Page 18 of 28
AD7651
POWER DISSIPATION VERSUS THROUGHPUT
The CNVST trace should be shielded with ground and a low
value serial resistor (i.e., 50 Ω) termination should be added
close to the output of the component that drives this line.
Operating currents are very low during the acquisition phase,
allowing significant power savings when the conversion rate is
reduced (see ). The AD7651 automatically reduces its
power consumption at the end of each conversion phase. This
makes the part ideal for very low power battery applications.
The digital interface and the reference remain active even
during the acquisition phase. To reduce operating digital supply
currents even further, digital inputs need to be driven close to
the power supply rails (i.e., DVDD or DGND), and OVDD
should not exceed DVDD by more than 0.3 V.
Figure 25
Figure 25. Power Dissipation vs. Sampling Rate
For applications where SNR is critical, the CNVST signal should
have very low jitter. This may be achieved by using a dedicated
oscillator for CNVST generation, or to clock CNVST with a
high frequency, low jitter clock, as shown in . Figure 22
BUSY
MODE
t2
t1
t3
t4
t5
t6
t7t8
ACQUIRE CONVERT ACQUIRE CONVERT
02964-0-011
CNVST
100000
POWER DISSIPATION (
µ
W)
SAMPLING RATE (SPS)
100k1k10 100 10k
10000
1000
100
10
02964-0-038
PDREF = PDBUF = PDHIGH
CONVERSION CONTROL
Figure 26
Figure 26. Basic Conversion Timing
t
9
t
8
RESET
DATA
BUSY
02964-0-011
CNVST
shows the detailed timing diagrams of the conversion
process. The AD7651 is controlled by the CNVST signal, which
initiates conversion. Once initiated, it cannot be restarted or
aborted, even by the power-down input PD, until the conversion
is complete. CNVST operates independently of CS and RD. Figure 27. RESET Timing
Conversions can be automatically initiated with the AD7651. If
CNVST is held LOW when BUSY is LOW, the AD7651 controls
the acquisition phase and automatically initiates a new
conversion. By keeping CNVST LOW, the AD7651 keeps the
conversion process running by itself. It should be noted that the
analog input must be settled when BUSY goes LOW. Also, at
power-up, CNVST should be brought LOW once to initiate the
conversion process. In this mode, the AD7651 can run slightly
faster than the guaranteed 100 kSPS.
t
1
t
3
t
4
t
11
BUSY
DATA
BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA NEW DATA
02964-0-012
CNVST
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges, and levels with minimum
overshoot and undershoot or ringing.
Figure 28. Master Parallel Data Timing for Reading (Continuous Read)
Rev. 0 | Page 19 of 28
AD7651
CURRENT
CONVERSION
BUSY
DATA
BUS
t
12
t
13
02964-0-013
RD
CS
DIGITAL INTERFACE
The AD7651 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7651 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7651 to the host system interface digital supply. Finally, by
using the OB/2C input pin, both twos complement or straight
binary coding can be used.
The two signals, CS and RD, control the interface. CS and RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually CS allows the selection
of each AD7651 in multicircuit applications and is held low in a
single AD7651 design. RD is generally used to enable the
conversion result on the data bus.
PARALLEL INTERFACE
The AD7651 is configured to use the parallel interface when
SER/PARis held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F and
, respectively. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
igure 29
Figure 29. Slave Parallel Data Timing for Reading (Read after Convert)
Figure 30
Figure 30. Slave Parallel Data Timing for Reading (Read during Convert)
PREVIOUS
CONVERSION
t
1
t
3
t
12
t
13
t
4
BUSY
DATA
BUS
02964-0-014
CNVST,
RD
CS = 0
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in , the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
Figure 31
Figure 31. 8-Bit Parallel Interface
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0] HI-Z
HI-Z HIGH BYTE LOW BYTE
LOW BYTE HIGH BYTE HI-Z
HI-Z
t
12
t
12
t
13
02964-0-025
SERIAL INTERFACE
The AD7651 is configured to use the serial interface when
SER/PAR is held HIGH. The AD7651 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.
Rev. 0 | Page 20 of 28
AD7651
MASTER SERIAL INTERFACE Usually, because the AD7651 has a longer acquisition phase than
the conversion phase, the data is read immediately after conversion.
This makes the Master Read After Conversion the most recom-
mended serial mode when it can be used. In this mode, it should be
noted that unlike in other modes, the BUSY signal returns LOW
after the 16 data bits are pulsed out and not at the end of the
conversion phase, which results in a longer BUSY width.
Internal Clock
The AD7651 is configured to generate and provide the serial data
clock SCLK when the EXT/INT pin is held LOW. The AD7651 also
generates a SYNC signal to indicate to the host when the serial data
is valid. The serial clock SCLK and the SYNC signal can be inverted
if desired. Depending on the RDC/SDIN input, the data can be read
after each conversion or during the following conversion. Figure 32
and Figure 33 show detailed timing diagrams of these two modes. In the Read During Conversion mode, the serial clock and data
toggle at appropriate instants, which minimize potential feed-
through between digital activity and critical conversion decisions
t
3
BUSY
SYNC
SCLK
SDOUT
t
28
t
29
t
14
t
18
t
19
t
20
t
21
t
24
t
26
t
27
t
23
t
22
t
16
t
15
123 141516
D15 D14 D2 D1 D0
X
RDC/SDIN = 0 INVSCLK = INVSYNC = 0
t
25
t
30
02964-0-015
CNVST
CS, RD
EXT/INT = 0
Figure 32. Master Serial Data Timing for Reading (Read after Convert)
EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0
t
3
t
1
t
17
t
14
t
19
t
20
t
21
t
24
t
26
t
25
t
27
t
23
t
22
t
16
t
15
D15 D14 D2 D1 D0X
12 3 141516
t
18
BUSY
SYNC
SCLK
SDOUT
02964-0-016
CNVST
CS, RD
Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
Rev. 0 | Page 21 of 28
AD7651
SLAVE SERIAL INTERFACE
External Clock
The AD7651 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is held
HIGH. In this mode, several methods can be used to read the
data. The external serial clock is gated by CS. When CS and RD
are both LOW, the data can be read after each conversion or
during the following conversion. The external clock can be
either a continuous or a discontinuous clock. A discontinuous
clock can be either normally HIGH or normally LOW when
inactive. F and F show the detailed timing
diagrams of these methods. Usually, because the AD7651 has a
longer acquisition phase than conversion phase, the data are
read immediately after conversion.
igure 34
Figure 34. Slave Serial Data Timing for Reading (Read after Convert)
igure 35
Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)
While the AD7651 is performing a bit decision, it is important
that voltage transients be avoided on digital input/output pins or
degradation of the conversion result could occur. This is
particularly important during the second half of the conversion
phase because the AD7651 provides error correction circuitry
that can correct for an improper bit decision made during the
first half of the conversion phase. For this reason, it is
recommended that when an external clock is being provided, it
is a discontinuous clock that is toggling only when BUSY is
LOW, or, more importantly, that it does not transition during the
latter half of BUSY HIGH.
SCLK
SDOUT D15 D14 D1 D0
D13
X15 X14 X13 X1 X0 Y15 Y14
BUSY
SDIN
INVSCLK = 0
t35
t36 t37
t31 t32
t16
t33
X15 X14
X
1 2 3 14151617 18
t34
02964-0-017
EXT/INT = 1
RD RD = 0
S
DOUT
SCLK
D1 D0
XD15 D14 D13
123 141516
t
3
t
35
t
36
t
37
t
31
t
32
t
16
BUSY
EXT/INT = 1 INVSCLK = 0
02965-0-018
CNVST
CS RD = 0
Rev. 0 | Page 22 of 28
AD7651
External Discontinuous Clock Data Read After
Conversion
External Clock Data Read During Conversion
Figure 35 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are LOW, the result
of the previous conversion can be read. The data is shifted out
MSB first with 16 clock pulses, and is valid on both the rising
and falling edges of the clock. The 16 bits must be read before
the current conversion is complete; otherwise, RDERROR is
pulsed HIGH and can be used to interrupt the host interface to
prevent incomplete data reading. There is no daisy-chain feature
in this mode and the RDC/SDIN input should always be tied
either HIGH or LOW.
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
LOW, the conversion’s result can be read while both CS and RD
are LOW. Data is shifted out MSB first with 16 clock pulses and
is valid on the rising and falling edges of the clock.
Figure 34
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of at least 18 MHz is recommended to
ensure that all the bits are read during the first half of the
conversion phase. It is also possible to begin to read data after
conversion and continue to read the last bits after a new
conversion has been initiated. This allows the use of a slower
clock speed like 14 MHz.
Finally, in this mode only, the AD7651 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple con-
verters together. This feature is useful for reducing component
count and wiring connections when desired, as, for instance, in
isolated multiconverter applications.
An example of the concatenation of two devices is shown in
. Simultaneous sampling is possible by using a
common CNVST signal. It should be noted that the RDC/SDIN
input is latched on the opposite edge of SCLK of the one used to
shift out the data on SDOUT. Therefore, the MSB of the
“upstream” converter just follows the LSB of the “downstream”
converter on the next SCLK cycle.
Figure 36
Figure 36. Two AD7651s in a Daisy-Chain Configuration
SCLK
SDOUTRDC/SDIN
BUSYBUSY
DATA
OUT
AD7651
#1
(DOWNSTREAM)
BUSY
OUT
SCLK
AD7651
#2
(UPSTREAM)
RDC/SDIN SDOUT
SCLK IN
CNVST IN
02964-0-019
CNVST
CS
CNVST
CS
CS IN
Rev. 0 | Page 23 of 28
AD7651
MICROPROCESSOR INTERFACING
The AD7651 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7651 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7651 to prevent digital noise from coupling
into the ADC. The following section discusses the use of an
AD7651 with an ADSP-219x SPI equipped DSP.
SPI Interface (ADSP-219x)
Figure 37
Figure 37. Interfacing the AD7651 to an SPI Interfac
shows an interface diagram between the AD7651 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7651 acts as a slave device and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command can be initiated in
response to an internal timer interrupt. The reading process can
be initiated in response to the end-of-conversion signal (BUSY
going LOW) using an interrupt line of the DSP. The serial inter-
face (SPI) on the ADSP-219x is configured for master mode—
(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit
(CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by
writing to the SPI control register (SPICLTx). To meet all timing
requirements, the SPI clock should be limited to 17 Mbps, which
allows it to read an ADC result in less than 1 µs. When a higher
sampling rate is desired, use of one of the parallel interface
modes is recommended.
AD7651*
ADSP-219x*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
* ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
02964-0-021
Rev. 0 | Page 24 of 28
AD7651
APPLICATION HINTS
BIPOLAR AND WIDER INPUT RANGES
In some applications, it is desirable to use a bipolar or wider
analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although
the AD7651 has only one unipolar range, simple modifications
of input driver circuitry allow bipolar and wider input ranges to
be used without any performance degradation. shows
a connection diagram that allows this. Component values
required and resulting full-scale ranges are shown in .
Figure 38
Figure 38
Figure 38. Using the AD7651 in 16-Bit Bipolar and/or Wider Input Ranges
Table 8
Table 8. Component Values and Input Ranges
When desired, accurate gain and offset can be calibrated by
acquiring a ground and voltage reference using an analog
multiplexer (U2), as shown in .
U1
ANALOG
INPUT
R2
R3 R4 100nF
R1
U2
C
REF
IN
INGND
REF
REFGND
AD7651
02964-0-022
C
F
Input Range R1 (Ω) R2 (kΩ) R3 (kΩ) R4 (kΩ)
±10 V 500 4 2.5 2
±5 V 500 2 2.5 1.67
0 V to –5 V 500 1 None 0
LAYOUT
The AD7651 has very good immunity to noise on the power
supplies. However, care should still be taken with regard to
grounding layout.
The printed circuit board that houses the AD7651 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be separated easily. Digital and analog
ground planes should be joined in only one place, preferably
underneath the AD7651, or as close as possible to the AD7651.
If the AD7651 is in a system where multiple devices require
analog-to-digital ground connections, the connection should
still be made at one point only, a star ground point that should
be established as close as possible to the AD7651.
Running digital lines under the device should be avoided since
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7651 to avoid noise
coupling. Fast switching signals like CNVST or clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board, and should never run near analog signal
paths. Crossover of digital and analog signals should be avoided.
Traces on different but close layers of the board should run at
right angles to each other. This will reduce the effect of crosstalk
through the board.
The power supply lines to the AD7651 should use as large a
trace as possible to provide low impedance paths and reduce the
effect of glitches on the power supply lines. Good decoupling is
also important to lower the supply’s impedance presented to the
AD7651 and to reduce the magnitude of the supply spikes.
Decoupling ceramic capacitors, typically 100 nF, should be
placed on each power supply pin—AVDD, DVDD, and
OVDD—close to, and ideally right up against these pins and
their corresponding ground pins. Additionally, low ESR 10 µF
capacitors should be located near the ADC to further reduce
low frequency ripple.
The DVDD supply of the AD7651 can be a separate supply or
can come from the analog supply AVDD or the digital interface
supply OVDD. When the system digital supply is noisy or when
fast switching digital signals are present, if no separate supply is
available, the user should connect DVDD to AVDD through an
RC filter (see F ) and the system supply to OVDD and
the remaining digital circuitry. When DVDD is powered from
the system supply, it is useful to insert a bead to further reduce
high frequency spikes.
igure 22
The AD7651 has five different ground pins: INGND, REFGND,
AGND, DGND, and OGND. INGND is used to sense the analog
input signal. REFGND senses the reference voltage and, because
it carries pulsed currents, should be a low impedance return to
the reference. AGND is the ground to which most internal ADC
analog signals are referenced; it must be connected with the
least resistance to the analog ground plane. DGND must be tied
to the analog or digital ground plane depending on the
configuration. OGND is connected to the digital system
ground.
EVALUATING THE AD7651’S PERFORMANCE
A recommended layout for the AD7651 is outlined in the
EVAL-AD7651 evaluation board for the AD7651. The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD2.
Rev. 0 | Page 25 of 28
AD7651
OUTLINE DIMENSIONS
TOP VIEW
(PINS DOWN )
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
7.00
BSC S
Q
SEATING
PLANE
1.60
MAX
0.75
0.60
0.45
VIEW A
9.00 BSC
SQ
PIN 1
0.20
0.09
1.45
1.40
1.35
0.10 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
7°
3.5°
0°
10°
6°
2°
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 39. 48-Lead Quad Flatpack (LQFP) [ST-48]
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
BOTTOM
VIEW
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX 0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
PADDLE CONNECTED TO AGND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES
0.25 MIN
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 40. 48-Lead Frame Chip Scale Package (LFCSP) [CP-48]
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD7651AST –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7651ASTRL –40°C to +85°C Quad Flatpack (LQFP) ST-48
AD7651ACP –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
AD7651ACPRL –40°C to +85°C Lead Frame Chip Scale (LFCSP) CP-48
EVAL-AD7651CB1 Evaluation Board
EVAL-CONTROL BRD22 Controller Board
1This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
2This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
Rev. 0 | Page 26 of 28
AD7651
NOTES
Rev. 0 | Page 27 of 28
AD7651
NOTES
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C02964–0–9/03(0)
Rev. 0 | Page 28 of 28
