TC74AC161,163P/F/FT
2014-03-01
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC161P, TC74AC161F, TC74AC161FT
TC74AC163P, TC74AC163F, TC74AC163FT
Synchronous Presettable 4-Bit Binary Counter
TC74AC161P/F/FT Asynchronous Clear
TC74AC163P/F/FT Synchronous Clear
The TC74AC161 and 163 are advanced high speed CMOS
SYNCHRONOUS PRESETTABLE COUNTERs fabricated with
silicon gate and double-layer metal wiring C2MOS technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The CK input is active on the rising edge. Both LOAD and
CLR inputs are active on low logic level.
Presetting of these IC’s is synchronous to the rising edge of CK.
The clear function of the TC74AC163 is synchronous to CK,
while the TC74AC161 are cleared asynchronously.
Two enable inputs (ENP and ENT) and CARRY OUTPUT are
provided to enable easy cascading of counters, which facilitates
easy implementation of n-bit counters without using external
gates.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Features
• High speed: fmax = 170 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 8 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: tpLH ∼
−
tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F161/163
TC74AC161P, TC74AC163P
TC74AC161F, TC74AC163F
TC74AC161FT, TC74AC163FT
Weight
DIP16-P-300-2.54A : 1.00 g (typ.)
SOP16-P-300-1.27A : 0.18 g (typ.)
TSSOP16-P-0044-0.65A : 0.06 g (typ.)
Start of commercial production
1987-05
TC74AC161,163P/F/FT
2014-03-01
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Pin Assignment
IEC Logic Symbol
Truth Table (Note)
Inputs Outputs
CLR
(161)
CLR
(163) LOAD ENP ENT CK
(161)
CK
(163) QA QB QC QD
Function
L L X X X X L L L L Reset to “0”
H H L X X A B C D
Preset Data
H H H X L No Change No Count
H H H L X No Change No Count
H H H H H Count Up Count
H X X X X No Change No Count
Note: X: Don’t care
A, B, C, D: Logic level of data inputs
Carry: Carry = ENT·QA·QB·QC·QD
VCC 16
Carry Output
QA
QB
15
14
13
12
11
10
CLR 1
2
3
4
5
6
7
B
C
D
ENP
GND
QC
8 LOAD9
QD
ENT
(top view)
CK
A
(9)
(1)
(10)
(2)
(7)
ENP
1, 5D (1)
CK
(3)
(4)
B
A
(15)
(14)
QB
(13)
QA
QC
CT = 0
M1
LOAD
CLR
C(5)
(6)
D
(12)
QD
(11)
Carry Output
ENT
TC74AC161
CTRDIV 16
M2
G3
G4
C5/2, 3, 4+
3CT = 15
(2)
(4)
(8)
(9)
(1)
(10)
(2)
(7)
ENP
1, 5D (1)
CK
(3)
(4)
B
A
(15)
(14)
QB
(13)
QA
QC
5CT = 0
M1
LOAD
CLR
C(5)
(6)
D
(12)
QD
(11)
Carry Output
ENT
TC74AC163
CTRDIV 16
M2
G3
G4
C5/2, 3, 4+
3CT = 15
(2)
(4)
(8)
TC74AC161,163P/F/FT
2014-03-01
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Timing Chart
COUNT INHIBIT
12
ASYNC
CLEAR
(161)
SYNC
CLEAR
(163)
PRESET
13 14 15 0 1 2
Carry
Output
QD
QC
QB
QA
ENT
ENP
CK
D
C
B
A
LOAD
CLR
Data
Inputs
Outputs
DON’T CARE UNTIL LOAD GOES LOW
TC74AC161,163P/F/FT
2014-03-01
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System Diagram
Note: Truth table of internal F/F
TC74AC161 TC74AC163
D CK R Q Q D CK R Q Q
X X H L H X H L H
L L L H L L L H
H L H L H L H L
X L No Change X L No Change
X: Don’t care
CLR
ENT
1
10
ENP
LOAD
7
9
E
E
L
15 Carry
Out
14 QA
E
E
L
(Note 2)
L
A
3
RQD
Q
CK
13 QB
EL
(Note 2)
L
B 4
RQD
Q
CK
E12 QC
EL
(Note 2)
L
C 5
RQD
Q
CK
E
11 QD
E
(Note 2)
L
D
RQD
Q
CK
6
CK 2
L
L
E
(Note)
(Note)
(Note)
(Note)
TC74AC161,163P/F/FT
2014-03-01
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Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage VOUT −0.5 to VCC + 0.5 V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current IOUT ±50 mA
DC VCC/ground current ICC ±125 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP/TSSOP) mW
Storage temperature Tstg −65 to 150 °C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2.0 to 5.5 V
Input voltage VIN 0 to VCC V
Output voltage VOUT 0 to VCC V
Operating temperature Topr −40 to 85 °C
Input rise and fall time dt/dV 0 to 100 (VCC = 3.3 ± 0.3 V)
0 to 20 (VCC = 5 ± 0.5 V) ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
TC74AC161,163P/F/FT
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Electrical Characteristics
DC Characteristics
Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol Test Condition VCC
(V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH ―
2.0
3.0
5.5
1.50
2.10
3.85
―
―
―
―
―
―
1.50
2.10
3.85
―
―
―
V
Low-level input
voltage VIL ―
2.0
3.0
5.5
―
―
―
―
―
―
0.50
0.90
1.65
―
―
―
0.50
0.90
1.65
V
IOH = −50 μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
―
―
―
1.9
2.9
4.4
―
―
―
High-level output
voltage VOH
VIN
= VIH or
VIL IOH = −4 mA
IOH = −24 mA
IOH = −75 mA (Note)
3.0
4.5
5.5
2.58
3.94
―
―
―
―
―
―
―
2.48
3.80
3.85
―
―
―
V
IOL = 50 μA
2.0
3.0
4.5
―
―
―
0.0
0.0
0.0
0.1
0.1
0.1
―
―
―
0.1
0.1
0.1
Low-level output
voltage VOL
VIN
= VIH or
VIL IOL = 12 mA
IOL = 24 mA
IOL = 75 mA (Note)
3.0
4.5
5.5
―
―
―
―
―
―
0.36
0.36
―
―
―
―
0.44
0.44
1.65
V
Input leakage
current IIN VIN = VCC or GND 5.5 ― ― ±0.1 ― ±1.0 μA
Quiescent supply
current ICC VIN = VCC or GND 5.5 ― ― 8.0 ― 80.0 μA
Note: This spec indicates the capability of driving 50 Ω transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
TC74AC161,163P/F/FT
2014-03-01
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Timing Requirements (input: tr = tf = 3 ns)
Ta =
25°C
Ta =
−40 to
85°C
Characteristics Symbol Test Condition
VCC (V) Limit Limit
Unit
Minimum pulse width
(CK)
tw (L)
tw (H)
Figure 1 3.3 ± 0.3
5.0 ± 0.5
7.0
5.0
7.0
5.0 ns
Minimum pulse width
(CLR ) (Note 1)
tw (L) Figure 4 3.3 ± 0.3
5.0 ± 0.5
7.0
5.0
7.0
5.0 ns
Minimum set-up time
(LOAD , ENP, ENT) ts Figure 2, Figure 3 3.3 ± 0.3
5.0 ± 0.5
11.0
7.0
13.0
7.0 ns
Minimum set-up time
(A, B, C, D) ts Figure 2 3.3 ± 0.3
5.0 ± 0.5
8.0
4.0
8.0
4.0 ns
Minimum set-up time
(CLR ) (Note 2)
ts Figure 5 3.3 ± 0.3
5.0 ± 0.5
6.0
4.0
6.0
4.0 ns
Minimum hold time th Figure 2, Figure 3, Figure 5 3.3 ± 0.3
5.0 ± 0.5
1.0
1.0
1.0
1.0 ns
Minimum removal time
(CLR ) (Note 1)
trem Figure 4 3.3 ± 0.3
5.0 ± 0.5
6.0
4.0
6.0
4.0 ns
Note 1: For TC74AC161 only
Note 2: For TC74AC163 only
TC74AC161,163P/F/FT
2014-03-01
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AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol Test Condition
VCC (V) Min Typ. Max Min Max
Unit
Propagation delay
time
(CK-Q)
tpLH
tpHL
Figure 1 3.3 ± 0.3
5.0 ± 0.5
―
―
8.8
6.5
15.8
9.6
1.0
1.0
18.0
11.0 ns
Propagation delay
time
(CK-carry, count
mode)
tpLH
tpHL
Figure 1 3.3 ± 0.3
5.0 ± 0.5
―
―
10.4
8.1
18.4
11.8
1.0
1.0
21.6
13.5 ns
Propagation delay
time
(CK-carry, preset
mode)
tpLH
tpHL
Figure 2 3.3 ± 0.3
5.0 ± 0.5
―
―
12.9
9.1
22.4
13.2
1.0
1.0
25.5
15.0 ns
Propagation delay
time
(ENT-carry)
tpLH
tpHL Figure 6 3.3 ± 0.3
5.0 ± 0.5
―
―
7.5
5.8
13.2
8.3
1.0
1.0
15.0
9.5 ns
Propagation delay
time
(CLR -Q) (Note 1)
tpHL Figure 4 3.3 ± 0.3
5.0 ± 0.5
―
―
10.6
7.7
18.4
11.4
1.0
1.0
21.0
13.0 ns
Propagation delay
time
(CLR -carry)
(Note 1)
tpHL Figure 4 3.3 ± 0.3
5.0 ± 0.5
―
―
12.0
8.6
21.0
12.7
1.0
1.0
24.0
14.5 ns
Maximum clock
frequency fmax ― 3.3 ± 0.3
5.0 ± 0.5
50
90
110
140
―
―
50
90
―
― MHz
Input capacitance CIN ― ― 5 10 ― 10 pF
Power dissipation
capacitance CPD (Note 2) ― 85 ― ― ― pF
Note 1: For TC74AC161 only
Note 2: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is
obtained from the following formula:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛++++⋅ 16
C
16
C
8
C
4
C
2
C
Vf = ΔICO
QDQCQBQA
CCCKCC
C
QA to CQD and CCO are the capacitances at QA to QD and CARRY OUT, respectively.
f
CK is the input frequency of the CK.
TC74AC161,163P/F/FT
2014-03-01
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Switching Characteristics Test Waveform
Figure 1 Count Mode Figure 4 Clear Mode (TC74AC161)
CK 50%
twH t
wL
VCC
GND
50%
VOH
VOL
tpHL
50%
50%
tpLH
Q,
Carry
CLR 50%
twL
VCC
GND
VOH
VOL
trem
50%
0.5 VCC
tpHL
CK
Q,
Carry
VCC
GND
Figure 2 Preset Mode Figure 5 Clear Mode (TC74AC163)
LOAD 50%
ts
VCC
GND
th
50%
ts th
50%
ts th
50%
A
to D
tpLH, tpHL
50%
VCC
GND
CK
VOH
VOL
Q,
Carry 0.5 VCC
CLR 50%
VCC
GND
VOH
VOL
50%
CK
Q,
Carry
VCC
GND
50%
tsth
ENP,
ENT 50%
ts
VCC
GND
th
50%
ts th
CK
Q
VOH
VOL
VOH
VOL
ENT
VCC
GND
VCC
GND
50%50%
50% 50%
Carry 0.5
VCC
0.5 VCC
tpLH tpHL
Figure 3 Count Enable Mode Figure 6 Cascade Mode
(fix maximum count)
TC74AC161,163P/F/FT
2014-03-01
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Typical Application
Parallel Carry N-Bit Counter
LD A
CLR QA
B C
QB QC
D
QD
INPUTS
OUTPUTS
Carry
ENP
ENT
CK
LD A
CLR QA
BC
QB QC
D
QD
INPUTS
OUTPUTS
Carry
ENP
ENT
CK
LD A
CLR QA
BC
QB QC
D
QD
INPUTS
OUTPUTS
Carry
ENP
ENT
CK
NEXT
STAGE
H: COUNT
L: DISABLE
H: COUNT
L: DISABLE
CK
CLR
TC74AC161,163P/F/FT
2014-03-01
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Package Dimensions
Weight: 1.00 g (typ.)
TC74AC161,163P/F/FT
2014-03-01
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Package Dimensions
Weight: 0.18 g (typ.)
TC74AC161,163P/F/FT
2014-03-01
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Package Dimensions
Weight: 0.06 g (typ.)
TC74AC161,163P/F/FT
2014-03-01
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