LTC3860
1
3860fc
TYPICAL APPLICATION
DESCRIPTION
Dual, Multiphase Step-Down
Voltage Mode DC/DC Controller
with Current Sharing
The LTC
®
3860 is a dual, PolyPhase
®
synchronous step-
down switching regulator controller for high current
distributed power systems, digital signal processors, and
other telecom and industrial DC/DC power supplies. It uses
a constant frequency voltage mode architecture combined
with very low offset, high bandwidth error amplifi ers and
a remote output sense differential amplifi er for excellent
transient response and output regulation.
The controller incorporates lossless inductor DCR current
sensing to maintain current balance between phases and to
provide overcurrent protection. The chip operates from a
VCC supply between 3V and 5.5V and is designed for step-
down conversion from VIN between 3V and 24V to output
voltages between 0.6V and VCC – 0.5V.
The TRACK/SS pins provide programmable soft-start or
tracking functions. Inductor current reversal is disabled
during soft-start to safely power prebiased loads. The con-
stant operating frequency can be synchronized to an exter-
nal clock or linearly programmed from 250kHz to 1.25MHz.
Up to six LTC3860 controllers can operate in parallel for
1-, 2-, 3-, 4-, 6- or 12-phase operation.
The LTC3860 is available in a 32-pin 5mm × 5mm QFN
package.
FEATURES
APPLICATIONS
n Operates with Power Blocks, DRMOS or External
Gate Drivers and MOSFETs
n Constant Frequency Voltage Mode Control with
Accurate Current Sharing
n ±0.75% 0.6V Voltage Reference
n Differential Remote Output Voltage Sense Amplifi er
n Multiphase Capability—Up to 12-Phase Operation
n Programmable Current Limit
n Safely Powers a Prebiased Load
n Programmable or PLL-Synchronizable Switching
Frequency Up to 1.25MHz
n Lossless Current Sensing Using Inductor DCR or
Precision Current Sensing with Sense Resistor
n V
CC Range: 3V to 5.5V
n V
IN Range: 3V to 24V
n Power Good Output Voltage Monitor
n Output Voltage Tracking Capability
n Programmable Soft-Start
n Available in a 32- Pin 5mm × 5mm QFN Package
n High Current Distributed Power Systems
n Digital Signal Processor and ASIC Supplies
n Telecom Systems
n Industrial Power Supplies L, LT, LTC, LTM, PolyPhase, μModule, Linear Technology and the Linear logo are registered
trademarks and No RSENSE is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
6144194, 5055767
VINSNS
VCC
FREQ
FB2
ILIM2
FB1
COMP1,2
SS1,2
IN
VLOGIC
VCC
BOOST
GND
TG
TS
BG
RUN1,2
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
LTC3860
PWM1
LTC4449
VIN
VIN
SW1 0.3μH
SGND CLKIN
VSNSOUT
VSNSN
VSNSP
PWM2 PWM2
PWM1
470μF
1μF 0.22μF
0.22μF
TG1
BG1
VCC
VCC
0.22μF
100pF
1nF
0.1μF
220pF 12.7k
220Ω
50k 2.32k
2.32k
20k
20k
33pF
VOUT
VIN
VCC
IN
VLOGIC
VCC
BOOST
GND
TG
TS
BG
LTC4449
SW2 0.3μH
0.22μF
TG2
BG2
3860 TA01
330μF
s4
VOUT
1.2V
50A
IAVG
LTC3860
2
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VCC Voltage .................................................. –0.3V to 6V
VINSNS Voltage ......................................... –0.3V to 30V
VSNSN Voltage ............................................ –0.3V to 2V
RUN Voltage ................................................ –0.3V to 6V
ISNS1P
, ISNS1N,
ISNS2P
, ISNS2N ...........................–0.3V to (VCC + 0.1V)
All Other Voltages .........................–0.3V to (VCC + 0.3V)
Operating Junction Temperature Range
(Note 3) .................................................. –40°C to 125°C
Storage Temperature Range ................... –65°C to 125°C
(Note 1)
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
33
SGND
UH PACKAGE
32-LEAD (5mm s 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS SGND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3860EUH#PBF LTC3860EUH#TRPBF 3860 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3860IUH#PBF LTC3860IUH#TRPBF 3860 32-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 3). VCC = 5V, VRUN1,2 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V,
fOSC = 0.6MHz unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Voltage Range l3.0 5.5 V
VIN VIN Range VCC = 5V l324V
IQInput Voltage Supply Current
Normal Operation
Shutdown Mode
UVLO
VRUN1,2 = 5V
VRUN1,2 = 0V
VCC < VUVLO
14
3.5
50
mA
μA
mA
VRUN RUN Input Threshold VRUN Rising
VRUN Hysteresis
1.95 2.25
250
2.45 V
mV
IRUN RUN Input Pull-Up Current VRUN1,2 = 2.4V 1.5 μA
VUVLO Undervoltage Lockout Threshold VCC Rising
VCC Hysteresis
l
100
3.0 V
mV
LTC3860
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 3). VCC = 5V, VRUN1,2 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V,
fOSC = 0.6MHz unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ISS Soft-Start Pin Output Current VSS = 0V 2.5 μA
tSS(INTERNAL) Internal Soft-Start Time 2ms
VFB Regulated Feedback Voltage 0°C to 85°C
–40°C to 85°C
–40°C to 125°C l
595.5
594
592.5
600
600
600
604.5
606
607.5
mV
mV
mV
ΔVFB/ΔVCC Regulated Feedback Voltage Line
Dependence
3.0V < VCC < 5.5V 0.05 0.2 %/V
ILIMIT ILIM Pin Output Current VILIM = 0.8V 18 20 22 μA
Power Good
VFB(OV) PGOOD/VFB Overvoltage Threshold VFB Falling
VFB Rising 650
645
660 670
mV
mV
VFB(UV) PGOOD/VFB Undervoltage Threshold VFB Falling
VFB Rising
530 540
555
550 mV
mV
VPGOOD(ON) PGOOD Pull-Down Resistance 15 60 Ω
Error Amplifi er
IFB FB Pin Input Current VFB = 600mV –100 100 nA
IOUT COMP Pin Output Current Sourcing
Sinking
1
5
mA
mA
AV(OL) Open-Loop Voltage Gain 75 dB
SR Slew Rate 45 V/μs
f0dB COMP Unity-Gain Bandwidth 20 MHz
Differential Amplifi er
AVDifferential Amplifi er Voltage Gain VVSNSN = 0V l1.007 1 0.993 V/V
VOS Input Referred Offset VVSNSN = 0V –2 2 mV
SR Slew Rate 45 V/μs
f0dB Bandwidth 20 MHz
VOUT(MAX) Maximum Output Voltage 4V
Current Sense Amplifi er
VISENSE(MAX) Maximum Differential Current Sense
Voltage (VISNSP-VISNSN)
50 mV
AV(ISENSE) Voltage Gain 18.5 V/V
VCM(ISENSE) Input Common Mode Range –0.3 VCC + 0.1 V
IISENSE SENSE Pin Input Current VCM = 1.5V 100 nA
VOS Current Sense Input Referred Offset 0°C to 125°C
–40°C to 125°C l
–2
–2.2
2
2.2
mV
mV
Oscillator and Phase-Locked Loop
fOSC Oscillator Frequency VCLKIN = 0V
VFREQ = 0V
VFREQ = 5V
l
l
360
540
400
600
440
660
kHz
kHz
VCLKIN = 5V
RFREQ < 24.9k
RFREQ = 30.1k
RFREQ = 54.9k
RFREQ = 75.0k
200
300
800
1.2
kHz
kHz
kHz
MHz
Maximum Frequency
Minimum Frequency
1.25
0.25
MHz
MHz
LTC3860
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ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at TA = 25°C (Note 3). VCC = 5V, VRUN1,2 = 5V, VFREQ = VCLKIN = 0V, VFB = 0.6V,
fOSC = 0.6MHz unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IFREQ FREQ Pin Output Current VFREQ = 0.8V 19 21 23 μA
tCLKIN(HI) CLKIN Pulse Width High VCLKIN = 0V to 5V 100 ns
tCLKIN(LO) CLKIN Pulse Width Low VCLKIN = 0V to 5V 100 ns
RCLKIN CLKIN Pull-Up Resistance 13 kΩ
VCLKIN CLKIN Input Threshold VCLKIN Falling
VCLKIN Rising
1.2
2
V
V
VFREQ FREQ Input Threshold VCLKIN = 0V
VFREQ Falling
VFREQ Rising
1.5
2.5
V
V
VOL(CLKOUT) CLKOUT Low Output Voltage ILOAD = –500μA 0.2 V
VOH(CLKOUT) CLKOUT High Output Voltage ILOAD = 500μA VCC – 0.2 V
θ2-θ1Channel 1-to-Channel 2 Phase Relationship VPHSMD = 0V
VPHSMD = Float
VPHSMD = VCC
180
180
120
Deg
Deg
Deg
θCLKOUT-θ1CLKOUT-to-Channel 1 Phase Relationship VPHSMD = 0V
VPHSMD = Float
VPHSMD = VCC
60
90
240
Deg
Deg
Deg
PWM/PWMEN Outputs
PWM PWM Output High Voltage ILOAD = 500μA l4.5 V
PWM Output Low Voltage ILOAD = –500μA l0.5 V
PWM Output Current in Hi-Z State ±5 μA
PWM Maximum Duty Cycle 91.5 %
PWMEN PWMEN Output High Voltage ILOAD = 1mA l4.5 V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
T
J = TA + (PD • θJA)
Note 3: The LTC3860 is tested under pulsed load conditions such that
TJ
≈
TA. The LTC3860E is guaranteed to meet performance specifi cations
from 0°C to 85°C junction temperature. Specifi cations over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3860I is guaranteed over the full –40°C to 125°C operating junction
temperature range. The maximum ambient temperature consistent with
these specifi cations is determined by specifi c operating conditions in
conjunction with board layout, the rated package thermal resistors and
other environmental factors.
LTC3860
5
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Load Step Transient Response
(Single Phase)
Load Step Transient Response
(2-Phase)
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step Transient Response
(2-Phase with 50% Inductor
Mismatch)
Effi ciency and Power Loss
vs Load Current
Effi ciency and Power Loss
vs Supply Voltage
50μs/DIV 3860 G01
VIN = 12V
VOUT = 1.2V
ILOAD STEP = 10A
COMP VALUES:
R2A = 6.8kΩ, C1A = 470pF, C2A = 100pF
VOUT
50mV/DIV
ILOAD
10A/DIV
IL
10A/DIV
Load Step Transient Response
(2-Phase)
VOUT
50mV/DIV
50μs/DIV 3860 G02
VIN = 12V
VOUT = 1.8V
ILOAD STEP = 10A
IL1
5A/DIV
ILOAD
10A/DIV
IL2
5A/DIV
VOUT
50mV/DIV
50μs/DIV 3860 G03
VIN = 12V
VOUT = 1.2V
ILOAD STEP = 10A
IL1
5A/DIV
ILOAD
10A/DIV
IL2
5A/DIV
LOAD CURRENT (A)
0.001
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
0.01 0.1 1 10 100
3860 G05
30
20
10
0
90
100
1
2
3
4
5
0
6
7
VIN = 6V
VOUT = 1.2V
SUPPLY VOLTAGE (V)
6
70
EFFICIENCY (%)
POWER LOSS (W)
72
76
78
80
90
84
810 11
3860 G06
74
86
88
82
1.0
1.5
2.5
3.0
3.5
6.0
4.5
2.0
5.0
5.5
4.0
79 12 13 14
VOUT = 1.2V
IOUT = 15A
VOUT(AC)
100mV/DIV
50μs/DIV 3860 G04
VIN = 12V
VOUT = 1.2V
ILOAD = 0A TO 25A
IL1 = 320nH
10A/DIV
ILOAD
20A/DIV
IL2 = 220nH
10A/DIV
LTC3860
6
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TYPICAL PERFORMANCE CHARACTERISTICS
Oscillator Frequency
vs Supply Voltage
SUPPLY VOLTAGE (V)
3.0
OSCILLATOR FREQUENCY (MHz)
1.175
1.200
1.225
4.5 5.5
3860 G11
1.150
1.125
1.100 3.5 4.0 5.0
1.250
1.275
1.300
Short-Circuit Protection Regulated VFB vs Supply Voltage Oscillator Frequency vs RFREQ
10ms/DIV 3860 G07
VIN = 12V
VOUT = 1.2V
ILOAD = SHORTED
SW NODE
5V/DIV
VOUT
1V/DIV
SUPPLY VOLTAGE (V)
3
0.596
REGULATED VFB (V)
0.598
0.600
0.602
0.604
45
3860 G08
6
RFREQ (kΩ)
0
OSCILLATOR FREQUENCY (MHz)
0.7
0.9
1.1
60 100
3860 G09
0.5
0.3
0.1 20 40 80
1.3
1.5
1.7
120
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50
OSCILLATOR FREQUENCY (kHz)
595
600
605
25 50 75 100 125
3860 G10
590
585
–25 0 150
580
575
610
LTC3860
7
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Soft-Start Start-Up Ratiometric Tracking Start-Up
Line Step Transient Response
(2-Phase)
5ms/DIV 3860 G12
VIN = 12V
VOUT1 = 1.2V
0.1μF CAPACITOR ON TRACK/SS1
VOUT1
200mV/DIV
Coincident Tracking Start-Up
2μs/DIV 3860 G13
CHANNEL 1 TRACKING OFF PULSE GENERATOR
VOUT1
500mV/DIV
TRACK/SS1
500mV/DIV
2μs/DIV 3860 G14
CHANNEL 1 TRACKING OFF PULSE GENERATOR
VOUT1
500mV/DIV
TRACK/SS1
500mV/DIV
VOUT
50mV/DIV
VIN
5V/DIV
COMP1
100mV/DIV
20μs/DIV 3860 G15
VIN = 12V
VOUT = 1.8V
VIN STEP = 7V TO 14V
IL1
5A/DIV
IL2
5A/DIV
Line Step Transient Response
(2-Phase)
VOUT
50mV/DIV
VIN
5V/DIV
COMP1
100mV/DIV
20μs/DIV 3860 G16
VIN = 12V
VOUT = 1.2V
VIN STEP = 7V TO 14V
IL1
5A/DIV
IL2
5A/DIV
Line Step Transient Response
(Single Phase)
20μs/DIV
VOUT = 1.2V
VIN STEP = 7V TO 14V
3860 G17
VOUT
50mV/DIV
IL
2A/DIV
VIN
5V/DIV
COMP1
100mV/DIV
TYPICAL PERFORMANCE CHARACTERISTICS
LTC3860
8
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PIN FUNCTIONS
VCC (Pin 1): Chip Supply Voltage. Bypass this pin to GND
with a capacitor (0.1μF to 1μF ceramic) in close proximity
to the chip.
FB1 (Pin 2), FB2 (Pin 8): Error Amplifi er Inverting Inputs.
FB1 or FB2 can be connected to VSNSOUT via a resistor
divider for remote VOUT sensing. The bottom of the divider
should be connected to the SGND pin of the IC. The other
FB, when used, is typically connected to the other VOUT via
a resistor divider, also terminated at the IC SGND pin.
COMP1 (Pin 3), COMP2 (Pin 7): Error Amplifi er Outputs.
PWM duty cycle increases with this control voltage.
The error amplifi ers in the LTC3860 are true operational
amplifi ers with low output impedance. As a result, the
outputs of two active error amplifi ers cannot be directly
connected together! For multiphase operation, connecting
the FB pin on an error amplifi er to VCC will three-state
the output of that amplifi er. Multiphase operation can
then be achieved by connecting all of the COMP pins
together and using one channel as the master and all
others as slaves.
VSNSOUT (Pin 4): Differential Amplifi er Output.
VSNSN (Pin 5): Remote Sense Differential Amplifi er
Inverting Input. Connect this pin to sense ground at the
output load.
VSNSP (Pin 6): Remote Sense Differential Amplifi er
Noninverting Input. Connect this pin to VOUT at the output
load.
FREQ (Pin 10): Frequency Set/Select Pin. If CLKIN is high,
the resistor between this pin and SGND sets the switching
frequency. If CLKIN is low, the logic state of this pin sets
frequency. This pin sources 21μA.
CLKIN (Pin 11): External Clock Synchronization Input
Pin. If an external clock is present at this pin, the switch-
ing frequency will be synchronized to the external clock.
Otherwise, if high, a resistor from FREQ to SGND sets
frequency; if low, FREQ state sets frequency.
CLKOUT (Pin 12): Clock Output Pin. Used to synchronize
other LTC3860s.
PHSMD (Pin 13): Phase Mode Pin. Selects Ch1-Ch2 and
Ch1-CLKOUT phase relationship.
ISNS1N (Pin 21), ISNS2N (Pin 20): Current Sense Am-
plifi er (–) Input. The (–) input to the current amplifi er is
normally connected to the respective VOUT.
ISNS1P (Pin 22), ISNS2P (Pin 19): Current Sense Amplifi er
(+) Input. The (+) input to the current sense amplifi er is
normally connected to the midpoint of the inductor’s parallel
RC sense circuit or to the node between the inductor and
sense resistor if using a discrete sense resistor.
ILIM1 (Pin 23), ILIM2 (Pin 18): Current Comparator Sense
Voltage Limit Selection Pin. Connect a resistor from this
pin to SGND. This pin sources 20μA. The resultant voltage
sets the threshold for overcurrent protection.
RUN1 (Pin 24), RUN2 (Pin 17): Run Control Inputs. A
voltage above 2.25V on either pin turns on the IC. How-
ever, forcing either of these pins below 2V causes the IC
to shut down that particular channel. There are 1.5μA
pull-up currents for these pins.
PWM1 (Pin 25), PWM2 (Pin 16): (Top) Gate Signal Out-
put. This signal goes to the PWM or top gate input of the
external gate driver or integrated driver MOSFET. This is
a three-state compatible output.
PWMEN1/PWMEN2 (Pin 26/Pin 15): Enable Pin for Non-
Three-State compatible drivers. This pin has an internal
open-drain pull-up to VCC. An external resistor to SGND
is required. This pin is low when the corresponding PWM
pin is high impedance.
PGOOD1 (Pin 27), PGOOD2 (Pin 14): Power Good Pins.
Open-drain outputs that pull to ground when output volt-
age is not in regulation.
IAVG (Pin 28): Average Current Output Pin. A capacitor tied
to ground from this pin stores a voltage proportional to
the master’s instantaneous average current when multiple
outputs are paralleled. Tie the IAVG pin to ground when the
controller drives two independent outputs.
SGND (Pins 29, 30, Exposed Pad Pin 33): Ground. Pins
29, 30 and 33 are electrically connected internally. The
exposed pad must be soldered to the PCB for rated thermal
performance.
VINSNS (Pin 31): V
IN Sense Pin. Connects to the VIN
power supply to provide line feedforward compensation.
LTC3860
9
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FUNCTIONAL DIAGRAM
PIN FUNCTIONS
A change in VIN immediately modulates the input to the
PWM comparator and changes the pulse width in an in-
versely proportional manner, thus bypassing the feedback
loop and providing excellent transient line regulation. An
external lowpass fi lter can be added to this pin to prevent
noisy signals from affecting the loop gain.
TRACK/SS1 (Pin 32), TRACK/SS2 (Pin 9): Soft-Start. The
voltage ramp rate at these pins sets the voltage ramp rate
of the outputs. Self soft-start is accomplished by placing
a capacitor to ground.
22 ISNS1P
21 ISNS1N
20
231828
ISNS2N
IAVG ILIM2 ILIM1
20μA
21μA
20μA
10
FREQ
13
PHSMD
12
CLKOUT
11
16
CLKIN
3860 BD
OC1
NOC1
OC2
NOC2
19 ISNS2P
x18.5
x18.5
8FB2
7COMP2
9TRACK/SS2 EA2
REF
REF
2FB1
32 TRACK/SS1
3COMP1
EA1
+
+
–
+
+
–
+
–
+
–
5VSNSN
24
RUN1
100k
VCC
1.5μA
1.5μA
VCC
17
RUN2
6VSNSP
4VSNSOUT
DA
S
VFB1
ILIM1
VFB2
ILIM2
S
MASTER/SLAVE/
INDEPENDENT?
SD/UVLO
27
PGOOD1
VFB1 VFB2
14
PGOOD2
RAMP/SLOPE/
FEEDFORWARD
PGOOD
LOGIC
OC1 OC2 OV1 OV2
NOC1
NOC2 PWM2
31
VINSNS
25
PWM1
15
PWMEN2
26
PWMEN1
PLL/VCO
BG/BIAS
VCC
VCC
VCC
100k
VCC
1
VCC
29
SGND
30
SGND
+
+
LTC3860
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OPERATION
(Refer to Functional Diagram)
Main Control Architecture
The LTC3860 is a dual-channel/dual-phase, constant
frequency, voltage mode controller for DC/DC step-down
applications. It is designed to be used in a synchronous
switching architecture with external integrated-driver
MOSFETs or external drivers and N-channel MOSFETs
using single wire three-state PWM interfaces. The
controller allows the use of sense resistors or lossless
inductor DCR current sensing to maintain current balance
between phases and to provide overcurrent protection.
The operating frequency is selectable from 250kHz to
1.25MHz. To multiply the effective switching frequency,
multiphase operation can be extended to 3, 4, 6, or 12
phases by paralleling up to 6 controllers. In single or 3-
phase operation, the 2nd or 4th channel can be used as
an independent output.
The output of the differential amplifi er is connected to
the error amplifi er inverting input (FB) through a resistor
divider. The remote sense differential amplifi er output
(VSNSOUT) provides a signal equal to the differential voltage
(VSNSP – VSNSN) sensed across the output capacitor, but
re-referenced to the local ground (SGND). This permits
accurate voltage sensing at the load, without regard to
the potential difference between its ground and local
ground.
In the main voltage mode control loop, the error ampli-
fi er output (COMP) directly controls the converter duty
cycle in order to drive the FB pin to 0.6V in steady state.
Dynamic changes in output load current can perturb the
output voltage. When the output is below regulation,
COMP rises, increasing the duty cycle. If the output rises
above regulation, COMP will decrease, decreasing the
duty cycle. As the output approaches regulation, COMP
will settle to the steady-state value representing the step-
down conversion ratio.
In normal operation, the PWM latch is set high at the begin-
ning of the clock cycle (assuming COMP > 0.5V). When
the (line feedforward compensated) PWM ramp exceeds
the COMP voltage, the comparator trips and resets the
PWM latch. If COMP is less than 0.5V at the beginning
of the clock cycle, as in the case of an overvoltage at the
outputs, the PWM pin remains low throughout the entire
cycle. When the PWM pin goes high it has a minimum
on-time of approximately 20ns and a minimum off-time
of approximately 1/12th the switching period.
Current Sharing
In multiphase operation, the LTC3860 also incorporates an
auxiliary current sharing loop. Inductor current is sampled
each cycle. The master’s current sense amplifi er output
is averaged at the IAVG pin. A small capacitor connected
from IAVG to GND (typically 100pF) stores a voltage cor-
responding to the instantaneous average current of the
master. Each phase integrates the difference between its
current and the master’s. Within each phase the integrator
output is proportionally summed with the system error
amplifi er voltage (COMP), adjusting that phase’s duty
cycle to equalize the currents. When multiple ICs are
daisychained the IAVG pins must be connected together.
When the phases are operated independently, the IAVG
pin should be tied to ground. Figure 1 shows a transient
load step with 50% inductor mismatch in a 2-phase system.
Figure 1
VOUT(AC)
100mV/DIV
50μs/DIV 3860 F01
VIN = 12V
VOUT = 1.2V
ILOAD = 0A TO 25A
IL1 = 320nH
10A/DIV
ILOAD
20A/DIV
IL2 = 220nH
10A/DIV
Overcurrent Protection
The current sense amplifi er outputs also connect to
overcurrent (OC) comparators that provide fault protec-
tion in the case of an output short. When an OC fault is
detected, the controller three-states the PWM output,
resets the soft-start capacitor, and waits for 32768 clock
cycles before attempting to start up again. The LTC3860
also provides negative OC (NOC) protection by preventing
turn-on of the bottom MOSFET during a negative OC fault
condition. The negative OC threshold is equal to –3/4 the
positive OC threshold. See Applications Information for
guidelines on setting these thresholds.
LTC3860
11
3860fc
Excellent Transient Response
The LTC3860 error amplifi ers are true operational ampli-
fi ers, meaning that they have high bandwidth, high DC gain,
low offset and low output impedance. Their bandwidth,
when combined with high switching frequencies and low-
value inductors, allows the compensation network to be
optimized for very high control loop crossover frequencies
and excellent transient response. The 600mV internal ref-
erence allows regulated output voltages as low as 600mV
without external level-shifting amplifi ers.
Line Feedforward Compensation
The LTC3860 achieves outstanding line transient response
using a feedforward correction scheme which instanta-
neously adjusts the duty cycle to compensate for changes
in input voltage, signifi cantly reducing output overshoot
and undershoot. It has the added advantage of making
the DC loop gain independent of input voltage. Figure 2
shows how large transient steps at the input have little
effect on the output voltage.
Shutdown Control Using the RUN Pins
The two channels of the LTC3860 can be independently
enabled using the RUN1 and RUN2 pins. When both pins
are driven low all internal circuitry, including the internal
reference and oscillator, are completely shut down. A 1.5μA
pull-up current is provided for each RUN pin internally.
The RUN pins remain low impedance up to VCC. From VCC
to 6V, they may sink some current.
Undervoltage Lockout
To prevent operation of the power supply below safe input
voltage levels, both channels are disabled when VCC is below
the undervoltage lockout (UVLO) threshold (2.9V falling,
3V rising). If a RUN pin is driven high, the LTC3860 will
start up the reference to detect when VCC rises above the
UVLO threshold, and enable the appropriate channel.
Overvoltage Protection
If the output voltage rises to more than 10% above the
set regulation value, which is refl ected as a VFB voltage of
0.66V or above, the LTC3860 will force the PWM output
low to turn on the bottom MOSFET and discharge the
output. Normal operation resumes once the output is
back within the regulation window. However, if the reverse
current fl owing from VOUT back through the bottom power
MOSFET to PGND is greater than 3/4 the positive OC
threshold, the NOC comparator trips and shuts off the
bottom power MOSFET to protect it from being destroyed.
This scenario can happen when the LTC3860 tries to start
into a precharged load, higher than the OV threshold. As
a result, the bottom switch turns on until the amount of
reverse current trips the NOC comparator threshold.
Internal Soft-Start
By default, the start-up of each channel’s output voltage
is normally controlled by an internal soft-start ramp. The
internal soft-start ramp represents a noninverting input
to the error amplifi er. The FB pin is regulated to the lower
of the error amplifi er’s three noninverting inputs (the
internal soft-start ramp for that channel, the TRACK/SS
pin or the internal 600mV reference). As the ramp volt-
age rises from 0V to 0.6V over approximately 2ms, the
output voltage rises smoothly from its prebiased value to
its fi nal set value.
OPERATION
(Refer to Functional Diagram)
Figure 2
20μs/DIV
VOUT = 1.2V
VIN STEP = 7V TO 14V
3860 F02
VOUT
50mV/DIV
IL
2A/DIV
VIN
5V/DIV
COMP1
100mV/DIV
Remote Sense Differential Amplifi er
The LTC3860 includes a low offset, unity gain, high
bandwidth differential amplifi er for remote output sens-
ing. Output voltage accuracy is signifi cantly improved
by removing board interconnection losses from the total
error budget.
The LTC3860 differential amplifi er has a typical output
slew rate of 45V/μs, bandwidth of 20MHz, input referred
offset < 2mV and a typical maximum output voltage of VCC
– 1V. The amplifi er is confi gured for unity gain, meaning
that the differential voltage between VSNSP and VSNSN is
translated to VSNSOUT, relative to SGND.
LTC3860
12
3860fc
Certain applications can result in the start-up of the
converter into a non-zero load voltage, where residual
charge is stored on the output capacitor at the onset of
converter switching. In order to prevent the output from
discharging under these conditions, the bottom MOSFET
is disabled until soft-start is complete. However, the bot-
tom MOSFET will be turned on for 20ns every 8 cycles
to allow the driver IC to recharge its topside gate drive
capacitor.
Soft-Start and Tracking Using TRACK/SS Pin
The user can connect an external capacitor greater than
10nF to the TRACK/SS pin for the relevant channel to
increase the soft-start ramp time beyond the internally set
default. The TRACK/SS pin represents a noninverting input
to the error amplifi er and behaves identically to the internal
ramp described in the previous section. An internal 2.5μA
current source charges the capacitor, creating a voltage
ramp on the TRACK/SS pin. As the TRACK/SS pin voltage
rises from 0V to 0.6V, the output voltage rises smoothly
from 0V to its fi nal value in:
CSS • 0.6V
2.5µA seconds
Alternatively, the TRACK/SS pin can be used to force the
start-up of VOUT to track the voltage of another supply.
Typically this requires connecting the TRACK/SS pin to
an external divider from the other supply to ground (see
Applications Information). It is only possible to track
another supply that is slower than the internal soft-start
ramp. The TRACK/SS pin also has an internal open-drain
NMOS pull-down transistor that turns on to reset the
TRACK/SS voltage when the channel is shut down (RUN
= 0V or VCC < UVLO threshold) or during an OC fault
condition.
In multiphase operation, one master error amplifi er is
used to control all of the PWM comparators. The FB pins
for the unused error amplifi ers are connected to VCC in
order to three-state these amplifi er outputs, and the COMP
pins are connected together. The TRACK/SS pins should
also be connected together so that the slave phases can
detect when soft-start is complete and enable the bottom
MOSFET.
Frequency Selection and the Phase-Locked Loop (PLL)
The selection of the switching frequency is a trade-off
between effi ciency, transient response and component
size. High frequency operation reduces the size of the
inductor and output capacitor as well as increasing the
maximum practical control loop bandwidth. However,
effi ciency is generally lower due to increased transition
and switching losses.
The LTC3860’s switching frequency can be set in three
ways: using an external resistor to linearly program the
frequency, synchronizing to an external clock, or simply
selecting one of two fi xed frequencies (400kHz and
600kHz). Table 1 highlights these modes.
Table 1. Frequency Selection
CLKIN PIN FREQ PIN FREQUENCY
Clocked RFREQ to GND 250kHz to 1.25MHz
High RFREQ to GND 250kHz to 1.25MHz
Low Low 400kHz
Low High 600kHz
No external PLL fi lter is required to synchronize the
LTC3860 to an external clock. Applying an external clock
signal to the CLKIN pin will automatically enable the PLL
with internal fi lter.
Constant frequency operation brings with it a number of
benefi ts: inductor and capacitor values can be chosen
for a precise operating frequency and the feedback loop
can be similarly tightly specifi ed. Noise generated by the
circuit will always be at known frequencies.
Using the CLKOUT and PHSMD Pins in
Multiphase Applications
The LTC3860 features CLKOUT and PHSMD pins that al-
low multiple LTC3860 ICs to be daisychained together in
multiphase applications. The clock output signal on the
CLKOUT pin can be used to synchronize additional ICs in
a 3-, 4-, 6- or 12-phase power supply solution feeding a
single high current output, or even several outputs from
the same input supply.
The PHSMD pin is used to adjust the phase relationship
between channel 1 and channel 2, as well as the phase
OPERATION
(Refer to Functional Diagram)
LTC3860
13
3860fc
relationship between channel 1 and CLKOUT, as sum-
marized in Table 2. The phases are calculated relative to
zero degrees, defi ned as the rising edge of PWM1. Refer
to Applications Information for more details on how to
create multiphase applications.
Table 2. Phase Selection
PHSMD PIN CH-1 to CH-2 PHASE CH-1 to CLKOUT PHASE
Float 180° 90°
Low 180° 60°
High 120° 240°
Using the LTC3860 Error Amplifi ers in
Multiphase Applications
Due to the low output impedance of the error amplifi ers,
multiphase applications using the LTC3860 use one
error amplifi er as the master with all of the slaves’
error amplifi ers disabled. The channel 1 error amplifi er
(phase = 0°) may be used as the master with phases 2
through n (up to 12) serving as slaves. To disable the
slave error amplifi ers connect the FB pins of the slaves
to VCC. This three-states the output stages of the ampli-
fi ers. All COMP pins should then be connected together
to create PWM outputs for all phases. As noted in the
section on soft-start, all TRACK/SS pins should also be
shorted together. Refer to the Multiphase Operation sec-
tion in Applications Information for schematics of various
multiphase confi gurations.
Theory and Benefi ts of Multiphase Operation
Multiphase operation provides several benefi ts over tra-
ditional single phase power supplies:
n Greater output current capability
n Improved transient response
n Reduction in component size
n Increased real world operating effi ciency
Because multiphase operation parallels power stages,
the amount of output current available is n times what it
would be with a single comparable output stage, where n
is equal to the number of phases.
The main advantages of PolyPhase operation are ripple
current cancellation in the input and output capacitors, a
faster load step response due to a smaller clock delay and
reduced thermal stress on the inductors and MOSFETs
due to current sharing between phases. These advantages
allow for the use of a smaller size or a smaller number
of components.
Power Good Indicator Pins (PGOOD1, PGOOD2)
Each PGOOD pin is connected to the open drain of an
internal pull-down device which pulls the PGOOD pin
low when the corresponding FB pin voltage is outside
the PGOOD regulation window (±7.5% entering regula-
tion, ±10% leaving regulation). The PGOOD pins are also
pulled low when the corresponding RUN pin is low, or
during UVLO.
In multiphase applications, one FB pin and error amplifi er
are used to control all of the phases. PGOOD outputs for
the slave phases may be left unconnected as they will not
report fault conditions.
PWM and PWMEN Pins
The PWM pins are three-state compatible outputs, de-
signed to drive MOSFET drivers, DRMOSs, etc which do
not represent a heavy capacitive load. An external resistor
divider may be used to set the voltage to mid-rail while in
the high impedance state.
The PWMEN outputs have an open-drain pull-up to VCC and
require an appropriate external pull-down resistor. This pin
is intended to drive the enable pins of the MOSFET driv-
ers that do not have three-state compatible PWM inputs.
PWMEN is low only when PWM is high impedance, and
high at any other PWM state.
OPERATION
(Refer to Functional Diagram)
LTC3860
14
3860fc
APPLICATIONS INFORMATION
Setting the Output Voltage
The LTC3860 regulates the FB pins to 0.6V. FB is con-
nected to VOUT or VSNSOUT (for remote output sensing)
via an external resistive divider as shown in Figure 3. The
divider sets the output voltage according to the following
equation:
VOUT =0.6V • 1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
Care should be taken to place the output divider resistors
and the compensation components as close as possible
to the FB pin to minimize switching noise coupling into
the control signal path.
Programming the Operating Frequency
The LTC3860 can be hard wired to one of two fi xed fre-
quencies, linearly programmed to any frequency between
250kHz and 1.25MHz or synchronized to an external
clock.
Table 1 in the Operation section shows how to connect the
CLKIN and FREQ pins to choose the mode of frequency
programming. In linear programming mode the frequency
of operation is given by the following equation:
Frequency (RFREQ – 15kΩ) • 20Hz/Ω
^
Figure 4 shows operating frequency vs RFREQ.
COMP
LTC3860
FB
RA
RB
VOUT
DIVIDER AND COMPENSATION
COMPONENTS PLACED NEAR
FB, SGND AND COMP PINS
COUT
3860 F03
SGND
Figure 3. Output Divider and Compensation
Component Placement
Sensing the Output Voltage with a
Differential Amplifi er
When using the remote sense differential amplifi er, care
should be taken to route the VSNSP and VSNSN PCB traces
parallel to each other all the way to the terminals of the
output capacitor or remote sensing points on the board.
In addition, avoid routing these sensitive traces near any
high speed switching nodes in the circuit. Ideally, they
should be shielded by a low impedance ground plane to
maintain signal integrity.
When using a single LTC3860 to regulate two output
voltages, the negative terminal of VOUT2 should be
kelvin-connected to SGND and the differential amplifi er
should be used to remotely sense VOUT1. This will maxi-
mize output voltage accuracy for both channels.
Figure 4. Operating Frequency vs RFREQ
Frequency Synchronization
The LTC3860 incorporates an internal phase-locked loop
(PLL) which enables synchronization of the internal os-
cillator (rising edge of PWM1) to an external clock from
250kHz to 1.25MHz.
Since the entire PLL is internal to the LTC3860, simply
applying a CMOS level clock signal to the CLKIN pin will
enable frequency synchronization. A resistor from FREQ
to GND is still required to set the free running frequency
close to the sync input frequency.
RFREQ (kΩ)
0
OSCILLATOR FREQUENCY (MHz)
0.7
0.9
1.1
60 100
3860 F04
0.5
0.3
0.1 20 40 80
1.3
1.5
1.7
120
LTC3860
15
3860fc
APPLICATIONS INFORMATION
Choosing the Inductor and Setting the Current Limit
The inductor value is related to the switching frequency,
which is chosen based on the trade-offs discussed in the
Operation section. The inductor can be sized using the
following equation:
L=VOUT
f•ΔIL
⎛
⎝
⎜⎞
⎠
⎟•1−VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
Choosing a larger value of ΔIL leads to smaller L, but re-
sults in greater core loss (and higher output voltage ripple
for a given output capacitance and/or ESR). A reasonable
starting point for setting the ripple current is 30% of the
maximum output current, or:
ΔIL = 0.3 • IOUT
The inductor saturation current rating needs to be higher
than the peak inductor current during transient conditions.
If IOUT is the maximum rated load current, then the maxi-
mum transient current, IMAX, would normally be chosen
to be some factor (e.g., 60%) greater than IOUT:
I
MAX = 1.6 • IOUT
The minimum saturation current rating should be set to
allow margin due to manufacturing and temperature varia-
tion in the sense resistor or inductor DCR. A reasonable
value would be:
I
SAT = 2.2 • IOUT
The programmed current limit must be low enough to
ensure that the inductor never saturates and high enough
to allow increased current during transient conditions and
allow margin for DCR variation.
For example, if:
I
SAT = 2.2 • IOUT
and
I
MAX = 1.6 • IOUT
A reasonable ILIMIT would be:
I
LIMIT = 2 • IOUT
If the sensed inductor current exceeds current limit, the
IC will three-state the PWM outputs, reset the soft-start
timer and wait 32768 switching cycles before attempting
to return the output to regulation.
The current limit is programmed using a resistor from the
ILIM pin to SGND. The ILIM pin sources 20μA to generate
a voltage corresponding to the current limit. The current
sense circuit has a voltage gain of 20 and a zero current
level of 500mV. Therefore, the current limit resistor should
be set using the following equation:
RILIM =18.5 • ILIMIT(SET) •R
SENSE +0.53V
20µA
In multiphase applications only one current limit resistor
should be used per LTC3860. The ILIM2 pin should be tied
to VCC. Internal logic will then cause channel 2 to use the
same current limit levels as channel 1. If an LTC3860 has
a slave and an independent, then both ILIM pins must be
independently set to the right voltage.
Inductor Core Selection
Once the value of L is known, the type of inductor must be
selected. High effi ciency converters generally cannot afford
the core losses found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Also, core losses decrease as inductance increases.
Unfortunately, increased inductance requires more turns
of wire, larger inductance and larger copper losses.
Ferrite designs have very low core loss and are preferred at
high switching frequencies. However, these core materials
exhibit “hard” saturation, causing an abrupt reduction in the
inductance when the peak current capability is exceeded.
Do not allow the core to saturate!
CIN Selection
The input bypass capacitor in an LTC3860 circuit is com-
mon to both channels. The input bypass capacitor needs
to meet these conditions: its ESR must be low enough to
keep the supply drop low as the top MOSFETs turn on, its
RMS current capability must be adequate to withstand the
ripple current at the input, and the capacitance must be
large enough to maintain the input voltage until the input
LTC3860
16
3860fc
APPLICATIONS INFORMATION
supply can make up the difference. Generally, a capacitor
(particularly a non-ceramic type) that meets the fi rst two
parameters will have far more capacitance than is required
to keep capacitance-based droop under control.
The input capacitor’s voltage rating should be at least 1.4
times the maximum input voltage. Power loss due to ESR
occurs not only as I2R dissipation in the capacitor itself,
but also in overall battery effi ciency. For mobile applica-
tions, the input capacitors should store adequate charge
to keep the peak battery current within the manufacturer’s
specifi cations.
The input capacitor RMS current requirement is simpli-
fi ed by the multiphase architecture and its impact on the
worst-case RMS current drawn through the input network
(battery/fuse/capacitor). It can be shown that the worst-
case RMS current occurs when only one controller is
operating. The controller with the highest (VOUT)(IOUT)
product needs to be used to determine the maximum
RMS current requirement. Increasing the output current
drawn from the other out-of-phase controller will actually
decrease the input RMS ripple current from this maximum
value. The out-of-phase technique typically reduces the
input capacitor’s RMS ripple current by a factor of 30%
to 70% when compared to a single phase power supply
solution.
In continuous mode, the source current of the top N-channel
MOSFET is approximately a square wave of duty cycle
VOUT/VIN. The maximum RMS capacitor current is given
by:
IRMS ≈IOUT(MAX)
VOUT VIN –V
OUT
()
VIN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst-case condition is com-
monly used for design because even signifi cant deviations
do not offer much relief. The total RMS current is lower
when both controllers are operating due to the interleav-
ing of current pulses through the input capacitors. This
is why the input capacitance requirement calculated
above for the worst-case controller is adequate for the
dual controller design.
Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Always consult the
manufacturer if there is any question.
Ceramic, tantalum, OS-CON and switcher-rated electrolytic
capacitors can be used as input capacitors, but each has
drawbacks: ceramics have high voltage coeffi cients of
capacitance and may have audible piezoelectric effects;
tantalums need to be surge-rated; OS-CONs suffer from
higher inductance, larger case size and limited surface
mount applicability; and electrolytics’ higher ESR and
dryout possibility require several to be used. Sanyo
OS-CON SVP, SVPD series; Sanyo POSCAP TQC series
or aluminum electrolytic capacitors from Panasonic WA
series or Cornell Dubilier SPV series, in parallel with a
couple of high performance ceramic capacitors, can be
used as an effective means of achieving low ESR and high
bulk capacitance.
COUT Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step transients.
The output ripple ΔVOUT is approximately bounded by:
ΔVOUT ≤ΔILESR +1
8•f
SW •C
OUT
⎛
⎝
⎜⎞
⎠
⎟
where ΔIL is the inductor ripple current.
ΔIL may be calculated using the equation:
ΔIL=VOUT
L•f
SW
1– VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
Since ΔIL increases with input voltage, the output ripple
voltage is highest at maximum input voltage. Typically,
once the ESR requirement is satisfi ed, the capacitance is
adequate for fi ltering and has the necessary RMS current
rating.
LTC3860
17
3860fc
APPLICATIONS INFORMATION
Manufacturers such as Sanyo, Panasonic and Cornell Du-
bilier should be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has a good (ESR)(size)
product. An additional ceramic capacitor in parallel with
OS-CON capacitors is recommended to offset the effect
of lead inductance.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or transient current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount confi gurations. New special polymer surface
mount capacitors offer very low ESR also but have much
lower capacitive density per unit volume. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
output capacitor choices include the Sanyo POSCAP TPD,
TPE, TPF series, the Kemet T520, T530 and A700 series,
NEC/Tokin NeoCapacitors and Panasonic SP series. Other
capacitor types include Nichicon PL series and Sprague
595D series. Consult the manufacturer for other specifi c
recommendations.
Current Sensing
To maximize effi ciency the LTC3860 is designed to sense
current through the inductor’s DCR, as shown in Figure 6.
The DCR of the inductor represents the small amount
of DC winding resistance of the copper, which for most
inductors applicable to this application, is between 0.3
and 1mΩ. If the fi lter RC time constant is chosen to be
exactly equal to the L/DCR time constant of the inductor,
the voltage drop across the external capacitor is equal
to the voltage drop across the inductor DCR. Check the
manufacturer’s data sheet for specifi cations regarding the
inductor DCR in order to properly dimension the external
fi lter components. The DCR of the inductor can also be
measured using a good RLC meter.
Since the temperature coeffi cient of the inductor’s DCR is
3900ppm/°C, fi rst order compensation of the fi lter time
constant is possible by using fi lter resistors with an equal
but opposite (negative) TC, assuming a low TC capacitor is
used. That is, as the inductor’s DCR rises with increasing
temperature, the L/DCR time constant drops. Since we
want the fi lter RC time constant to match the L/DCR time
constant, we also want the fi lter RC time constant to drop
with increasing temperature. Typically, the inductance will
also have a small negative TC.
The ISNSP and ISNSN pins are the inputs to the current
comparators. The common mode range of the current
comparators is –0.3V to VCC + 0.1V. Continuous linear
operation is provided throughout this range, allowing
output voltages between 0.6V (the reference input to the
error amplifi ers) and VCC + 0.1V. The maximum differential
current sense input (VISNSP – VISNSN) is 50mV.
The high impedance inputs to the current comparators
allow accurate DCR sensing. However, care must be taken
not to fl oat these pins during normal operation.
Filter components mutual to the sense lines should be
placed close to the LTC3860, and the sense lines should
run close together to a Kelvin connection underneath
the current sense element (shown in Figure 5). Sensing
current elsewhere can effectively add parasitic induc-
tance and capacitance to the current sense element,
degrading the information at the sense terminals and
making the programmed current limit unpredictable. If
low value (<5mΩ) sense resistors are used, verify that
the signal across CF resembles the current through the
inductor, and reduce RF to eliminate any large step as-
sociated with the turn-on of the primary switch. If DCR
sensing is used (Figure 6b), sense resistor R1 should be
placed close to the switching node, to prevent noise from
coupling into sensitive small-signal nodes. The capacitor
C1 should be placed close to the IC pins.
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
INDUCTOR OR RSENSE 3860 F05
Figure 5. Sense Lines Placement with Inductor or Sense Resistor
LTC3860
18
3860fc
APPLICATIONS INFORMATION
Multiphase Operation
When the LTC3860 is used in a single output, multiphase
application, the slave error amplifi ers must be disabled by
connecting their FB pins to VCC. All current limits should be
set to the same value using only one resistor to SGND per IC.
ILIM2 should then be connected to VCC. These connections
are shown in Table 3. In a multiphase application all COMP,
RUN and TRACK/SS pins must be connected together.
For output loads that demand high current, multiple
LTC3860s can be daisychained to run out of phase to
provide more output current without increasing input and
output voltage ripple. The CLKIN pin allows the LTC3860
to synchronize to the CLKOUT signal of another LTC3860.
The CLKOUT signal can be connected to the CLKIN pin of
the following LTC3860 stage to line up both the frequency
and the phase of the entire system. Tying the PHSMD pin to
VCC, SGND or fl oating it generates a phase difference
(between CLKIN and CLKOUT) of 240°, 60° or 90° respec-
tively, and a phase difference (between CH1 and CH2) of
120°, 180° or 180°. Figure 7 shows the PHSMD connections
necessary for 3-, 4-, 6- or 12-phase operation. A total of
12 phases can be daisychained to run simultaneously out
of phase with respect to each other.
BOOST
TG
LTC4449
VIN
12V
TS VOUT
3860 F06a
RSESLL
SENSE RESISTOR
PLUS PARASITIC
INDUCTANCE
FILTER COMPONENTS PLACED
NEAR SENSE PINS
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
VLOGIC
VCC
5V
IN
BG
GND
RF
CF
RF
VINSNS
VCC
PWM
ISNSPISNSN
LTC3860
GND
(6a) Using a Resistor to Sense Current
BOOST
TG
LTC4449
VIN
12V
TS VOUT
3860 F06b
DCRL
R1*
INDUCTOR
VLOGIC
VCC
5V
IN
*PLACE R1 NEAR INDUCTOR
PLACE C1 NEAR ISNSP, ISNSN PINS
BG
GND
C1*
VINSNS
VCC
PWM
ISNSPISNSN
LTC3860
GND
R1 • C1 = L
DCR
(6b) Using the Inductor to Sense Current
Figure 6. Two Different Methods of Sensing Current
Table 3. Multiphase Confi gurations
CH1 CH2 FB1 FB2 ILIM1 ILIM2
Master Slave On Off
(FB = VCC)
Resistor
to GND
VCC
Slave Slave Off
(FB = VCC)
Off
(FB = VCC)
Resistor
to GND
VCC
Slave Additional
Output
Off
(FB = VCC)
On Resistor
to GND
Resistor
to GND
LTC3860
19
3860fc
APPLICATIONS INFORMATION
Figure 7a. 3-Phase Operation Figure 7b. 4-Phase Operation
Figure 7c. 6-Phase Operation
Figure 7d. 12-Phase Operation
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
VCC VCC
0, 120
+240
VSNSOUT1
VSNSOUT2
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
3960 F07a
LTC3860
240, 60
CLKOUT
TRACK/SS2
COMP1
COMP2
TRACK/SS1
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
VCC VCC
0, 180
+90
VSNSOUT1
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
3960 F07b
LTC3860
90, 270
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
VCC VCC
0, 180
+60 +60
VSNSOUT1
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
60, 240
CLKOUT
COMP1
COMP2
TRACK/SS1,2
VCC
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
3960 F07c
LTC3860
120, 300
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
VCC VCC
0, 180
+60
VSNSOUT1
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
60, 240
CLKOUT
COMP1
COMP2
TRACK/SS1,2
VCC
+60 +90
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
120, 300
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
VCC VCC
210, 30
+60
CLKOUT
COMP1
COMP2
TRACK/SS1,2
CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
LTC3860
270, 90
CLKOUT
COMP1
COMP2
TRACK/SS1,2
VCC
+60 CLKIN
PHSMD
FB1
FB2
ILIM2
ILIM1
IAVG
3960 F07d
LTC3860
330, 150
CLKOUT
COMP1
COMP2
TRACK/SS1,2
LTC3860
20
3860fc
APPLICATIONS INFORMATION
A multiphase power supply signifi cantly reduces the
amount of ripple current in both the input and output ca-
pacitors. The RMS input ripple current is divided by, and
the effective ripple frequency is multiplied by, the number
of phases used (assuming that the input voltage is greater
than the number of phases used times the output volt-
age). The output ripple amplitude is also reduced by the
number of phases used. Figure 8 graphically illustrates
the principle.
3860 F08
SW1 V
ICIN
ICOUT
SINGLE PHASE
SW1 V
SW2 V
ICIN
IL2
IL1
ICOUT
DUAL PHASE
RIPPLE
Figure 8. Single and 2-Phase Current Waveforms
DUTY FACTOR (VOUT/VIN)
0.1
DIC(P-P)
VO/L
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.3 0.5 0.6
3860 F09
0.2 0.4 0.7 0.8 0.
9
1 PHASE
2 PHASE
Figure 9. Normalized Output Ripple Current
vs Duty Factor [IRMS” 0.3 (DIC(PP))]
0
0.1
0.2
0.3
0.4
3860 F10
0.5
0.6
DUTY FACTOR (VOUT/VIN)
0.1
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
0.3 0.5 0.6
0.2 0.4 0.7 0.8 0.9
1 PHASE
2 PHASE
Figure 10. Normalized RMS Input Ripple Current
vs Duty Factor for 1 and 2 Output Stages
The worst-case RMS ripple current for a single stage de-
sign peaks at an input voltage of twice the output voltage.
The worst case RMS ripple current for a two stage design
results in peak outputs of 1/4 and 3/4 of input voltage.
When the RMS current is calculated, higher effective duty
factor results and the peak current levels are divided as
long as the current in each stage is balanced. Refer to
Application Note 19 for a detailed description of how
to calculate RMS current for the single stage switching
regulator. Figures 9 and 10 illustrate how the input and
output currents are reduced by using an additional phase.
For a 2-phase converter, the input current peaks drop in
half and the frequency is doubled. The input capacitor
requirement is thus reduced theoretically by a factor of
four! Just imagine the possibility of capacitor savings
with even higher number of phases!
Output Current Sharing
When multiple LTC3860s are daisychained to drive a com-
mon load, accurate output current sharing is essential to
achieve optimal performance and effi ciency. Otherwise,
if one stage is delivering more current than another, then
the temperature between the two stages will be different,
and that could translate into higher switch RDS(ON), lower
effi ciency, and higher RMS ripple. When the COMP and IAVG
pins of multiple LTC3860s are tied together, the amount
of output current delivered from each LTC3860 is actively
balanced by the IAVE loop. The SGND pins of the multiple
LTC3860s must be kelvined to the same point for optimal
current sharing.
LTC3860
21
3860fc
Dual-Channel Operation
The LTC3860 can control two independent power supply
outputs with no channel-to-channel interaction or jitter.
The following recommendations will ensure maximum
performance in this mode of operation:
n The output of channel 1 should be sensed using the
remote sense differential amplifi er. The SGND pins and
exposed pad and all local small-signal GND should then
be a Kelvin connection to the negative terminal of the
channel 2 output. This will provide the best possible
regulation on channel 2 without adversely affecting
channel 1.
n Due to internal logic used to determine the mode of
operation, separate current limit resistors should be
used for each channel in dual-channel operation, even
when the values are the same.
Table 4 shows the ILIM and EA confi guration for dual-
channel operation.
Table 4. Dual-Channel Confi guration
CH1 CH2 EA1 EA2 ILIM1 ILIM2
Independent Independent On On Resistor
to GND
Resistor
to GND
Tracking and Soft-Start (TRACK/SS Pins)
The start-up of the supply output is controlled by the volt-
age on the TRACK/SS pin for that channel. The LTC3860
regulates the FB pin voltage to the lower of the voltage
on the TRACK/SS pin and the internal 600mV reference.
APPLICATIONS INFORMATION
The TRACK/SS pin can therefore be used to program an
external soft-start function or allow the output supply to
track another supply during start-up.
External soft-start is enabled by connecting a capacitor
from the TRACK/SS pin to SGND. An internal 2.5μA current
source charges the capacitor, creating a linear voltage ramp
at the TRACK/SS pin, and causing the output supply to
rise smoothly from its prebiased value to its fi nal regulated
value. The total soft-start time is approximately:
tSS =CSS •600mV
2.5µA
Alternatively, the TRACK/SS pin can be used to track
another supply during start-up.
For example, Figure 11a shows the start-up of VOUT2 con-
trolled by the voltage on the TRACK/SS2 pin. Normally this
pin is used to allow the start-up of VOUT2 to track that of
VOUT1 as shown qualitatively in Figures 11a and 11b. When
the voltage on the TRACK/SS2 pin is less than the internal
0.6V reference, the LTC3860 regulates the FB2 voltage to
LTC3860
FB2
VOUT2
VOUT1
FB1
TRACK/SS2
R2B
R2A
3860 F11a
R1B
R1A
RTRACKA
RTRACKB
Figure 11b and 11c. Two Different Modes of Output Voltage Tracking
Figure 11a. Using the TRACK/SS Pin
TIME
(
11b
)
Coincident Trackin
g
VOUT1
VOUT2
OUTPUT VOLTAGE
TIME 3860 F11b_c
(
11c
)
Ratiometric Trackin
g
VOUT1
VOUT2
OUTPUT VOLTAGE
LTC3860
22
3860fc
the TRACK/SS2 pin voltage instead of 0.6V. The start-up
of VOUT2 may ratiometrically track that of VOUT1, according
to a ratio set by a resistor divider (Figure 11c):
VOUT1
VOUT2
=R2A
RTRACKA
•RTRACKA +RTRACKB
R2B +R2A
For coincident tracking (VOUT1 = VOUT2 during start-up),
R2A = RTRACKA
R2B = RTRACKB
The ramp time for VOUT2 to rise from 0V to its fi nal
value is:
tSS2 =tSS1 •0.6
VOUT1F
•RTRACKA +RTRACKB
RTRACKA
For coincident tracking,
tSS2 =tSS1 •VOUT2F
VOUT1F
where VOUT1F and VOUT2F are the fi nal, regulated values
of VOUT1 and VOUT2. VOUT1 should always be greater than
VOUT2 when using the TRACK/SS2 pin for tracking. If no
tracking function is desired, then the TRACK/SS2 pin may
be tied to a capacitor to ground, which sets the ramp time
to fi nal regulated output voltage. It is only possible to track
another supply that is slower than the internal soft-start
ramp. At the completion of tracking, the TRACK/SS pin
must be >620mV, so as not to affect regulation accuracy
and to ensure the part is in CCM mode.
APPLICATIONS INFORMATION
Feedback Loop Compensation
The LTC3860 is a voltage mode controller with a second
dedicated current sharing loop to provide excellent phase-
to-phase current sharing in multiphase applications. The
current sharing loop is internally compensated.
While Type 2 compensation for the voltage control loop
may be adequate in some applications (such as with the
use of high ESR bulk capacitors), Type 3 compensation,
along with ceramic capacitors, is recommended for opti-
mum transient response. Referring to Figure 12, the error
amplifi ers sense the output voltage at VOUT.
The positive input of the error amplifi er is connected to
an internal 600mV reference, while the negative input is
connected to the FB pin. The output is connected to COMP,
which is in turn connected to the line feedforward circuit
and from there to the PWM generator. To speed up the
overshoot recovery time, the maximum potential at the
COMP pin is internally clamped.
Unlike many regulators that use a transconductance (gm)
amplifi er, the LTC3860 is designed to use an inverting
summing amplifi er topology with the FB pin confi gured
as a virtual ground. This allows the feedback gain to be
tightly controlled by external components, which is not
possible with a simple gm amplifi er. In addition, the voltage
feedback amplifi er allows fl exibility in choosing pole and
zero locations. In particular, it allows the use of Type 3
compensation, which provides a phase boost at the LC
pole frequency and signifi cantly improves the control loop
phase margin.
–
+
VOUT
VREF
R1 R3
C3 R2 C1
GAIN (dB)
C2
FB
RBCOMP
FREQ
–1
–1+1
GAIN
PHASE
BOOST
0
PHASE (DEG)
–90
–180
–270
–380
3806 F12
Figure 12. Type 3 Amplifi er Compensation
LTC3860
23
3860fc
APPLICATIONS INFORMATION
In a typical LTC3860 circuit, the feedback loop consists
of the line feedforward circuit, the modulator, the external
inductor, the output capacitor and the feedback amplifi er
with its compensation network. All these components
affect loop behavior and need to be accounted for in the
loop compensation. The modulator consists of the PWM
generator, the output MOSFET drivers and the external
MOSFETs themselves. The modulator gain varies linearily
with the input voltage. The line feedforward circuit com-
pensates for this change in gain, and provides a constant
gain from the error amplifi er output to the inductor input
regardless of input voltage. From a feedback loop point of
view, the combination of the line feedforward circuit and
the modulator looks like a linear voltage transfer function
from COMP to the inductor input. It has fairly benign AC
behavior at typical loop compensation frequencies with
signifi cant phase shift appearing at half the switching
frequency.
The external inductor/output capacitor combination makes
a more signifi cant contribution to loop behavior. These
components cause a second order LC roll-off at the output
with 180° phase shift. This roll-off is what fi lters the PWM
waveform, resulting in the desired DC output voltage, but
this phase shift causes stability issues in the feedback loop
and must be frequency compensated. At higher frequen-
cies, the reactance of the output capacitor will approach
its ESR, and the roll-off due to the capacitor will stop,
leaving –20dB/decade and 90° of phase shift.
Figure 12 shows a Type 3 amplifi er. The transfer function
of this amplifi er is given by the following equation:
VCOMP
VOUT
=–1+sC1R2
()
1+s(R1+R3)C3
[]
sR1 C1+C2
()
1+s(C1//C2)R2
⎡
⎣⎤
⎦1+sC3R3
()
The RC network across the error amplifi er and the feed-
forward components R3 and C3 introduce two pole-zero
pairs to obtain a phase boost at the system unity-gain
frequency, fC. In theory, the zeros and poles are placed
symmetrically around fC, and the spread between the zeros
and the poles is adjusted to give the desired phase boost
at fC. However, in practice, if the crossover frequency
is much higher than the LC double-pole frequency, this
method of frequency compensation normally generates
a phase dip within the unity bandwidth and creates some
concern regarding conditional stability.
If conditional stability is a concern, move the error ampli-
fi er’s zero to a lower frequency to avoid excessive phase
dip. The following equations can be used to compute the
feedback compensation components value:
fSW =Switching frequency
fLC =1
2πLCOUT
fESR =1
2πRESR COUT
choose:
fC=Crossover frequency =fSW
10
fZ1(ERR) =fLC =1
2πR2C1
fZ2(RES) =fC
5=1
2πR1+R3
()
C3
fP1(ERR) =fESR =1
2πR2(C1// C2)
fP2(RES) =5fC=1
2πR3C3
Required error amplifi er gain at frequency fC:
A
≈40log 1+fC
fLC
⎛
⎝
⎜⎞
⎠
⎟
2
– 20log 1+fC
fESR
⎛
⎝
⎜⎞
⎠
⎟
2
– 20log AMOD
()
≈20logR2
R1 •
1+fLC
fC
⎛
⎝
⎜⎞
⎠
⎟1+fP2(RES)
fC
+fP2(RES) –f
Z2(RES)
fZ2(RES)
⎛
⎝
⎜⎞
⎠
⎟
1+fC
fESR
+fLC
fESR –f
LC
⎛
⎝
⎜⎞
⎠
⎟1+fP2(RES)
fC
⎛
⎝
⎜⎞
⎠
⎟
where AMOD is the modulator and line feedforward gain
and is equal to:
AMOD ≈VIN(MAX) •DC
MAX
VSAW
≈12V/V
LTC3860
24
3860fc
APPLICATIONS INFORMATION
Once the value of resistor R1, poles and zeros location
have been decided, the value of R2, C1, C2, R3 and C3
can be obtained from the previous equations.
Compensating a switching power supply feedback loop
is a complex task. The applications shown in this data
sheet show typical values, optimized for the power
components shown. Though similar power compon-
ents should suffi ce, substantially changing even one
major power component may degrade performance
signifi cantly. Stability also may depend on circuit board
layout. To verify the calculated component values, all
new circuit designs should be prototyped and tested
for stability.
Inductor
The inductor in a typical LTC3860 circuit is chosen for a
specifi c ripple current and saturation current. Given an
input voltage range and an output voltage, the inductor
value and operating frequency directly determine the
ripple current. The inductor ripple current in the buck
mode is:
ΔIL=VOUT
(f)(L) 1– VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Thus highest effi ciency operation is obtained at
low frequency with small ripple current. To achieve this
however, requires a large inductor.
A reasonable starting point is to choose a ripple cur-
rent between 20% and 40% of IO(MAX). Note that the
largest ripple current occurs at the highest VIN. To guar-
antee that ripple current does not exceed a specifi ed
maximum, the inductor in buck mode should be chosen
according to:
L≥VOUT
fΔIL(MAX)
1– VOUT
VIN(MAX)
⎛
⎝
⎜⎞
⎠
⎟
Power MOSFET Selection
The LTC3680 requires at least two external N-channel power
MOSFETs per channel, one for the top (main) switch and
one or more for the bottom (synchronous) switch. The
number, type and on-resistance of all MOSFETs selected
take into account the voltage step-down ratio as well as
the actual position (main or synchronous) in which the
MOSFET will be used. A much smaller and much lower
input capacitance MOSFET should be used for the top
MOSFET in applications that have an output voltage that
is less than 1/3 of the input voltage. In applications where
VIN >> VOUT, the top MOSFETs’ on-resistance is normally
less important for overall effi ciency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with signifi cantly
reduced input capacitance for the main switch application
in switching regulators.
Selection criteria for the power MOSFETs include the on-
resistance RDS(ON), input capacitance, breakdown voltage
and maximum output current.
For maximum effi ciency, on-resistance RDS(ON) and input
capacitance should be minimized. Low RDS(ON) minimizes
conduction losses and low input capacitance minimizes
switching and transition losses. MOSFET input capacitance
is a combination of several components but can be taken
from the typical “gate charge” curve included on most
data sheets (Figure 13).
+
–VDS
VIN
VGS
MILLER EFFECT
QIN
ab
CMILLER = (QB – QA)/VDS
VGS V
+
–
3860 F12
Figure 13. Gate Charge Characteristic
LTC3860
25
3860fc
APPLICATIONS INFORMATION
The curve is generated by forcing a constant input cur-
rent into the gate of a common source, current source
loaded stage and then plotting the gate voltage versus
time. The initial slope is the effect of the gate-to-source
and the gate-to-drain capacitance. The fl at portion of the
curve is the result of the Miller multiplication effect of the
drain-to-gate capacitance as the drain drops the voltage
across the current source load. The upper sloping line
is due to the drain-to-gate accumulation capacitance
and the gate-to-source capacitance. The Miller charge
(the increase in coulombs on the horizontal axis from
a to b while the curve is fl at) is specifi ed for a given
VDS drain voltage, but can be adjusted for different VDS
voltages by multiplying by the ratio of the application
VDS to the curve specifi ed VDS values. A way to estimate
the CMILLER term is to take the change in gate charge
from points a and b on a manufacturers data sheet and
divide by the stated VDS voltage specifi ed. CMILLER is
the most important selection criteria for determining
the transition loss term in the top MOSFET but is not
directly specifi ed on MOSFET data sheets. CRSS and
COS are specifi ed sometimes but defi nitions of these
parameters are not included.
When the controller is operating in continuous mode
the duty cycles for the top and bottom MOSFETs are
given by:
Main Switch Duty Cycle =VOUT
VIN
Synchronous Switch Duty Cycle =VIN –V
OUT
VIN
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
P
MAIN =VOUT
VIN
IMAX
()
2(1+δ)RDS(ON) +
VIN
2IMAX
2(RDR )(CMILLER)•
1
VCC –V
TH(IL)
+1
VTH(IL)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥(f)
PSYNC =VIN −VOUT
VIN
(IMAX)2(1+δ)RDS(0N)
where δ is the temperature dependency of RDS(ON), RDR
is the effective top driver resistance, VIN is the drain po-
tential and the change in drain potential in the particular
application. VTH(IL) is the data sheet specifi ed typical gate
threshold voltage specifi ed in the power MOSFET data sheet
at the specifi ed drain current. CMILLER is the calculated
capacitance using the gate charge curve from the MOSFET
data sheet and the technique previously described.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve. Typical
values for δ range from 0.005/°C to 0.01/°C depending
on the particular MOSFET used.
Multiple MOSFETs can be used in parallel to lower RDS(ON)
and meet the current and thermal requirements if desired.
Suitable drivers such as the LTC4449 are capable of driv-
ing large gate capacitances without signifi cantly slowing
transition times. In fact, when driving MOSFETs with very
low gate charge, it is sometimes helpful to slow down
the drivers by adding small gate resistors (5Ω or less) to
reduce noise and EMI caused by the fast transitions
MOSFET Driver Selection
Gate driver ICs, DRMOSs and power blocks with an interface
compatible with the LTC3860’s three-state PWM outputs
or the LTC3860’s PWM/PWMEN outputs can be used.
LTC3860
26
3860fc
APPLICATIONS INFORMATION
Effi ciency Considerations
The effi ciency of a switching regulator is equal to the
output power divided by the input power. It is often useful
to analyze individual losses to determine what is limiting
the effi ciency and which change would produce the most
improvement. Percent effi ciency can be expressed as:
%Effi ciency = 100% - (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the system produce
losses, three main sources usually account for most of the
losses in LTC3860 applications: 1) I2R losses, 2) topside
MOSFET transition losses, 3) gate drive current.
1. I2R losses occur mainly in the DC resistances of the
MOSFET, inductor, PCB routing, and input and output
capacitor ESR. Since each MOSFET is only on for part
of the cycle, its on-resistance is effectively multiplied
by the percentage of the cycle it is on. Therefore in high
step-down ratio applications the bottom MOSFET should
have a much lower RDS(ON) than the top MOSFET. It
is crucial that careful attention is paid to the layout of
the power path on the PCB to minimize its resistance.
In a 2-phase, 1.2V output, 60A system, 1mΩ of PCB
resistance at the output costs 5% in effi ciency.
2. Transition losses apply only to the topside MOSFET but
in 12V input applications are a very signifi cant source
of loss. They can be minimized by choosing a driver
with very low drive resistance and choosing a MOSFET
with low QG, RG and CRSS.
3. Gate drive current is equal to the sum of the top and
bottom MOSFET gate charges multiplied by the fre-
quency of operation. However, many drivers employ a
linear regulator to reduce the input voltage to a lower
gate drive voltage. This multiplies the gate loss by that
step down ratio. In high frequency applications it may
be worth using a secondary user supplied rail for gate
drive to avoid the linear regulator.
Other sources of loss include body or Schottky diode
conduction during the driver dependent non-overlap time
and inductor core losses.
Design Example
As a design example, consider a 2-phase application
where VIN = 12V, VOUT = 1.2V, ILOAD = 50A and fSWITCH =
600kHz. Assume that a secondary 5V supply is available
for the LTC3860 VCC supply.
The inductance value is chosen based on a 30% ripple
assumption. Each channel supplies an average 25A to the
load resulting in 7.5A peak-peak ripple:
ΔIL=
VOUT •1–
VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
f•L
A 240nH inductor per phase will create 7.5A peak-to-peak
ripple. A 0.3μH inductor with a DCR of 0.7mΩ typical
is selected from the Vishay IHLP5050FD-01 series.
Connect CLKIN to SGND and FREQ to VCC to select
600kHz operation. Setting ILIMIT = 50A per phase leaves
plenty of headroom for transient conditions while still
adequately protecting against inductor saturation. This
corresponds to:
RILIM =18.5 • 50A • 0.7mΩ+0.53V
20µA =58.8k
Ω
Choose 59.0kΩ.
For the DCR sense fi lter network, we can choose R = 2.0k
and C = 220nF to match the L/DCR time constant of the
inductor.
A loop crossover frequency of 100kHz provides good
transient performance while still being well below the
switching frequency of the converter. Four 330μF 9mΩ
POSCAPs are chosen for the output capacitors to maintain
supply regulation during severe transient conditions and
to minimize output voltage ripple.
The following compensation values (Figure 12) were
determined empirically:
R1 = 10k
R2 = 6.04k
R3 = 698
C1 = 680pF
C2 = 47pF
C3 = 390pF
LTC3860
27
3860fc
APPLICATIONS INFORMATION
To set the output voltage equal to 1.2V:
R
B = 10k
The Renesas R2J20602NP integrated-driver MOSFET is
chosen for the power stages because of its high effi ciency
and high level of integration.
Printed Circuit Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the converter.
1. The connection between the SGND pin on the LTC3860
and all of the small-signal components surrounding the
IC should be isolated from the system power ground.
Place all decoupling capacitors, such as the ones on
VCC, between ISNSP and ISNSN etc., close to the IC. In
multiphase operation SGND should be Kelvin-connected
to the main ground node near the bottom terminal of
the input capacitor. In dual-channel operation, SGND
should be Kelvin-connected to the bottom terminal of
the output capacitor for channel 2, and channel 1 should
be remotely sensed using the remote sense differential
amplifi er.
2. Place the small-signal components away from high
frequency switching nodes on the board. The LTC3860
contains remote sensing of output voltage and inductor
current and logic-level PWM outputs enabling the IC to
be isolated from the power stage.
3. The PCB traces for remote voltage and current sense
should avoid any high frequency switching nodes in
the circuit and should ideally be shielded by ground
planes. Each pair (VSNSP and VSNSN, ISNSP and
ISNSN) should be routed parallel to one another with
minimum spacing between them. If DCR sensing is
used, place the top resistor (Figure 6b, R1) close to
the switching node.
4. The input capacitor should be kept as close as possible
to the power MOSFETs. The loop from the input capaci-
tor’s positive terminal, through the MOSFETs and back
to the input capacitor’s negative terminal should also
be as small as possible.
5. If using discrete drivers and MOSFETs, check the
stress on the MOSFETs by independently measuring
the drain-to-source voltages directly across the device
terminals. Beware of inductive ringing that could exceed
the maximum voltage rating of the MOSFET. If this
ringing cannot be avoided and exceeds the maximum
rating of the device, choose a higher voltage rated
MOSFET.
6. When cascading multiple LTC3860 ICs, minimize
the capacitive load on the CLKOUT pin to minimize
phase error. Kelvin all the LTC3860 IC grounds to the
same point, typically SGND of the IC containing the
master.
LTC3860
28
3860fc
TYPICAL APPLICATIONS
Dual Output with DRMOS
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
VDIFF1
VOS1N
VOS1P
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWM2
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
PWM1
RUN1
LTC3860
SGND
PWMEN1,2
470pF
220Ω
VDIFF1
VOUT2
VCC
VCC
VCC
VCIN
DISABLE
PWM
VIN
R2J20602
REG5V BOOT
SW1
SW2
VSWH
VLDRV
2.2Ω
2.2Ω
5V
CGND PGND
VCIN
PWM
DISABLE
VIN
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCC
5V
20k
20k
1μF
0.22μF
0.22μF
VIN
7V TO 14V 470μF
4.7μF
4.7μF
1μF
22μF
47μF
s3
47μF
s3
330μF
s3
VOUT1
1.2V
25A
330μF
s3
VOUT2
1.8V
25A
3860 TA02
VIN
0.22μF
0.3μH
0.22μF
1μF
4.7μF
4.7μF
22μF
4.7k
47pF
1000pF
470pF 0.1μF
FREQ SET FOR 600kHz
45.3k 100k
49.9k
OPEN
(OPT)
7V TO 14V IN AND 1.2V/1.8V OUT AT 25A
fSW = 600kHz, DCR SENSING
CH1 TRACKS CH2, CH1 USES DIFFAMP
NOTE 1: PLEASE REFER TO THE R2J20602 DATA SHEET
FOR THE MOST UP TO DATE PINOUT
NOTE 2: PLEASE REFER TO THE PIN CONFIGURATION
OF THIS DATA SHEET FOR THE LTC3860 PINOUT
OPEN
(OPT)
PWM2
VCC
220Ω
VOUT2
CLKOUT
RUN2
20k
10k
20k
20k
100k
49.9k
PWM1
OPEN
OPEN
(OPT)
4.7k
47pF
1000pF
RUN1
0.3μH
47Ω
2.74k
2.74k
47Ω
VOS1P
VOS1N
LTC3860
29
3860fc
TYPICAL APPLICATIONS
Quad-Phase Single Output with DRMOS
VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VDIFF
VOSN
VOSP
VCC
VCC
RUN1
VCC
TRACK/SS1
PWM2
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
LTC3860
0.01μF
470μF
22μF
1μF
VIN
7V TO 14V
VCC
5V
RUN1
VDIFF
TRACK/SS1
100k
49.9k
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
PWM1
PWM3
100pF
IAVG1
2.2Ω
0.22μF
SW1
SW2
5V
0.22μF
0.22μF
VCC VCC
47pF
1000pF
COMP1
470pF
4.7k
220Ω20k
20k
4.7μF
1μF
VIN
2.2Ω
VIN
0.22μF
5V
VCC
22μF
4.7μF
1μF
2k
2k
VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VCC
VCC
VCC
RUN1
TRACK/SS1
PWM4
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
LTC3860
470μF
22μF
47μF
6.3V
s8
0.4μH
0.4μH
0.4μH
0.4μH
1μF
VIN
7V TO 14V
VCC
5V
RUN1
TRACK/SS1 IAVG1
49.9k
OPEN
(OPT)
45.3k
OPEN
(OPT)
2.2Ω
0.22μF
SW3
SW4
3860 TA03
5V
0.22μF
0.22μF
VCC
4.7μF
1μF
VIN
2.2Ω
VIN
0.22μF
5V
330μF
2.5V
s8
VOUT1
1.2V
100A
VCC
22μF
4.7μF
1μF
2k
2k
47Ω
47Ω
VOSN
VOSP
VCIN
DISABLE
PWM
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
DISABLE
PWM
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
PWM
DISABLE
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
PWM
DISABLE
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
4.7μF
4.7μF
4.7μF
4.7μF
LTC3860
30
3860fc
TYPICAL APPLICATIONS
Dual-Phase Single Output with Discrete Drivers and MOSFETs
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
VDIFF1
VOS1N
VOS1P
VCC
VCC
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWM2
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
PWM1
RUN1
LTC3860
220pF
1.33k
VDIFF1
VCC
VCC
5V
20k
20k
1μF
PWMEN1,2
SGND
0.22μF
0.22μF
VIN
7V TO 14V 470μF 100pF
0.22μF
SW1
SW1 0.3μH
12.7k
33pF
1.5nF
FREQ SET FOR 600kHz
45.3k
7V TO 14V IN AND 1.2V OUT AT 50A
fSW = 600kHz, DCR SENSING
PWM2
SS1
CLKOUT
RUN2
0.1μF
TRACK/SS1
100k
49.9k
2.2Ω
1μF
4.7μF
VCC
PWM1
RUN1
IN
VLOGIC
VCC
BOOST
4
3
2
1
5
6
7
8
4
3
2
1
5
6
7
8
GND
BG
TS
TG
LTC4449 RJK0305DPB
VIN
BG1
TG1
RJK0330DPB
RJK0305DPB
RJK0330DPB
RJK0305DPB
RJK0330DPB
RJK0305DPB
RJK0330DPB
22μF
s2
47μF
s3
330μF
s3
47Ω VOUT1
1.2V
50A
VOS1P
VOS1N
47Ω2.74k
2.74k
0.22μF
SW2
SW2 0.3μH
2.2Ω
1μF
4.7μF
VCC
IN
VLOGIC
VCC
BOOST
GND
BG
TS
TG
LTC4449
VIN
BG2
TG2
22μF
s2
47μF
s3
330μF
s3
3860 TA04
NOTE: PLEASE REFER TO THE PIN CONFIGURATION
OF THIS DATA SHEET FOR THE LTC3860 PINOUT
LTC3860
31
3860fc
TYPICAL APPLICATIONS
Dual Output—3-Channel + Single Channel, Synchronized to External Clock
VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VDIFF
VOSN
VOSP
VCC
VCC
RUN1
TRACK/SS1
PWM2
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
LTC3860
0.01μF
470μF 22μF
1μF
VIN
7V TO 14V
VCC
5V
RUN1
VDIFF1
CLOCKIN
600kHz
SYNC INPUT
TRACK/SS1
100k
49.9k
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
PWM1
IAVG1
PWM3
100pF
2.2Ω
0.22μF
SW1
SW2
5V
0.22μF
0.22μF
VCC VCC
47pF
1000pF
COMP1
470pF
4.7k
220Ω20k
20k
47pF
1000pF
470pF
4.7k
220Ω
VDIFF4
20k
10k
45.3k
4.7μF
1μF
VIN
2.2Ω
VIN
0.22μF
5V
VCC
22μF
4.7μF
1μF
2.3k
2.3k
VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VOS4P
VOS4N
VCC
COMP1
PWM4
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
LTC3860
470μF
22μF
47μF
6.3V
s6
0.3μH
0.3μH
0.3μH
0.3μH
1μF
VIN
7V TO 14V
VCC
5V
RUN1
TRACK/SS1 IAVG1
49.9k
49.9k
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
45.3k 100k
VCC OPEN
(OPT)
2.2Ω
0.22μF
SW3
SW4
3860 TA05
5V
0.22μF
0.22μF
0.01μF
RUN2
VCC
4.7μF
1μF
VIN
2.2Ω
VIN
0.22μF
5V
330μF
2.5V
s6
VOUT1
1.2V
75A
VCC
22μF
4.7μF
1μF
2.32k
2.32k
47Ω
VOSP
47μF
s3
330μF
s3
VOUT4
1.8V
25A
47Ω
VOS4P
VCIN
DISABLE
PWM
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
DISABLE
PWM
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
PWM
DISABLE
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
PWM
DISABLE
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
47Ω
VOSN
47Ω
VOS4N
4.7μF
4.7μF
VCC
4.7μF
4.7μF
LTC3860
32
3860fc
TYPICAL APPLICATIONS
2-Phase 1.5V/40A Converter with Delta 20A Power Blocks and External 400kHz Clock
VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VDIFF
VOSN
VOSP
VCC
VCC
RUN1
TRACK/SS1
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
LTC3860
0.1μF
470μF
1μF
VIN
7V TO 14V
VCC
5V
RUN1
VDIFF
CLOCKIN
400kHz
SYNC INPUT
TRACK/SS1
100k 59k
IAVG1
100pF
22μF
VCC
OPEN
OPT
5V BIAS
0.22μF
OPEN
OPT
VCC
100pF
2200pF COMP1
470pF
6.8k
523Ω20k
13.3k
34.8k
10k
22μF
VIN
100μF
6.3V
100μF
6.3V
3860 TA06
10k
47Ω
47Ω
VOSP
VOSN
0.22μF
5V
GND2
PWM
TEMP
GND1
VIN
ENABLE
CSP
CSN
VOUT
D12S36A
22μF
PWM2
PWM1
VCC
OPEN
OPT
5V BIAS
OPEN
OPT
22μF
330μF
2.5V
s6
VOUT
1.5V
40A
VIN
5V
GND2
PWM
TEMP
GND1
VIN
ENABLE
CSP
CSN
VOUT
D12S36A
LTC3860
33
3860fc
TYPICAL APPLICATIONS
Dual Output Converter with Emerson 30A (SMT30PB-O1SADJJ) Power Blocks
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VDIFF1
VOS1N
VOS1P
VCC
TRACK/SS1
VINSNS
IAVG
PGOOD1
PWM1
RUN1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWM2
LTC3860
PWMEN1,2
SGND
0.1μF
470μF
1μF
0.1μF
VIN
8V TO 14V
VCC
5V
RUN1
VDIFF1
100k
59k
PWM1
PWM2
VCC
0.22μF
VCC
100pF
2200pF
470pF
6.8k
523Ω20k
29.4k
VOUT2
RUN2
8V TO 14V IN AND 1.0V/1.8V OUT AT 25A
fSW = 400kHz
CH1 USES DIFFAMP
100pF
2200pF
470pF
6.8k
523Ω20k
10k
34.8k 100k
59k
100μF
s2
3860 TA07
100μF
s2
51Ω
51Ω
VOS1P
VOS1N
GND
0.22μF
1μF
VCC
OPEN
OPT
7V BIAS
OPEN
OPT
22μF
330μF
s3
GND
330μF
s3
VOUT1
1V
30A
VOUT2
1.8V
30A
VIN
7V
TEMP
PWM
GND
VIN
VOUT
CSP
CSN
1μF
VCC
OPEN
OPT
OPEN
OPT
7V BIAS
22μF
VIN
7V
TEMP
PWM
GND
VIN
VOUT
CSP
CSN
SMT30PB-
01SADJJ
SMT30PB-
01SADJJ
LTC3860
34
3860fc
PACKAGE DESCRIPTION
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693 Rev D)
5.00 p 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 p 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.50 REF
(4-SIDES)
3.45 p 0.10
3.45 p 0.10
0.75 p 0.05 R = 0.115
TYP
0.25 p 0.05
(UH32) QFN 0406 REV D
0.50 BSC
0.200 REF
0.00 – 0.05
0.70 p0.05
3.50 REF
(4 SIDES)
4.10 p0.05
5.50 p0.05
0.25 p 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 s 45o CHAMFER
R = 0.05
TYP
3.45 p 0.05
3.45 p 0.05
LTC3860
35
3860fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 04/10 Updates to Features 1
Updates to Absolute Maximum Ratings, Order Information sections, Electrical Characteristics heading and Note 2 2, 3, 4
Update to Design Example section 27
Updates to Typical Applications 30, 31, 33, 35, 38
B 10/10 Updated Electrical Characteristics section 2, 3, 4
Updated Pin Functions 8
Updated Frequency Selection and the Phase Locked Loop (PLL) section 12
Updated Theory and Benefi ts of Multiphase Operation section 13
Updated equations 15, 27
Updated Typical Applications 28, 29, 31-33, 36
Updated Related Parts 36
C 03/11 Updated VFB and IFREQ specifi cations in the Electrical Characteristics section
Updated Pin 10 and Pin 28 text in Pin Functions
Updated Functional Diagram
Updated text in Current Sharing section
Updated Equation
Updated Related Parts
3, 4
8
9
10
23
36
LTC3860
36
3860fc
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2010
LT 0311 REV C • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3850/LTC3850-1
LTC3850-2
Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller,
RSENSE or DCR Current Sensing
PLL Fixed 250kHz to 780kHz Frequency, 4V ≤ VIN ≤ 30V,
0.8V ≤ VOUT ≤ 5.25V
LTC3869/
LTC3869-2
Dual Output, 2-Phase Synchronous Step-Down DC/DC Controller
with Accurate Current Share
PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ VIN ≤ 38V,
VOUT3 Up to 12.5V
LTC3856 Single Output 2-Phase Synchronous Step-Down DC/DC
Controller with Diff Amp and DCR Temperature Compensation
PLL Fixed 250kHz to 770kHz Frequency, 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 5V
LTC3855 Dual Output, 2-Phase, Synchronous Step-Down DC/DC Controller
with Diff Amp and DCR Temperature Compensation
PLL Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 12V
LTC3775 High Frequency Synchronous Voltage Mode Step-Down DC/DC
Controller
Very Fast Transient Response, tON(MIN) = 30ns, 4V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 0.8VIN, MSOP-16E, 3mm × 3mm QFN-16
LTC3853 Triple Output, Multiphase Synchronous Step-Down DC/DC
Controller, RSENSE or DCR Current Sensing and Tracking
PLL Fixed 250kHz to 750kHz Frequency, 4V ≤ VIN ≤ 24V,
VOUT3 Up to 13.5V
LTC4449 High Speed Synchronous N-Channel MOSFET Driver VIN Up to 38V, 4V ≤ VCC ≤ 6.5V Adaptive Shoot-Through
Protection, 2mm × 3mm DFN-8 Package
LTC4442/LTC4442-1 High Speed Synchronous N-Channel MOSFET Driver VIN Up to 38V, 6V ≤ VCC ≤ 9V Adaptive Shoot-Through
Protection, MSOP-8 Package
LTC3880/LTC3880-1 Dual Output PolyPhase Step-Down DC/DC Controller with Digital
Power System Management
VIN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Analog Control Loop,
I2C/PMBus Interface with EEPROM and 16-Bit ADC
TYPICAL APPLICATION
VCC
FB1
COMP1
VSNSOUT
VSNSN
VSNSP
COMP2
FB2
RUN1
ILIM1
ISNS1P
ISNS1N
ISNS2N
ISNS2P
ILIM2
RUN2
VDIFF
VOSN
VOSP
VCC
VCC
RUN1
TRACK/SS1
PWM2
TRACK/SS1
VINSNS
SGND
SGND
IAVG
PGOOD1
PWMEN1
PWM1
TRACK/SS2
FREQ
CLKIN
CLKOUT
PHSMD
PGOOD2
PWMEN2
PWM2
LTC3860
0.01μF
470μF 4.7μF 22μF
1μF
VIN
7V TO 14V
VCC
5V
RUN1
VDIFF1
CLOCKIN
600kHz
SYNC INPUT
TRACK/SS1
100k
59.0k
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
OPEN
(OPT)
PWM1
IAVG1
100pF
2.2Ω
0.22μF
SW1
SW2
5V
100Ω
0.01μF
0.01μF
VCC VCC
47pF
1000pF
COMP1
470pF
4.7k
220Ω20k
20k
45.3k
4.7μF
1μF
VIN
1mΩ
2.2Ω
VIN
0.22μF
5V
4.7μF
VCC
22μF
4.7μF
1μF
47μF
6.3V
s4
0.3μH
0.3μH
330μF
2.5V
s4
VOUT1
1.2V
40A
47Ω
3860 TA08
VOSP
VCIN
DISABLE
PWM
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
VCIN
PWM
DISABLE
VIN
R2J20602
REG5V BOOT
VSWH
VLDRV
CGND PGND
1mΩ
47Ω
VOSN
Dual Phase Single Output with DRMOS and RSENSE
