8 7
3 4
2
1
5
6
VO-GND
VDD VO+
SD
IN-
IN+
BYP
IN-
IN+
VDD
VO+
GND
VO-
BYP
SD
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LM4923 1.1 Watt Fully Differential Audio Power Amplifier
With Shutdown Select
Check for Samples: LM4923,LM4923LQBD
1FEATURES DESCRIPTION
The LM4923 is a fully differential audio power
2• Fully Differential Amplification amplifier primarily designed for demanding
• Available in Space-saving WQFN Package applications in mobile phones and other portable
• Ultra Low Current Shutdown Mode communication device applications. It is capable of
delivering 1.1 watt of continuous average power to an
• Can Drive Capacitive Loads up to 100pF 8ΩBTL load with less than 1% distortion (THD+N)
• Improved Pop & Click Circuitry Eliminates from a 5VDC power supply.
Noises During Turn-on and Turn-off Boomer audio power amplifiers were designed
Transitions specifically to provide high quality output power with a
• 2.4 - 5.5V Operation minimal amount of external components. The
• No Output Coupling Capacitors, Snubber LM4923 does not require output coupling capacitors
Networks or Bootstrap Capacitors Required or bootstrap capacitors, and therefore is ideally suited
for mobile phone and other low voltage applications
where minimal power consumption is a primary
APPLICATIONS requirement.
• Mobile Phones The LM4923 features a low-power consumption
• PDAs shutdown mode. To facilitate this, Shutdown may be
• Portable Electronic Devices enabled by logic low. Additionally, the LM4923
features an internal thermal shutdown protection
KEY SPECIFICATIONS mechanism.
• Improved PSRR at 217Hz 85dB(typ) The LM4923 contains advanced pop & click circuitry
• Power Output at 5.0V @ 1% THD+N 1.1W(typ) which eliminates noises which would otherwise occur
during turn-on and turn-off transitions.
• Power Output at 3.3V @ 1% THD+N
400mW(typ)
• Shutdown Current 0.1μA(typ)
Connection Diagrams
Figure 1. NGP Package, Top View Figure 2. 8 Pin VSSOP Package, Top View
See Package Number NGP0008A See Package Number DGK0008A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SD
BYP
- Differential Input -IN
+ Differential Input +IN
-
+
VO+
VO-
GND
VDD
CS
1 PF
+
RL
8:
+
-
Ri1
Ri2
RF2
RF1
Common
Mode
Bias
CB
1.0 PF
20 k:
20 k:
20 k:
20 k:
LM4923, LM4923LQBD
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Typical Application
Figure 3. Typical Audio Amplifier Application Circuit
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation(3) Internally Limited
ESD Susceptibility(4) 2000V
ESD Susceptibility(5) 200V
Junction Temperature 150°C
Thermal Resistance θJA (WQFN) 140°C/W
θJA (DGK) 210°C/W
θJC (DGK) 56°C/W
Soldering Information
See AN-1187 (SNOA401)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature
TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4923, see power derating curve for additional information.
(4) Human body model, 100pF discharged through a 1.5kΩresistor.
(5) Machine Model, 220pF – 240pF discharged through all pins.
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Electrical Characteristics VDD = 5V(1)(2)
The following specifications apply for VDD = 5V, AV= 1, and 8Ωload unless otherwise specified. Limits apply for TA= 25°C.
LM4923 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)
IDD Quiescent Power Supply Current VIN = 0V, no load 4 9 mA (max)
VIN = 0V, RL= 8Ω4 9
ISD Shutdown Current VSHUTDOWN = GND 0.1 1 µA (max)
PoOutput Power THD = 1% (max); f = 1 kHz
LM4923, RL= 8Ω1.1 1
THD+N Total Harmonic Distortion+Noise Po= 0.4 Wrms; f = 1kHz 0.02 %
PSRR Power Supply Rejection Ratio Vripple = 200mV sine p-p
f = 217Hz(5) 85 73
f = 1kHz(5) 85 73
CMRR Common_Mode Rejection Ratio f = 217Hz, 50 dB
VCM = 200mVpp
VOS Output Offset VIN = 0V 4 mV
VSDIH Shutdown Voltage Input High 0.9 V
VSDIL Shutdown Voltage Input Low 0.7 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(5) 10Ωterminated input.
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Electrical Characteristics VDD = 3V(1) (2)
The following specifications apply for VDD = 3V, AV= 1, and 8Ωload unless otherwise specified. Limits apply for TA= 25°C.
LM4923 Units
Symbol Parameter Conditions (Limits)
Typical(3) Limit(4)
IDD Quiescent Power Supply Current VIN = 0V, no load 3 5.5 mA (max)
VIN = 0V, RL= 8Ω3 5.5
ISD Shutdown Current VSHUTDOWN = GND 0.1 1 µA (max)
PoOutput Power THD = 1% (max); f = 1kHz 0.375 W
LM4923, RL= 8Ω
THD+N Total Harmonic Distortion+Noise Po= 0.25Wrms; f = 1kHz 0.02 %
PSRR Power Supply Rejection Ratio Vripple = 200mV sine p-p
f = 217Hz (5) 85
f = 1kHz (5) 85 73
CMRR Common-Mode Rejection Ratio f = 217Hz 50 dB
VCM = 200mVpp
VOS Output Offset VIN = 0V 4 mV
VSDIH Shutdown Voltage Input High 0.8 V
VSDIL Shutdown Voltage Input Low 0.6 V
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(5) 10Ωterminated input.
EXTERNAL COMPONENTS DESCRIPTION
(Figure 3)
Components Functional Description
1. RiInverting input resistance which sets the closed-loop gain in conjunction with Rf.
2. RfFeedback resistance which sets the closed-loop gain in conjunction with Ri.
3. CSSupply bypass capacitor which provides power supply filtering. Refer to the Power Supply Bypassing section for
information concerning proper placement and selection of the supply bypass capacitor.
4. CBBypass pin capacitor which provides half-supply filtering. Refer to the section, Proper Selection of External
Components, for information concerning proper placement and selection of CB.
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20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
20 Hz
1 kHz
20 kHz
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
20 100 1k 10k 20k
0.001
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
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Typical Performance Characteristics
THD+N THD+N
vs vs
Frequency Frequency
VDD = 2.6V, RL= 8Ω, PO= 150mW VDD = 2.6V, RL= 4Ω, PO= 150mW
Figure 4. Figure 5.
THD+N THD+N
vs vs
Frequency Frequency
VDD = 5V, RL= 8Ω, PO= 400mW VDD = 3V, RL= 8Ω, PO= 275mW
Figure 6. Figure 7.
THD+N THD+N
vs vs
Frequency Output Power
VDD = 3V, RL= 4Ω, PO= 225mW VDD = 2.6V, RL= 8Ω
Figure 8. Figure 9.
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20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
20 100 1k 10k 100k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
FREQUENCY (Hz)
10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
20 Hz
1 kHz
20 kHz
10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
20 Hz
1 kHz
20 kHz
10m 100m 1
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
20 Hz
1 kHz
20 kHz
10m 100m 1 2
0.001
0.01
0.1
1
10
THD+N (%)
OUTPUT POWER (W)
20 kHz
1 kHz
20 Hz
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Typical Performance Characteristics (continued)
THD+N THD+N
vs vs
Output Power Output Power
VDD = 2.6V, RL= 4ΩVDD = 5V, RL= 8Ω
Figure 10. Figure 11.
THD+N THD+N
vs vs
Output Power Output Power
VDD = 3V, RL= 8ΩVDD = 3V, RL= 4Ω
Figure 12. Figure 13.
PSRR PSRR
vs vs
Frequency Frequency
VDD = 5V, RL= 8Ω, Input terminated VDD = 3V, RL= 8Ω, Input terminated
Figure 14. Figure 15.
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0 1 2 4 5
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
DC COMMON-MODE VOLTAGE (V)
3
0 0.2 0.4
0
0.05
0.1
0.2
0.35
0.4
POWER DISSIPATION (W)
OUTPUT POWER (W)
0.1 0.3
0.3
0.25
0.15 RL = 8:
RL = 4:
20 100 1k 10k 20k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
CMRR (dB)
FREQUENCY (Hz)
0 1 2 4 5
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
PSRR (dB)
DC COMMON-MODE VOLTAGE (V)
T
3
2.4 3 3.5 4 5.5
0
200m
400m
600m
800m
1
1.2
1.4
1.6
1.8
2
OUTPUT POWER (W)
SUPPLY VOLTAGE (V)
4.5 5
10% THD+N
1% THD+N
20 100 1k 10k 20k
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
CMRR (dB)
FREQUENCY (Hz)
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Typical Performance Characteristics (continued)
Output Power CMRR
vs vs
Supply Voltage Frequency
RL= 8ΩVDD = 5V, RL= 8Ω
Figure 16. Figure 17.
CMRR PSRR
vs vs
Frequency Common Mode Voltage
VDD = 3V, RL= 8ΩVDD = 3V, RL= 8Ω, f = 217Hz
Figure 18. Figure 19.
PSRR Power Dissipation
vs vs
Common Mode Voltage Output Power
VDD = 5V, RL= 8Ω, f = 217Hz VDD = 2.6V, RL= 8Ωand 4Ω
Figure 20. Figure 21.
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20 100 1k 10k 20k
100n
1P
10P
100P
OUTPUT NOISE VOLTAGE (V)
FREQUENCY (Hz)
Vo1 + Vo2
Shutdown On
1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
0
0.1
0.2
0.3
0.5
0.6
0.7
0.8
DROPOUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
0.4
RL = 4: Top
RL = 4: Bottom
RL = 8: Top
RL = 8: Bottom
20 100 1k 10k 20k
100n
1P
10P
100P
OUTPUT NOISE VOLTAGE (V)
FREQUENCY (Hz)
Vo1 + Vo2
Shutdown On
020 40 60 80 100 120 140 160
AMBIENT TEMPERATURE (oC)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
POWER DISSIPATION (W)
0 0.4 0.8 1.2 1.4
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
POWER DISSIPATION (W)
OUTPUT POWER (W)
0.2 0.6 1
0 0.2 0.4 0.5
0
0.05
0.1
0.15
0.2
0.25
POWER DISSIPATION (W)
OUTPUT POWER (W)
0.1 0.3
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Typical Performance Characteristics (continued)
Power Dissipation Power Dissipation
vs vs
Output Power Output Power
VDD = 5V, RL= 8ΩVDD = 3V, RL= 8Ω
Figure 22. Figure 23.
Noise Floor
Power Derating Curve VDD = 5V
Figure 24. Figure 25.
Clipping Voltage
Noise Floor vs
VDD = 3V Supply Voltage
Figure 26. Figure 27.
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4 12 20 28 32
0
0.2
0.4
0.6
0.8
1.0
1.6
OUTPUT POWER (W)
LOAD RESISTANCE (:)
1.2
8
1.4
16 24
5V, 1% THD+N
5V, 10% THD+N
3V, 1% THD+N
3V, 10% THD+N
2.6V, 1% THD+N
2.6V, 10% THD+N
0 0.5 1 1.5 2 2.5
-1
0
1
2
3
4
5
SUPPLY CURRENT (mA)
SHUTDOWN VOLTAGE (V)
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Typical Performance Characteristics (continued)
Output Power
vs
Load Resistance Supply Current Shutdown Voltage
Figure 28. Figure 29.
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APPLICATION INFORMATION
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM4923 is a fully differential audio amplifier that features differential input and output stages. Internally this is
accomplished by two circuits: a differential amplifier and a common mode feedback amplifier that adjusts the
output voltages so that the average value remains VDD / 2. When setting the differential gain, the amplifier can be
considered to have "halves". Each half uses an input and feedback resistor (Ri1 and RF1) to set its respective
closed-loop gain (see Figure 1). With Ri1 = Ri2 and RF1 = RF2, the gain is set at -RF/ Rifor each half. This results
in a differential gain of
AVD = -RF/Ri(1)
It is extremely important to match the input resistors to each other, as well as the feedback resistors to each
other for best amplifier performance. See the Proper Selection of External Components section for more
information. A differential amplifier works in a manner where the difference between the two input signals is
amplified. In most applications, this would require input signals that are 180° out of phase with each other. The
LM4923 can be used, however, as a single ended input amplifier while still retaining its fully differential benefits.
In fact, completely unrelated signals may be placed on the input pins. The LM4923 simply amplifies the
difference between them.
All of these applications provide what is known as a "bridged mode" output (bridge-tied-load, BTL). This results in
output signals at Vo1 and Vo2 that are 180° out of phase with respect to each other. Bridged mode operation is
different from the single-ended amplifier configuration that connects the load between the amplifier output and
ground. A bridged amplifier design has distinct advantages over the single-ended configuration: it provides
differential drive to the load, thus doubling maximum possible output swing for a specific supply voltage. Four
times the output power is possible compared with a single-ended amplifier under the same conditions. This
increase in attainable output power assumes that the amplifier is not current limited or clipped. In order to choose
an amplifier's closed-loop gain without causing excess clipping, please refer to the Audio Power Amplifier Design
section.
A bridged configuration, such as the one used in the LM4923, also creates a second advantage over single-
ended amplifiers. Since the differential outputs, Vo1 and Vo2, are biased at half-supply, no net DC voltage exists
across the load. This assumes that the input resistor pair and the feedback resistor pair are properly matched
(see PROPER SELECTION OF EXTERNAL COMPONENTS). BTL configuration eliminates the output coupling
capacitor required in single-supply, single-ended amplifier configurations. If an output coupling capacitor is not
used in a single-ended output configuration, the half-supply bias across the load would result in both increased
internal IC power dissipation as well as permanent loudspeaker damage. Further advantages of bridged mode
operation specific to fully differential amplifiers like the LM4923 include increased power supply rejection ratio,
common-mode noise reduction, and click and pop reduction.
EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATIONS
The LM4923's exposed-DAP (die attach paddle) package (WQFN) provide a low thermal resistance between the
die and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper traces, ground plane and, finally, surrounding air. Failing to optimize thermal design
may compromise the LM4923's high power performance and activate unwanted, though necessary, thermal
shutdown protection. The WQFN package must have its DAP soldered to a copper pad on the PCB. The DAP's
PCB copper pad is connected to a large plane of continuous unbroken copper. This plane forms a thermal mass
and heat sink and radiation area. Place the heat sink area on either outside plane in the case of a two-sided
PCB, or on an inner layer of a board with more than two layers. Connect the DAP copper pad to the inner layer
or backside copper heat sink area with a thermal via. The via diameter should be 0.012in - 0.013in. Ensure
efficient thermal conductivity by plating-through and solder-filling the vias.
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Best thermal performance is achieved with the largest practical copper heat sink area. In all circumstances and
conditions, the junction temperature must be held below 150°C to prevent activating the LM4923's thermal
shutdown protection. Figure 24 in the Typical Performance Characteristics shows the maximum power
dissipation versus temperature. Example PCB layouts are shown in the Demonstration Board Layout section.
Further detailed and specific information concerning PCB layout, fabrication, and mounting an WQFN package is
available from Texas Instruments's package Engineering Group under application note AN1187.
PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 4ΩLOADS
Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load
impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and
wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes
a voltage drop, which results in power dissipated in the trace and not in the load as desired. This problem of
decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load
dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide
as possible.
Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output
voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output
signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the
same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps
maintain full output voltage swing.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifer, whether the amplifier is bridged or
single-ended. Equation 2 states the maximum power dissipation point for a single-ended amplifier operating at a
given supply voltage and driving a specified output load.
PDMAX = (VDD)2/ (2π2RL) Single-Ended (2)
However, a direct consequence of the increased power delivered to the load by a bridge amplifier is an increase
in internal power dissipation versus a single-ended amplifier operating at the same conditions.
PDMAX = 4 * (VDD)2/ (2π2RL) Bridge Mode (3)
Since the LM4923 has bridged outputs, the maximum internal power dissipation is 4 times that of a single-ended
amplifier. Even with this substantial increase in power dissipation, the LM4923 does not require additional
heatsinking under most operating conditions and output loading. From Equation 3, assuming a 5V power supply
and an 8Ωload, the maximum power dissipation point is 625mW. The maximum power dissipation point obtained
from Equation 3 must not be greater than the power dissipation results from Equation 4:
PDMAX = (TJMAX - TA) / θJA (4)
The LM4923's θJA in an NGP0008A package is 140°C/W. Depending on the ambient temperature, TA, of the
system surroundings, Equation 4 can be used to find the maximum internal power dissipation supported by the
IC packaging. If the result of Equation 3 is greater than that of Equation 4, then either the supply voltage must be
decreased, the load impedance increased, the ambient temperature reduced, or the θJA reduced with
heatsinking. In many cases, larger traces near the output, VDD, and GND pins can be used to lower the θJA. The
larger areas of copper provide a form of heatsinking allowing higher power dissipation. For the typical application
of a 5V power supply, with an 8Ωload, the maximum ambient temperature possible without violating the
maximum junction temperature is approximately 62°C provided that device operation is around the maximum
power dissipation point. Recall that internal power dissipation is a function of output power. If typical operation is
not around the maximum power dissipation point, the LM4923 can operate at higher ambient temperatures.
Refer to the Typical Performance Characteristics curves for power dissipation information.
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POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection ratio (PSRR). The capacitor location on both the bypass and power supply pins should be as close to
the device as possible. A larger half-supply bypass capacitor improves PSRR because it increases half-supply
stability. Typical applications employ a 5V regulator with 10µF and 0.1µF bypass capacitors that increase supply
stability. This, however, does not eliminate the need for bypassing the supply nodes of the LM4923. The LM4923
will operate without the bypass capacitor CB, although the PSRR may decrease. A 1µF capacitor is
recommended for CB. This value maximizes PSRR performance. Lesser values may be used, but PSRR
decreases at frequencies below 1kHz. The issue of CBselection is thus dependant upon desired PSRR and click
and pop performance as explained in the section Proper Selection of External Components.
SHUTDOWN FUNCTION
In order to reduce power consumption while not in use, the LM4923 contains shutdown circuitry that is used to
turn off the amplifier's bias circuitry. The device may then be placed into shutdown mode by toggling the
Shutdown Select pin to logic low. The trigger point for shutdown is shown as a typical value in the Supply
Current vs Shutdown Voltage graphs in the Typical Performance Characteristics section. It is best to switch
between ground and supply for maximum performance. While the device may be disabled with shutdown
voltages in between ground and supply, the idle current may be greater than the typical value of 0.1µA. In either
case, the shutdown pin should be tied to a definite voltage to avoid unwanted state changes.
In many applications, a microcontroller or microprocessor output is used to control the shutdown circuitry, which
provides a quick, smooth transition to shutdown. Another solution is to use a single-throw switch in conjunction
with an external pull-up resistor. This scheme ensures that the shutdown pin will not float, thus preventing
unwanted state changes.
PROPER SELECTION OF EXTERNAL COMPONENTS
Proper selection of external components in applications using integrated power amplifiers is critical when
optimizing device and system performance. Although the LM4923 is tolerant to a variety of external component
combinations, consideration of component values must be made when maximizing overall system quality.
The LM4923 is unity-gain stable, giving the designer maximum system flexibility. The LM4923 should be used in
low closed-loop gain configurations to minimize THD+N values and maximize signal to noise ratio. Low gain
configurations require large input signals to obtain a given output power. Input signals equal to or greater than
1Vrms are available from sources such as audio codecs. Please refer to the AUDIO POWER AMPLIFIER
DESIGN section for a more complete explanation of proper gain selection. When used in its typical application as
a fully differential power amplifier the LM4923 does not require input coupling capacitors for input sources with
DC common-mode voltages of less than VDD. Exact allowable input common-mode voltage levels are actually a
function of VDD, Ri, and Rfand may be determined by Equation 5:
VCMi < (VDD-1.2)*((Rf+(Ri)/(Rf)-VDD*(Ri/ 2Rf) (5)
-RF/ RI= AVD (6)
Special care must be taken to match the values of the feedback resistors (RF1 and RF2) to each other as well as
matching the input resistors (Ri1 and Ri2) to each other (see Figure 1) more in front. Because of the balanced
nature of differential amplifiers, resistor matching differences can result in net DC currents across the load. This
DC current can increase power consumption, internal IC power dissipation, reduce PSRR, and possibly
damaging the loudspeaker. The chart below demonstrates this problem by showing the effects of differing values
between the feedback resistors while assuming that the input resistors are perfectly matched. The results below
apply to the application circuit shown in Figure 1, and assumes that VDD = 5V, RL= 8Ω, and the system has DC
coupled inputs tied to ground.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM4923 LM4923LQBD
LM4923, LM4923LQBD
SNAS211E –JULY 2004–REVISED MAY 2013
www.ti.com
Tolerance RF1 RF2 V02 - V01 ILOAD
20% 0.8R 1.2R -0.500V 62.5mA
10% 0.9R 1.1R -0.250V 31.25mA
5% 0.95R 1.05R -0.125V 15.63mA
1% 0.99R 1.01R -0.025V 3.125mA
0% R R 0 0
Similar results would occur if the input resistors were not carefully matched. Adding input coupling capacitors in
between the signal source and the input resistors will eliminate this problem, however, to achieve best
performance with minimum component count it is highly recommended that both the feedback and input resistors
matched to 1% tolerance or better.
AUDIO POWER AMPLIFIER DESIGN
Design a 1W/8ΩAudio Amplifier
Given:
Power Output 1Wrms
Load Impedance 8Ω
Input Level 1Vrms
Input Impedance 20kΩ
Bandwidth 100Hz–20kHz ± 0.25dB
A designer must first determine the minimum supply rail to obtain the specified output power. The supply rail can
easily be found by extrapolating from the Output Power vs Supply Voltage graphs in the Typical Performance
Characteristics section. A second way to determine the minimum supply rail is to calculate the required VOPEAK
using Equation 7 and add the dropout voltages. Using this method, the minimum supply voltage is (Vopeak +
(VDO TOP + (VDO BOT )), where VDO BOT and VDO TOP are extrapolated from the Dropout Voltage vs Supply Voltage
curve in the Typical Performance Characteristics section.
(7)
Using the Output Power vs Supply Voltage graph for an 8Ωload, the minimum supply rail just about 5V. Extra
supply voltage creates headroom that allows the LM4923 to reproduce peaks in excess of 1W without producing
audible distortion. At this time, the designer must make sure that the power supply choice along with the output
impedance does not violate the conditions explained in the Power Dissipation section. Once the power
dissipation equations have been addressed, the required differential gain can be determined from Equation 8.
(8)
Rf/ Ri= AVD (9)
From Equation 8, the minimum AVD is 2.83. Since the desired input impedance was 20kΩ, a ratio of 2.83:1 of Rf
to Riresults in an allocation of Ri= 20kΩfor both input resistors and Rf= 60kΩfor both feedback resistors. The
final design step is to address the bandwidth requirement which must be stated as a single -3dB frequency point.
Five times away from a -3dB point is 0.17dB down from passband response which is better than the required
±0.25dB specified.
fH= 20kHz * 5 = 100kHz (10)
The high frequency pole is determined by the product of the desired frequency pole, fH, and the differential gain,
AVD . With a AVD = 2.83 and fH= 100kHz, the resulting GBWP = 150kHz which is much smaller than the LM4923
GBWP of 10MHz. This figure displays that if a designer has a need to design an amplifier with a higher
differential gain, the LM4923 can still be used without running into bandwidth limitations.
14 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LM4923 LM4923LQBD
LM4923, LM4923LQBD
www.ti.com
SNAS211E –JULY 2004–REVISED MAY 2013
Revision History
Rev Date Description
1.0 09/28/07 Added the VSSOP package, then released.
1.01 12/17/07 Updated the mktg outline NGP0008A into the rev B.
1.02 02/19/09 Fixed typo labels on the typical circuit diagram.
E 05/03/13 Changed layout of National Data Sheet to TI format.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM4923 LM4923LQBD
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4923LQ/NOPB ACTIVE WQFN NGP 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 GB2
LM4923LQX/NOPB ACTIVE WQFN NGP 8 4500 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 GB2
LM4923MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 GC8
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2014
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4923LQ/NOPB WQFN NGP 8 1000 178.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1
LM4923LQX/NOPB WQFN NGP 8 4500 330.0 12.4 2.2 2.2 1.0 8.0 12.0 Q1
LM4923MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4923LQ/NOPB WQFN NGP 8 1000 210.0 185.0 35.0
LM4923LQX/NOPB WQFN NGP 8 4500 367.0 367.0 35.0
LM4923MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
MECHANICAL DATA
NGP0008A
www.ti.com
LQB08A (Rev B)
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