1998-2013 Microchip Technology Inc. DS20001203T-page 1
24AA256/24LC256/24FC256
Device Selection Table
Features:
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms Max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, DFN,
TDFN, TSSOP and MSOP
• Pb-Free and RoHS Compliant
• Temperature Ranges:
Description:
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device also has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, TSSOP, MSOP, DFN and TDFN packages. The
24AA256 is also available in the 8-lead Chip Scale
package.
Block Diagram
Package Types
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
24AA256 1.7-5.5V 400 kHz(1) I, E
24LC256 2.5-5.5V 400 kHz I, E
24FC256 1.7-5.5V 1 MHz(2) I
Note 1: 100 kHz for VCC < 2.5V.
2: 400 kHz for VCC < 2.5V.
- Industrial (I): -40C to +85C
- Automotive (E): -40C to +125C
HV Generator
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp.
R/W Control
Memory
Control
Logic
I/O
Control
Logic
I/O
A0 A1A2
SDA
SCL
VCC
VSS
WP
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
24XX256
PDIP/SOIC TSSOP/MSOP(1)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
24XX256
DFN/TDFN
A0
A1
A2
VSS
WP
SCL
SDA
24XX256
5
6
7
8
4
3
2
1VCC
Note 1: * Pins A0 and A1 are no connects for the MSOP package only.
Note 2: Available in I-temp, “AA” only.
CS (Chip Scale)(2)
123
45
678
VCC A1 A0
WP A2
SDA SCL VSS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
256K I2C™ CMOS Serial EEPROM
24AA256/24LC256/24FC256
DS20001203T-page 2 1998-2013 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
— A0, A1, A2, SCL, SDA
and WP pins:
————
D1 VIH High-level input voltage 0.7 VCC —V—
D2 VIL Low-level input voltage — 0.3 VCC
0.2 VCC
V
V
VCC 2.5V
VCC < 2.5V
D3 VHYS Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
0.05 VCC —VVCC 2.5V (Note)
D4 VOL Low-level output voltage — 0.40 V IOL = 3.0 ma @ VCC = 4.5V
IOL = 2.1 ma @ VCC = 2.5V
D5 ILI Input leakage current — ±1 AVIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6 ILO Output leakage current — ±1 AVOUT = VSS or VCC
D7 CIN,
COUT
Pin capacitance
(all inputs/outputs)
—10pFVCC = 5.0V (Note)
T
A = 25°C, FCLK = 1 MHz
D8 ICC Read Operating current — 400 AVCC = 5.5V, SCL = 400 kHz
ICC Write — 3 mA VCC = 5.5V
D9 ICCS Standby current — 1 ATA = -40°C to +85°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
—5ATA = -40°C to +125°C
SCL = SDA = VCC = 5.5V
A0, A1, A2, WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
1998-2013 Microchip Technology Inc. DS20001203T-page 3
24AA256/24LC256/24FC256
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—
—
—
100
400
400
1000
kHz 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
2THIGH Clock high time 4000
600
600
500
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
3T
LOW Clock low time 4700
1300
1300
500
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
4TRSDA and SCL rise time
(Note 1)
—
—
—
1000
300
300
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC256
5TFSDA and SCL fall time
(Note 1)
—
—
300
100
ns All except, 24FC256
1.7V VCC 5.5V 24FC256
6T
HD:STA Start condition hold time 4000
600
600
250
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
7TSU:STA Start condition setup time 4700
600
600
250
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
8THD:DAT Data input hold time 0 — ns (Note 2)
9T
SU:DAT Data input setup time 250
100
100
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC256
10 TSU:STO Stop condition setup time 4000
600
600
250
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
11 TSU:WP WP setup time 4000
600
600
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC256
12 THD:WP WP hold time 4700
1300
1300
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 5.5V 24FC256
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
24AA256/24LC256/24FC256
DS20001203T-page 4 1998-2013 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DATA
13 TAA Output valid from clock
(Note 2)
—
—
—
—
3500
900
900
400
ns 1.7 V VCC 2.5V
2.5 V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5 V VCC 5.5V 24FC256
14 TBUF Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
1300
500
—
—
—
—
ns 1.7V VCC 2.5V
2.5V VCC 5.5V
1.7V VCC 2.5V 24FC256
2.5V VCC 5.5V 24FC256
15 TOF Output fall time from VIH
minimum to VIL maximum
CB 100 pF
10 + 0.1CB 250
250
ns All except, 24FC256 (Note 1)
16 TSP Input filter spike suppression
(SDA and SCL pins)
— 50 ns All except, 24FC256 (Notes 1
and 3)
17 TWC Write cycle time (byte or
page)
—5ms—
18 — Endurance 1,000,000 — cycles Page mode, 25°C, 5.5V (Note 4)
AC CHARACTERISTICS (Continued)
Electrical Characteristics:
Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to +125°C
Param.
No. Sym. Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
16
3
2
89
13
D3 4
10
11 12
14
1998-2013 Microchip Technology Inc. DS20001203T-page 5
24AA256/24LC256/24FC256
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2 - 1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400kHz and 1MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX256 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name 8-pin
PDIP
8-pin
SOIC
8-pin
TSSOP
8-pin
MSOP
8-pin
DFN/TDFN CS Function
A0 1 1 1 — 1 3 User Configurable Chip Select
A1 2 2 2 — 2 2 User Configurable Chip Select
(NC) — — — 1, 2 — — Not Connected
A2 3 3 3 3 3 5 User Configurable Chip Select
VSS 4 4 4 4 4 8 Ground
SDA 5 5 5 5 5 6 Serial Data
SCL 6 6 6 6 6 7 Serial Clock
(NC) — — — — — — Not Connected
WP 7 7 7 7 7 4 Write-Protect Input
VCC 8 8 8 8 8 1 +1.7V to 5.5V (24AA256)
+2.5V to 5.5V (24LC256)
+1.7V to 5.5V (24FC256)
Note: Exposed pad on DFN/TDFN can be connected to VSS or left floating.
24AA256/24LC256/24FC256
DS20001203T-page 6 1998-2013 Microchip Technology Inc.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
Note: The 24XX256 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
1998-2013 Microchip Technology Inc. DS20001203T-page 7
24AA256/24LC256/24FC256
FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
FIGURE 4-2: ACKNOWLEDGE TIMING
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
Start
Condition
SCL
SDA
(A) (B) (D) (D) (C) (A)
SCL 987654321 123
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
Data from transmitter
24AA256/24LC256/24FC256
DS20001203T-page 8 1998-2013 Microchip Technology Inc.
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
24XX256, this is set as ‘1010’ binary for read and
write operations. The next three bits of the control byte
are the Chip Select bits (A2, A1, A0). The Chip Select
bits allow the use of up to eight 24XX256 devices on
the same bus and are used to select which device is
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set to
‘0’. Only two 24XX256 MSOP packages can be
connected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A14…A0 are used, the upper address bits are a
“don’t care.” The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX256 will select a read
or write operation.
FIGURE 5-1: CONTROL BYTE
FORMAT
5.1 Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24XX256 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A15; A1 as address bit A16; and A2
as address bit A17. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX256 devices
can be added for up to 512 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A17. Bits A0 (A15) and A1 (A16) of the
control byte must always be set to a logic ‘0’ for the
MSOP.
FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS
1010A2 A1 A0
SACKR/W
Control Code
Chip Select
Bits
Slave Address
Acknowledge Bit
Start Bit
Read/Write Bit
1 010A
2A
1A
0R/W xA
11 A
10 A
9A
7A
0
A
8••••••
A
12
Control Byte Address High Byte Address Low Byte
Control
Code
Chip
Select
Bits
x = “don’t care” bit
A
13
A
14
1998-2013 Microchip Technology Inc. DS20001203T-page 9
24AA256/24LC256/24FC256
6.0 WRITE OPERATIONS
6.1 Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX256. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX256, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX256 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX256 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX256 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower Address
Pointer bits are internally incremented by one. If the
master should transmit more than 64 bytes prior to
generating the Stop condition, the address counter will
roll over and the previously received data will be over-
written. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command, but no write cycle will occur, no data will
be written and the device will immediately accept a new
command.
6.3 Write Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every Write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
Note: When doing a write of less than 64 bytes
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Note: Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of [page size – 1]. If
a Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
24AA256/24LC256/24FC256
DS20001203T-page 10 1998-2013 Microchip Technology Inc.
FIGURE 6-1: BYTE WRITE
FIGURE 6-2: PAGE WRITE
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
x
Bus Activity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte Data Byte 0
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte 63
A
C
K
x = “don’t care” bit
S1010 0
A
2A
1A
0P
1998-2013 Microchip Technology Inc. DS20001203T-page 11
24AA256/24LC256/24FC256
7.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram.
FIGURE 7-1: ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
NO
YES
24AA256/24LC256/24FC256
DS20001203T-page 12 1998-2013 Microchip Technology Inc.
8.0 READ OPERATION
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1 Current Address Read
The 24XX256 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous read
access was to address ‘n’ (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX256 issues an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1: CURRENT ADDRESS
READ
8.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX256 as part of a write operation (R/W bit set to
‘0’). Once the word address is sent, the master gener-
ates a Start condition following the acknowledge. This
terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24XX256 will then issue an acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24XX256 to discon-
tinue transmission (Figure 8-2). After a random Read
command, the internal address counter will point to the
address location following the one that was just read.
8.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX256 transmits
the first data byte, the master issues an acknowledge
as opposed to the Stop condition used in a random
read. This acknowledge directs the 24XX256 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an acknowledge,
but will generate a Stop condition. To provide sequen-
tial reads, the 24XX256 contains an internal Address
Pointer which is incremented by one at the completion
of each operation. This Address Pointer allows the
entire memory contents to be serially read during one
operation. The internal Address Pointer will
automatically roll over from address 7FFF to address
0000 if the master acknowledges the byte received
from the array address 7FFF.
FIGURE 8-2: RANDOM READ
Bus Activity
Master
SDA Line
Bus Activity
PS
S
T
O
P
Control
Byte
S
T
A
R
T
Data
A
C
K
N
O
A
C
K
1100
AAA1
Byte
210
x
Bus Activity
Master
SDA Line
Bus Activity
A
C
K
N
O
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
S
T
A
R
T
Control
Byte
Address
High Byte
Address
Low Byte
Control
Byte
Data
Byte
S
T
A
R
T
x = “don’t care” bit
S1010AAA0
210 S1010AAA
1
210 P
1998-2013 Microchip Technology Inc. DS20001203T-page 13
24AA256/24LC256/24FC256
FIGURE 8-3: SEQUENTIAL READ
Bus Activity
Master
SDA Line
Bus Activity
Control
Byte Data (n) Data (n + 1) Data (n + 2) Data (n + x)
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
24AA256/24LC256/24FC256
DS20001203T-page 14 1998-2013 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead SOIC (208 mil) Example:
24LC256
0510017
I/SM
24AA256
I/P 017
0510
XXXXXXXX
YYWWNNN
T/XXXXXX
24LC256I
SN 0510
017
3
e
3
e
3
e
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
*Standard device marking consists of Microchip part number, year code, week code, and traceability code. For
device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
1998-2013 Microchip Technology Inc. DS20001203T-page 15
24AA256/24LC256/24FC256
Package Marking Information (Continued)
8-Lead MSOP Example:
XXXXXT
YWWNNN
4L256I
510017
8-Lead DFN-S Example:
XXXXXXX
T/XXXXX
YYWW
24LC256
I/MF
0510
017
NNN
First Line Marking Codes
Part No. TSSOP Package Codes MSOP Package Codes TDFN Package Codes
24AA256 4AD 4A256T —
24LC256 4LD 4L256T EF4
24FC256 4FD 4F256T —
8-Lead TSSOP Example:
XXXX
TYWW
NNN
4LD
I510
017
3
e
8-Lead Chip Scale
XXX
XYYW
Example:
249
0017
WNNN
A051
8-Lead TDFN Example:
XXX
YWW
EF4
0510
017
NN
24AA256/24LC256/24FC256
DS20001203T-page 16 1998-2013 Microchip Technology Inc.
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
1998-2013 Microchip Technology Inc. DS20001203T-page 17
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 18 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 19
24AA256/24LC256/24FC256
! ""#$%& !'
24AA256/24LC256/24FC256
DS20001203T-page 20 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 21
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 22 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 23
24AA256/24LC256/24FC256
() )"* ! (+%+( !
D
N
E
E1
NOTE 1
12
b
e
c
A
A1
A2
L1 L
φ
24AA256/24LC256/24FC256
DS20001203T-page 24 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 25
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 26 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 27
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 28 1998-2013 Microchip Technology Inc.
,$*-.,/01,
NOTE 2
A1
A
A3
NOTE 1 12
E
N
D
EXPOSED PAD
NOTE 1
21
E2
L
N
e
b
K
BOTTOM VIEW
TOP VIEW
D2
1998-2013 Microchip Technology Inc. DS20001203T-page 29
24AA256/24LC256/24FC256
24AA256/24LC256/24FC256
DS20001203T-page 30 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 31
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 32 1998-2013 Microchip Technology Inc.
,$*-.200%31(,
1998-2013 Microchip Technology Inc. DS20001203T-page 33
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 34 1998-2013 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1998-2013 Microchip Technology Inc. DS20001203T-page 35
24AA256/24LC256/24FC256
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
24AA256/24LC256/24FC256
DS20001203T-page 36 1998-2013 Microchip Technology Inc.
APPENDIX A: REVISION HISTORY
Revision L
Corrections to Section 1.0, Electrical Characteristics.
Revision M
Added 1.8V 400 kHz option for 24FC256.
Revision N
Revised Sections 2.1 and 2.4. Removed 14-Lead
TSSOP Package.
Revision P
Revised Features; Changed 1.8V voltage to 1.7V;
Replaced Package Drawings; Revised markings (8-lead
SOIC); Revised Product ID System.
Revision Q (05/10)
Revised Table 1-1, Table 1-2, Section 6.1; Updated
Package Drawings.
Revision R (07/2011)
Added Chip Scale package.
Revision S (12/2012)
Revise Automotive E temp.
Revision T (04/2013)
Added TDFN Package.
1998-2013 Microchip Technology Inc. D20001203T-page 37
24AA256/24LC256/24FC256
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
24AA256/24LC256/24FC256
D20001203T-page 38 1998-2013 Microchip Technology Inc.
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO: Technical Publications Manager
RE: Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
D20001203T24AA256/24LC256/24FC256
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
1998-2013 Microchip Technology Inc. DS20001203T-page 39
24AA256/24LC256/24FC256
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA256: 256 Kbit 1.7V I2C Serial
EEPROM
24AA256T: 256 Kbit 1.7V I2C Serial
EEPROM Tape and Reel)
24LC256: 256 Kbit 2.5V I2C Serial
EEPROM
24LC256T: 256 Kbit 2.5V I2C Serial
EEPROM Tape and Reel)
24FC256: 256 Kbit High Speed I2C Serial
EEPROM
24FC256T: 256 Kbit High Speed I2C Serial
EEPROM Tape and Reel)
Temperature
Range:
I= -40C to +85C
E= -40C to +125C
Package: P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (3.90 mm body), 8-lead
SM = Plastic SOIJ (5.28 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm), 8-lead
MF = Dual, Flat, No Lead (DFN)(6x5 mm
body), 8-lead
MS = Plastic Micro Small Outline (MSOP),
8-lead
MNY(2)=Dual, Flat, No Lead (TDFN) (2x3 mm
body), 8-lead
CS16K(1) = Chip Scale (CS), 8-lead (I-temp,
“AA”, Tape and Reel only)
Examples:
a) 24AA256-I/P: Industrial Temp.,
1.7V, PDIP package.
b) 24AA256T-I/SN: Tape and Reel,
Industrial Temp., 1.7V, SOIC
package.
c) 24AA256-I/ST: Industrial Temp.,
1.7V, TSSOP package.
d) 24AA256-I/MS: Industrial Temp.,
1.7V, MSOP package.
e) 24LC256-E/P: Extended Temp.,
2.5V, PDIP package.
f) 24LC256-I/SN: Industrial Temp.,
2.5V, SOIC package.
g) 24LC256T-I/SN: Tape and Reel,
Industrial Temp., 2.5V, SOIC
package.
h) 24LC256-I/MS: Industrial Temp,
2.5V, MSOP package.
i) 24FC256-I/P: Industrial Temp,
1.7V, High Speed, PDIP package.
j) 24FC256-I/SN: Industrial Temp,
1.7V, High Speed, SOIC package.
k) 24FC256T-I/SN: Tape and Reel,
Industrial Temp, 1.7V, High Speed,
SOIC package.
l) 24AA256T-CS16K: Industrial Temp,
1.7V, CS package, Tape and Reel.
m) 24AA256T-E/SN: Tape and Reel,
Extended Temp., 1.7V, SOIC
package.
Note 1: “16K” indicates 160K technology.
2: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
24AA256/24LC256/24FC256
DS20001203T-page 40 1998-2013 Microchip Technology Inc.
NOTES:
1998-2013 Microchip Technology Inc. DS20001203T-page 41
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1998-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620771426
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20001203T-page 42 1998-2013 Microchip Technology Inc.
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