©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
H UFA75332G 3, HUFA75332P3, HUFA 75332S3S
60A, 55V, 0.019 Ohm, N-Channel UltraFET
Power MOSFETs
These N-Chann el power MOSFETs
are manufactured using the
innovative Ul tra FET® proce ss . This
advanced process technology
achie ves the lo west pos sible on-resi stance per sil icon area,
resultin g in outstanding performanc e. This dev ice is capable
of wit hstanding hi gh energ y in the avalanche mode and the
diode e xhibits v ery lo w reverse recov ery time and stored
charge. It w as designed for use in applica ti ons where po wer
efficiency is important, such as switching regulators,
switching converters , motor driv ers, relay drivers, low-
voltage bus s w itches, and power management in portab le
and bat ter y-operated products.
Formerly developmenta l ty pe TA75 332.
Features
• 60A, 55V
• Simulation Models
- Temper ature Compe nsa ted PSPI CE® a nd SABER™
Models
- SPICE and SABER Thermal Impedance Models
Availa ble on the WEB at: www.fairchi ldsemi.co m
• Peak Current vs Pulse Widt h Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Solder ing Surface Mount
Components to PC Boards”
Symbol
Packaging
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a
copy of the requir em ent s, se e AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.
All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
Ordering Information
PART NUMBER PACKAGE BRAND
HUFA75332G3 TO-247 75332G
HUFA75332P3 TO-220AB 75332P
HUFA75332S3S TO-263AB 75332S
NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-263AB v ariant in tape and reel, e.g., HUFA75332S3ST.
D
G
S
JEDEC STYLE TO-247 JEDEC TO-220AB
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(TAB)
DRAIN
SOURCE
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
Data S heet June 2002
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
Absolute Maximum Rat ings TC = 25oC, Unless Otherwise Specif ied UNITS
Drain to Source V o ltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . VDSS 55 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . VDGR 55 V
Gate to Source Vo ltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 60
Figu re 4 A
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figur e 6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
0.97 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 175 oC
Maximu m Temperature for S oldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . .TL
Package Body f or 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUT ION: St ress es above those list ed in “Abs olute Maximum Rati ngs” may cause per mane nt damage to the device. This is a str ess only rating and operati on of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Speci fications TC = 25oC, Unless Othe rwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Dr ain t o Sou rce Breakdown Voltag e BVDSS ID = 250µA, VGS = 0V (Figure 11) 55 - - V
Z ero Gat e V ol tag e D rain C urr e nt IDSS VDS = 5 0 V, VGS = 0V - - 1 µA
VDS = 45V, VGS = 0V, TC = 1 50oC--250µA
Ga te t o Sour c e Le ak ag e C urr e nt IGSS VGS = ±20V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Drain t o Source On Resistance rDS(ON) ID = 60A, VGS = 10V (Figure 9) - 0.016 0.019 Ω
THERMAL SPECIFICATIONS
T her m al Res ista nc e Ju ncti on to Case RθJC (Figure 3) - - 1.03 oC/W
Thermal Resistance Junction to Ambient RθJA TO-247 - - 30 oC/W
TO-220, TO-263 - - 62 oC/W
SWITCHING SPECIFICATIONS (VGS = 10V )
Turn -On Time tON VDD = 30V, ID ≅ 60A,
RL = 0.50Ω, VGS = 10V,
RGS = 6.8Ω
--100ns
Turn-O n Delay Time td(ON) -12- ns
Rise Time tr-55- ns
Turn-O ff Delay Time td(OFF) -11- ns
Fa ll Time tf-25- ns
Turn -Off Time tOFF - - 55 ns
GATE CHARGE SPECIFICATIONS
T otal G ate Charg e Qg(TOT) VGS = 0V to 20V VDD = 30V,
ID ≅ 60A,
RL = 0.5 0Ω
Ig(REF) = 1.0 m A
(Figure 13)
-7085nC
Gat e Charge at 10 V Qg(10) VGS = 0V to 10 V - 40 50 nC
T hresh old G ate Ch arge Qg(TH) VGS = 0V to 2V - 2.5 3.0 nC
Ga te to Sourc e Gate Charg e Qgs -6-nC
Reverse Transfer Capacitance Qgd -15-nC
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 2 5V, VGS = 0V ,
f = 1MHz
(Figure 12)
-1300- pF
Output Capacitance COSS -480- pF
Reverse Transfer Capacitance CRSS -115- pF
Electrical Speci fications TC = 25oC, Unless Othe rwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specific ations
PARAMETER SY MBOL TE ST CON DITIONS MIN TY P MAX UNITS
Source to Drain Diode Volta ge VSD ISD = 60A - - 1.25 V
Reverse Recovery Time trr ISD = 60A, dISD/dt = 100A/µs--75ns
Reverse Recovered Charge QRR ISD = 60A, dISD/dt = 100A/µs - - 140 nC
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPATI ON vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPER ATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 175
I
D
, DRAIN CURRENT (A)
T
C
, CAS E TEMPERATU R E (
o
C)
20
40
60
80
50 75 100 125 150 175
025
t, RECTANGULAR PULSE DURATION (s)
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
10-4 10-3 10-2 10-1 100101
10-5
0.1
1
2
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
FIGURE 4. PEAK CURRENT CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATI NG AREA NOTE: Refer to Fairchil d App lication Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARA CTERISTICS
Typical Performance Curves (Continued)
101
100
10-1
10-2
10-3
10-4
10-5
50
100
1000 TC = 25oC
I = I25 175 - TC
150
FOR TEMPERAT URES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
100
500
10 100
11200
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
T
J
= MAX RATED
T
C
= 25
o
C
100
µ
s
10ms
1ms
V
DSS(MAX)
= 55V
LIMITED BY r
DS(ON)
AREA MAY BE
OPER ATION IN THIS
STARTING TJ = 25oC
10
100
0.001 0.01 0.1 1 10
500
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
STARTING TJ = 25oC
STARTING TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
0
30
60
90
120
150
0 1.5 3.0 4.5 6.0 7.5
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
TC = 25oC
ID, DRAIN CURRENT (A)
VGS = 5V
VGS = 6V
VGS = 10V
VGS = 7V
VGS = 20V
DUTY CYCLE = 0.5% MAX
0
30
60
90
120
150
0 1.5 3.0 4.5 6.0 7.5
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 15V
175oC
-55oC
25oC
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
FIGURE 9. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED GA TE THRESHOLD V OL TA GE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN T O SOURCE BRE AKDOW N
VOLTAGE vs JUNCTION TEMPERAT URE FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild App lication Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Typical Performance Curves (Continued)
1.0
1.5
2.0
2.5
-40 0 40 80 120 160 200
0.5-80
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
PULSE DURATION = 80µs
VGS = 10V, ID = 60A
DUTY CYCLE = 0.5% MAX
0.8
1.0
1.2
-40 0 40 80 120 160 200
0.6-80
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
1.1
1.2
-40 0 40 80 120 160 200
0.9-80
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
BREAKDOWN VOLTAGE
0
500
1000
1500
2000
0 102030405060
VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS
COSS
CRSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
2
4
6
8
10
10 20 30 40 50 600
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 30V
Qg, GATE CHARGE (nC)
ID = 60A
ID = 45A
ID = 30A
ID = 15A
WAVEFORMS IN
DESCENDING ORDER:
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY W AVEFORMS
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
IG(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 1 0V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10% PULSE WIDTH
VGS
0
0
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
PSPICE Electrical Model
.SUBCKT HUFA75332 2 1 3 ; rev 18 J une 2002
C A 12 8 1. 8e- 9
CB 15 14 1.73e -9
CIN 6 8 1.19e-9
D BODY 7 5 DBODYM OD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 58.85
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH RES 6 21 19 8 1
EVTEM P 20 6 18 22 1
IT 8 1 7 1
LDRAIN 2 5 1e-9
LGATE 1 9 1e-9
LSOURC E 3 7 1e-9
K1 LS OURCE LGA T E 0.008 5
MMED 16 6 8 8 M M EDMOD
MSTR O 16 6 8 8 M S T ROMOD
MWEAK 16 21 8 8 M WE AKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 4.5e-3
RG ATE 9 20 1.3
RL DRAIN 2 5 10
RLGATE 1 9 10
RLSOURCE 3 7 10
RSLC1 5 51 R SL CM OD 1e-6
RSLC2 5 50 1e 3
R SOUR CE 8 7 RS OURC E M O D 5.95e -3
RVT HRE S 2 2 8 RVTHRESM OD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1A M OD
S1B 13 12 13 8 S1BMO D
S2A 6 15 14 13 S2AMO D
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*180),4.6))}
.MO DE L DB ODYM OD D (IS = 1.3 e-12 RS = 3.0 e-3 I KF = 20 XT I = 6 TRS 1 = 2.7e- 3 TRS2 = 7.0e-7 CJ O = 1.7e- 9 TT = 4.0e-8 M = 0. 45 vj = 0.75)
.MO DE L DB REAK M OD D (RS = 1. 71e-2 I KF = 1. 0e-5 TRS 1 = -4.0 e-4 T RS2 = -1.55e -5)
.MO DE L DP LCA P MOD D (CJO = 1.8 e-9 IS = 1e-30 N = 1 M = 0.9 vj = 1. 45)
. M ODEL MMEDMOD NM O S (V T O = 3. 183 KP = 2 IS = 1e-30 N = 10 TO X = 1 L = 1u W = 1u RG = 1.3)
.MO DEL M STROMOD NMOS (VTO = 3. 66 KP = 51.5 IS = 1e-30 N = 10 TO X = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.703 KP = 0.008 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 13)
.MO DE L RB REAK M OD RES (TC1 = 1. 05e-3 TC2 = 4.5 e-7)
.MO DE L RDRA INMOD RES (TC1 = 1.16e-2 TC 2 = 1. 7e-5)
.MO DE L RS LCM OD RES (TC1 = 3. 96e-3 TC2 = 2.7 e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-5)
.MODEL RVTHRESMOD RES (TC1 = -2.8e-3 TC2 = -1.0e-5)
.MO DEL RVT EMPMOD RES (T C1 = -2.75e-3 TC2 = 5.0e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8 VOFF= -3)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -8)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= 0)
.ENDS
NOTE: For further discussion of the PSPI CE model, cons ult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Option s; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
SABER Electrical Model
REV 18 June 20 02
templ ate hu fa7533 2 n2, n1, n3
el ectri cal n2, n1 , n3
{
var i iscl
d..model dbody m od = (i s = 1.3e-12, xti = 6, cjo = 1.7e- 9, tt = 4.0e-8, m = 0.45 , v j = 0.75 )
d..model dbreakmod = ()
d..model dplcap m od = (cjo = 1.8e -9, is = 1e- 30, m = 0.9 , vj = 1. 45)
m..model mmedmod = (type=_n, vt o = 3.183 , k p = 2, is = 1e-30, tox = 1)
m..model ms t rongmod = (ty pe=_n, vt o = 3. 66, kp = 51.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vt o = 2.703 , k p = 8.0 e-3, is = 1e-30, tox = 1)
sw_v cs p..mo del s1amod = (ron = 1e -5, roff = 0.1, vo n = -8, vof f = -3)
sw_v cs p..mo del s1bmod = (ron = 1e -5, roff = 0.1, vo n = -3, vof f = -8)
sw_v cs p..mo del s2amod = (ron = 1e -5, roff = 0.1, vo n = 0, voff = 0.5)
sw_v cs p..mo del s2bmod = (ron = 1e -5, roff = 0.1, vo n = 0.5 , v of f = 0)
c . ca n1 2 n8 = 1.8e -9
c.c b n15 n14 = 1. 73e-9
c.cin n6 n8 = 1.19 e-9
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = m odel=dbreakmod
d.dplcap n10 n5 = m odel =dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lg ate n1 n9 = 1.0e-9
l.lsource n3 n7 = 1.0e- 9
k.k l i (l.lgat e) i (l. lsourc e) = l (l. l gat e), l (l.lsource ), 0.0085
m.mmed n16 n6 n8 n8 = model=m m edmod, l = 1u, w = 1u
m.ms t rong n16 n6 n8 n8 = model=m strongmod, l = 1u, w = 1u
m.mw eak n16 n21 n8 n8 = model=m weakmod , l = 1u, w = 1u
res. rbreak n17 n18 = 1, tc1 = 1.05 e-3, tc2 = 4.5e-7
res. rdbody n71 n5 = 3.0 e-3, tc1 = 2.7e-3, tc2 = 7. 0e-7
res. rdbreak n7 2 n5 = 1. 71e-2, tc 1 = -4.0e -4, tc2 = -1.55e-5
res. rdrain n50 n16 = 4.5e-3, tc1 = 1.1 6e-2, tc 2 = 1. 7e-5
r e s .rgat e n9 n2 0 = 1. 3
res. rl drain n2 n5 = 10
res. rl gate n1 n9 = 10
res. rl sour ce n3 n7 = 10
res.rslc1 n5 n51 = 1e-6, tc1 = 3.96e-3, tc2 = 2.7e-6
res. rslc2 n5 n50 = 1e 3
res.rsource n8 n7 = 5.95e-3, tc1 = 1e-3, tc2 = 1e-5
res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 5.0e-7
res. rvth res n22 n8 = 1, tc1 = -2. 8e-3, tc 2 = -1.0 e-5
spe. ebreak n11 n7 n17 n18 = 58. 85
spe. eds n14 n8 n5 n8 = 1
spe. egs n13 n8 n6 n8 = 1
spe. esg n6 n10 n6 n8 = 1
spe. evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_v cs p.s1a n6 n12 n13 n8 = model =s1a m od
sw_v cs p.s1 b n13 n12 n13 n8 = model=s1bmod
sw_v cs p.s2 a n6 n15 n14 n13 = model=s2amod
sw_v cs p.s2 b n13 n15 n14 n13 = mod el =s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl : v (n51, n50) = ((v (n5,n51) / (1e-9+abs (v(n5,n51))))*(( abs(v (n5,n 51)*1e6/ 180))** 4. 6))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
©2002 Fairchild Semiconductor Corporation HUFA75332G3, HUFA75332P3, HUFA75332S3S Rev. A
SPICE Thermal Model
REV 18June 2002
HUFA75332
CTHERM1 th 6 4.00e-3
CTHERM2 6 5 7.00e-3
CTHERM3 5 4 7.50e-3
CTHERM4 4 3 8.00e-3
CTHERM5 3 2 1.85e-2
CTHERM6 2 tl 12.55
RTHERM1 th 6 7.09e-3
RTHERM2 6 5 1.77e-2
RTHERM3 5 4 4.97e-2
RTHERM4 4 3 2.79e-1
RTHERM5 3 2 4.21e-1
RTHERM6 2 tl 5.58e-2
SABER Thermal Mod el
SABER thermal model HUFA75332
template thermal_model th tl
thermal_c th, tl
{
c therm.ctherm1 th 6 = 4.00e-3
ctherm.ctherm2 6 5 = 7.00e-3
ctherm.ctherm3 5 4 = 7.50e-3
ctherm.ctherm4 4 3 = 8.00e-3
ctherm.ctherm5 3 2 = 1.85e-2
ctherm.ctherm6 2 tl = 12.55
rtherm.rtherm1 th 6 = 7 .09e-3
rtherm.rtherm2 6 5 = 1.77e-2
rtherm.rtherm3 5 4 = 4.97e-2
rtherm.rtherm4 4 3 = 2.79e-1
rtherm.rtherm5 3 2 = 4.21e-1
rtherm.rtherm6 2 tl = 5.58e-2
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUFA75332G3, HUFA7533 2P3 , HUFA75 332S 3S
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