DC1082A-D - Linear Technology

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

Block Diagram

Features

applications

Description

Serial 12-Bit/14-Bit, 2.8Msps

Sampling ADCs with Shutdown

The LT C

1403/LTC1403A are 12-bit/14-bit, 2.8Msps se-

rial ADCs with differential inputs. The devices draw only

4.7mA from a single 3V supply and come in a tiny 10-lead

MS package. A Sleep shutdown feature lowers power

consumption to 10µW. The combination of speed, low

power and tiny package makes the LTC1403/LTC1403A

suitable for high speed, portable applications.

The 80dB common mode rejection allows users to eliminate

ground loops and common mode noise by measuring

signals differentially from the source.

The devices convert 0V to 2.5V unipolar inputs differentially.

The absolute voltage swing for +AIN and –AIN extends from

ground to the supply voltage.

The serial interface sends out the conversion results during

the 16 clock cycles following CONV↑ for compatibility with

standard serial interfaces. If two additional clock cycles

for acquisition time are allowed after the data stream in

between conversions, the full sampling rate of 2.8Msps

can be achieved with a 50.4MHz clock.

n 2.8Msps Conversion Rate

n Low Power Dissipation: 14mW

n 3V Single Supply Operation

n –40°C to 125°C Guaranteed Operation

n 2.5V Internal Bandgap Reference can be Overdriven

n 3-Wire Serial Interface

n Sleep (10µW) Shutdown Mode

n Nap (3mW) Shutdown Mode

n 80dB Common Mode Rejection

n 0V to 2.5V Unipolar Input Range

n Tiny 10-Lead MS Package

n Automotive

n Communications

n Data Acquisition Systems

n Uninterrupted Power Supplies

n Multiphase Motor Control

n Multiplexed Data Acquisition

2nd, 3rd and SFDR vs

Input Frequency

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

LinearView and SoftSpan are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

–

S & H

GND

EXPOSED PAD

LTC1403A

VREF

10F

AIN–

AIN+

14-BIT ADC

3V10µF

14-BIT LATCH

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

VDD

SDO

CONV

SCK

1403A TA01

5 6 11

FREQUENCY (MHz)

0.1

–80

THD, 2nd, SFDR, 3rd (dB)

–74

–68

–62

–56

1 10 100

1403A TA02

–86

–92

–98

–104

–50

–44

THD

3rd

2nd, SFDR

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

pin conFigurationaBsolute maximum ratings

Supply Voltage (VDD) ..................................................4V

Analog Input Voltage

(Note 3) ................................... –0.3V to (VDD + 0.3V)

Digital Input Voltage..................... –0.3V to (VDD + 0.3V)

Digital Output Voltage .................. –0.3V to (VDD + 0.3V)

Power Dissipation ...............................................100mW

Operation Temperature Range

LTC1403C/LTC1403AC ............................. 0°C to 70°C

LTC1403I/LTC1403AI ........................... –40°C to 85°C

LTC1403H/LTC1403AH ...................... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

(Note 1, 2,)

orDer inFormation

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1403CMSE#PBF LTC1403CMSE#TRPBF LTBDN 10-Lead Plastic MSOP 0°C to 70°C

LTC1403IMSE#PBF LTC1403IMSE#TRPBF LTBDP 10-Lead Plastic MSOP –40°C to 85°C

LTC1403HMSE#PBF LTC1403HMSE#TRPBF LTBDP 10-Lead Plastic MSOP –40°C to 125°C

LTC1403ACMSE#PBF LTC1403ACMSE#TRPBF LTADF 10-Lead Plastic MSOP 0°C to 70°C

LTC1403AIMSE#PBF LTC1403AIMSE#TRPBF LTAFD 10-Lead Plastic MSOP –40°C to 85°C

LTC1403AHMSE#PBF LTC1403AHMSE#TRPBF LTAFD 10-Lead Plastic MSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

AIN+

AIN–

VREF

GND

CONV

SCK

SDO

VDD

GND

TOP VIEW

GND

MSE PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 150°C, qJA = 40°C/W

EXPOSED PAD (PIN 11) IS GND

MUST BE SOLDERED TO PCB

http://www.linear.com/product/LTC1403#orderinfo

LTC1403/LTC1403A

1403fc

For more information www.linear.com/LTC1403

converter characteristics

PARAMETER CONDITIONS

LTC1403 LTC1403H LTC1403A LTC1403AH

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l12 12 14 14 Bits

Integral Linearity Error (Notes 4, 5, 18) l–2 ±0.25 2 –2 ±0.25 2 –4 ±0.5 4 –4 ±0.5 4 LSB

Offset Error (Notes 4, 18) l–10 ±1 10 –20 ±2 20 –20 ±2 20 –30 ±2 30 LSB

Gain Error (Note 4, 18) l–30 ±5 30 –40 ±5 40 –60 ±10 60 –80 ±10 80 LSB

Gain Tempco Internal Reference (Note 4)

External Reference

±15

±1

±15

±1

±15

±1

±15

±1

ppm/°C

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. With internal reference. VDD = 3V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Differential Input Range (Notes 3, 9) 2.7V ≤ VDD ≤ 3.3V l0 to 2.5 V

VCM Analog Common Mode + Differential Input Range (Note 10) 0 to VDD V

IIN Analog Input Leakage Current l1 µA

CIN Analog Input Capacitance 13 pF

tACQ Sample-and-Hold Acquisition Time (Note 6) l39 ns

tAP Sample-and-Hold Aperture Delay Time 1 ns

tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ps

CMRR Analog Input Common Mode Rejection Ratio fIN = 1MHz, VIN = 0V to 3V

fIN = 100MHz, VIN = 0V to 3V

–60

–15

analog input

The l denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA = 25°C. VDD = 3V

The

l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C. VDD = 3V

Dynamic accuracy

SYMBOL PARAMETER CONDITIONS

LTC1403/LTC1403H LTC1403A/LTC1403AH

UNITSMIN TYP MAX MIN TYP MAX

SINAD Signal-to-Noise Plus

Distortion Ratio

100kHz Input Signal

1.4MHz Input Signal

1.4MHz Input Signal (H Grade)

100kHz Input Signal, External VREF = 3.3V,

VDD ≥ 3.3V

750kHz Input Signal, External VREF = 3.3V,

VDD ≥ 3.3V

70.5

73.5

73.0

76.3

THD Total Harmonic

Distortion

100kHz First 5 Harmonics

1.4MHz First 5 Harmonics

–87

–83

–76

–90

–86

–78

SFDR Spurious Free

Dynamic Range

100kHz Input Signal

1.4MHz Input Signal

–87

–83

–90

–86

IMD Intermodulation

Distortion

1.25V to 2.5V 1.25MHz into AIN+, 0V to 1.25V,

1.2MHz into AIN–

–82 –82 dB

Code-to-Code

Transition Noise

VREF = 2.5V (Note 18) 0.25 1 LSBRMS

Full Power Bandwidth VIN = 2.5VP-P, SDO = 11585LSBP-P (Note 15) 50 50 MHz

Full Linear Bandwidth S/(N + D) ≥ 68dB 5 5 MHz

LTC1403/LTC1403A

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SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage 2.7 3.6 V

IDD Positive Supply Voltage Active Mode

Active Mode (LTC1403H, LTC1403AH)

Nap Mode

Nap Mode (LTC1403H, LTC1403AH)

Sleep Mode (LTC1403, LTC1403H)

Sleep Mode (LTC1403A, LTC1403AH)

4.7

5.2

1.1

1.2

1.5

1.8

µA

PDPower Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 12 mW

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 17)

power requirements

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VDD = 3.3V l2.4 V

VIL Low Level Input Voltage VDD = 2.7V l0.6 V

IIN Digital Input Current VIN = 0V to VDD l±10 µA

CIN Digital Input Capacitance 5 pF

VOH High Level Output Voltage VDD = 3V, IOUT = –200µA l2.5 2.9 V

VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160µA

VDD = 2.7V, IOUT = 1.6mA

0.05

0.10

0.4

IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l±10 µA

COZ Hi-Z Output Capacitance DOUT 1 pF

ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3V 20 mA

ISINK Output Short-Circuit Sink Current VOUT = VDD = 3V 15 mA

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V

Digital inputs anD Digital outputs

PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF Output Voltage IOUT = 0 2.5 V

VREF Output Tempco 15 ppm//°C

VREF Line Regulation VDD = 2.7V to 3.6V, VREF = 2.5V 600 µV/V

VREF Output Resistance Load Current = 0.5mA 0.2 Ω

VREF Settling Time 2 ms

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 3V

internal reFerence characteristics

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSAMPLE(MAX) Maximum Sampling Frequency per Channel (Conversion Rate) l2.8 MHz

tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisition Period) l357 ns

tSCK Clock Period (Notes 16) l19.8 10000 ns

tCONV Conversion Time (Note 6) 17 18 SCLK cycles

t1Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns

t2CONV to SCK Setup Time (Notes 6, 10) 3 ns

t3Nearest SCK Edge Before CONV (Note 6) 0 ns

t4Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns

t5SCK to Sample Mode (Note 6) 4 ns

t6CONV to Hold Mode (Notes 6, 11) 1.2 ns

t716th SCK↑ to CONV↑ Interval (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns

t8Minimum Delay from SCK to Valid Bits 0 Through 13 (Notes 6, 12) 8 ns

t9SCK to Hi-Z at SDO (Notes 6, 12) 6 ns

t10 Previous SDO Bit Remains Valid After SCK (Notes 6, 12) 2 ns

t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 6, 14) 2 ms

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VDD = 3V

timing characteristics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: When these pins are taken below GND or above VDD, they will be

clamped by internal diodes. This product can handle input currents greater

than 100mA below GND or greater than VDD without latchup.

Note 4: Offset and full-scale specifications are measured for a single-

ended AIN+ input with AIN– grounded and using the internal 2.5V reference.

Note 5: Integral linearity is tested with an external 2.55V reference and is

defined as the deviation of a code from the straight line passing through

the actual endpoints of a transfer curve. The deviation is measured from

the center of quantization band.

Note 6: Guaranteed by design, not subject to test.

Note 7: Recommended operating conditions.

Note 8: The analog input range is defined for the voltage difference

between AIN+ and AIN–.

Note 9: The absolute voltage at AIN+ and AIN– must be within this range.

Note 10: If less than 3ns is allowed, the output data will appear one

clock cycle later. It is best for CONV to rise half a clock before SCK, when

running the clock at rated speed.

Note 11: Not the same as aperture delay. Aperture delay is smaller (1ns)

because the 2.2ns delay through the sample-and-hold is subtracted from

the CONV to Hold mode delay.

Note 12: The rising edge of SCK is guaranteed to catch the data coming

out into a storage latch.

Note 13: The time period for acquiring the input signal is started by the

16th rising clock and it is ended by the rising edge of convert.

Note 14: The internal reference settles in 2ms after it wakes up from Sleep

mode with one or more cycles at SCK and a 10µF capacitive load.

Note 15: The full power bandwidth is the frequency where the output code

swing drops to 3dB with a 2.5VP-P input sine wave.

Note 16: Maximum clock period guarantees analog performance during

conversion. Output data can be read without an arbitrarily long clock.

Note 17: VDD = 3V, fSAMPLE = 2.8Msps.

Note 18: The LTC1403A is measured and specified with 14-bit Resolution

(1LSB = 152µV) and the LTC1403 is measured and specified with 12-bit

Resolution (1LSB = 610µV).

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

typical perFormance characteristics

ENOBs and SINAD

vs Input Frequency

THD, 2nd and 3rd vs Input

Frequency SFDR vs Input Frequency

SNR vs Input Frequency

98kHz Sine Wave 4096 Point

FFT Plot

1.3MHz Sine Wave 4096 Point

FFT Plot

1.4MHz Input Summed with

1.56MHz Input IMD 4096 Point

FFT Plot

Differential Linearity

vs Output Code

Integral Linearity

vs Output Code

TA = 25°C, VDD = 3V (LTC1403A)

FREQUENCY (MHz)

0.1

10.0

ENOBs (BITS)

SINAD (dB)

11.0

12.0

1 10 100

1403A G01

9.0

9.5

10.5

11.5

8.5

8.0

FREQUENCY (MHz)

0.1

–80

THD, 2nd, 3rd (dB)

–74

–68

–62

–56

1 10 100

1403A G02

–86

–92

–98

–104

–50

–44

THD

3rd

2nd

FREQUENCY (MHz)

0.1

SFDR (dB)

44 1 10 100

1403A G03

104

FREQUENCY (MHz)

0.1

SNR (dB)

50 1 10 100

1403A G04

FREQUENCY (Hz)

0 350k 700k 1.05M 1.4M

MAGNITUDE (dB)

1403A G05

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

2.8Msps

FREQUENCY (Hz)

MAGNITUDE (dB)

1403A G06

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 0 350k 700k 1.05M 1.4M

2.8Msps

FREQUENCY (Hz)

MAGNITUDE (dB)

1403A G07

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120 0 350k 700k 1.05M 1.4M

2.8Msps

OUTPUT CODE

0 81924096 12288 16383

DIFFERENTIAL LINEARITY (LSB)

1403A G08

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

OUTPUT CODE

0 81924096 12288 16383

INTEGRAL LINEARITY (LSB)

1403A G09

–1

–2

–3

–4

LTC1403/LTC1403A

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typical perFormance characteristics

TA = 25°C, VDD = 3V (LTC1403A)

Differential and Integral Linearity

vs Conversion Rate

SINAD vs Conversion Rate

2.5VP-P Power Bandwidth

CMRR vs Frequency

PSRR vs Frequency

Reference Voltage vs Load

Current

Reference Voltage vs VDD

VDD Supply Current vs

Conversion Rate

TA = 25°C, VDD = 3V (LTC1403 and LTC1403A)

CONVERSION RATE (Msps)

2.0 2.2 3.02.6 3.8 4.02.82.4 3.43.2

LINEARITY (LSB)

1403A G10

–1

–2

–3

–4

–5

MAX INL

18 CLOCKS PER CONVERSION

MAX DNL

MIN DNL

MIN INL

3.6

CONVERSION RATE (Msps)

2.0 2.2 3.02.6 3.8 4.02.82.4 3.4 3.63.2

S/(N+D)

1403A G11

EXTERNAL VREF = 3.3V fIN~fS/40

INTERNAL VREF = 2.5V fIN~fS/40

INTERNAL VREF = 2.5V fIN~fS/3

EXTERNAL VREF = 3.3V fIN~fS/3

FREQUENCY (Hz)

1M 10M 100M 1G

–18

AMPLITUDE (dB)

–12

–6

1403A G12

–24

–30

–36

FREQUENCY (Hz)

100

CMRR (dB)

–20

–40

–60

–80

–100

–120 1k 10k 100k 1M

1403A G13

10M 100M

FREQUENCY (Hz)

1 10

–50

PSRR (dB)

–45

–40

–35

–30

100 1k 10k 100k 1M

1403A G14

–55

–60

–65

–70

–25

LOAD CURRENT (mA)

0.4 0.8 1.2 1.6

1403A G15

2.00.20 0.6 1.0 1.4 1.8

2.4890

VREF (V)

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

VDD (V)

2.4890

VREF (V)

2.4894

2.4898

2.4902

2.4892

2.4896

2.4900

2.8 3.0 3.2 3.4

1403A G16

2.6 3.6

CONVERSION RATE (Msps)

0 2.01.61.20.80.4 2.8 3.22.4 3.6 4.0

VDD SUPPLY CURRENT (mA)

1403A G17

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

LTC1403/LTC1403A

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Block Diagram

pin Functions

AIN+ (Pin 1): Noninverting Analog Input. AIN+ operates

fully differentially with respect to AIN– with a 0V to 2.5V

differential swing and a 0V to VDD common mode swing.

AIN– (Pin 2): Inverting Analog Input. AIN– operates

fully differentially with respect to AIN+ with a –2.5V to 0V

differential swing and a 0V to VDD common mode swing.

VREF (Pin 3): 2.5V Internal Reference. Bypass to GND

and to a solid analog ground plane with a 10µF ceramic

capacitor (or 10µF tantalum in parallel with 0.1µF ceramic).

Can be overdriven by an external reference between 2.55V

and VDD.

GND (Pins 5, 6, 11): Ground and Exposed Pad. These

ground pins and the exposed pad must be tied directly to

the solid ground plane under the part. Keep in mind that

analog signal currents and digital output signal currents

flow through these pins.

VDD (Pin 7): 3V Positive Supply. This single power pin

supplies 3V to the entire chip. Bypass to GND and to a

solid analog ground plane with a 10µF ceramic capacitor

(or 10µF tantalum in parallel with 0.1µF ceramic). Keep in

mind that internal analog currents and digital output signal

currents flow through this pin. Care should be taken to

place the 0.1µF bypass capacitor as close to Pins 6 and

7 as possible.

SDO (Pin 8): Three-State Serial Data Output. Each of output

data words represents the difference between AIN+ and

AIN– analog inputs at the start of the previous conversion.

SCK (Pin 9): External Clock Input. Advances the conver-

sion process and sequences the output data on the rising

edge. Responds to TTL (≤3V) and 3V CMOS levels. One

or more pulses wake from sleep.

CONV (Pin 10): Convert Start. Holds the analog input signal

and starts the conversion on the rising edge. Responds

to TTL (≤3V) and 3V CMOS levels. Two pulses with SCK

in fixed high or fixed low state start Nap mode. Four or

more pulses with SCK in fixed high or fixed low state start

Sleep mode.

1403A BD

–

S & H

GND

EXPOSED PAD

LTC1403A

VREF

10µF

AIN–

AIN+

14-BIT ADC

3V10µF

14-BIT LATCH

THREE-

STATE

SERIAL

OUTPUT

PORT

2.5V

REFERENCE

TIMING

LOGIC

VDD

SDO

CONV

SCK

5 6 11

LTC1403/LTC1403A

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timing Diagram

LTC1403 Timing Diagram

SCK

CONV

INTERNAL

S/H STATUS

SDO

t3t1

11716 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

t8t10

t4t5

t8t9

tACQ

SAMPLE HOLD HOLD

Hi-Z Hi-Z

tCONV

14-BIT DATA WORD

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

*BITS MARKED "X" AFTER D0 SHOULD BE IGNORED.

tTHROUGHPUT

1403A TD01

D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 X XD9

SAMPLE

LTC1403A Timing Diagram

SCK

CONV

INTERNAL

S/H STATUS

SDO

t3t1

11716 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

t8t10

t4t5

t8t9

tACQ

SAMPLE HOLD HOLD

Hi-Z Hi-Z

tCONV

14-BIT DATA WORD

SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION

tTHROUGHPUT

1403A TD01b

D13 D12 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D11

SAMPLE

Nap Mode and Sleep Mode Waveforms

SLK

CONV

NAP

SLEEP

VREF

t12

NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS 1403A TD02

SCK to SDO Delay

t10

SCK

SDO

1403A TD03

VIH

VOH

VOL

SCK

SDO

VIH

90%

10%

LTC1403/LTC1403A

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applications inFormation

DRIVING THE ANALOG INPUT

The differential analog inputs of the LTC1403/LTC1403A

are easy to drive. The inputs may be driven differentially or

as a single-ended input (i.e., the AIN– input is grounded).

Both differential analog inputs, AIN+ with AIN–, are sampled

at the same instant. Any unwanted signal that is common

to both inputs of each input pair will be reduced by the

common mode rejection of the sample-and-hold circuit.

The inputs draw only one small current spike while charging

the sample-and-hold capacitors at the end of conversion.

During conversion, the analog inputs draw only a small

leakage current. If the source impedance of the driving

circuit is low, then the LTC1403/LTC1403A inputs can be

driven directly. As source impedance increases, so will

acquisition time. For minimum acquisition time with high

source impedance, a buffer amplifier must be used. The

main requirement is that the amplifier driving the analog

input(s) must settle after the small current spike before

the next conversion starts (settling time must be 39ns

for full throughput rate). Also keep in mind while choos-

ing an input amplifier, the amount of noise and harmonic

distortion added by the amplifier.

CHOOSING AN INPUT AMPLIFIER

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<100Ω) at the closed-loop bandwidth

frequency. For example, if an amplifier is used in a gain

of 1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz must be less than 100Ω. The

second requirement is that the closed-loop bandwidth must

be greater than 40MHz to ensure adequate small-signal

settling for full throughput rate. If slower op amps are

used, more time for settling can be provided by increasing

the time between conversions. The best choice for an op

amp to drive the LTC1403/LTC1403A will depend on the

application. Generally, applications fall into two categories:

AC applications where dynamic specifications are most

critical and time domain applications where DC accuracy

and settling time are most critical. The following list is

a summary of the op amps that are suitable for driving

the LTC1403/LTC1403A. (More detailed information is

available in the Linear Technology Databooks and on the

LinearView

CD-ROM.)

LT C

1566-1: Low Noise 2.3MHz Continuous Time Low-

Pass Filter.

LT1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to ±15V supplies. Very high AVOL, 500µV offset and

520ns settling to 0.5LSB for a 4V swing. THD and noise

are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,

2VP-P into 1kΩ, VS = 5V), making the part excellent for AC

applications (to 1/3 Nyquist) where rail-to-rail performance

is desired. Quad version is available as LT1631.

LT1632: Dual 45MHz Rail-to-Rail Voltage FB Amplifier.

2.7V to ±15V supplies. Very high AVOL, 1.5mV offset and

400ns settling to 0.5LSB for a 4V swing. It is suitable

for applications with a single 5V supply. THD and noise

are –93dB to 40kHz and below 1LSB to 800kHz (AV = 1,

2VP-P into 1kΩ, VS = 5V), making the part excellent for

AC applications where rail-to-rail performance is desired.

Quad version is available as LT1633.

LT1813: Dual 100MHz 750V/µs 3mA Voltage Feedback

Amplifier. 5V to ±5V supplies. Distortion is –86dB to 100kHz

and –77dB to 1MHz with ±5V supplies (2VP-P into 500Ω).

Excellent part for fast AC applications with ±5V supplies.

LT1801: 80MHz GBWP, –75dBc at 500kHz, 2mA/Amplifier,

8.5nV/√Hz.

LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at

5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli-

fier, 3.5nV/√Hz.

LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz, Unity-

Gain Stable, R-R In and Out, 15mA/Amplifier, 16nV/√Hz.

LT1818/LT1819: 400MHz, 2500V/µs,9mA, Single/Dual

Voltage Mode Operational Amplifier.

LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,

Unity-Gain Stable, R-R In and Out, 15mA/Amplifier,

0.95nV/√Hz.

LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz, Unity-

Gain Stable, R-R In and Out, 3mA/Amplifier, 1.9nV/√Hz.

LT6600-10: Amplifier/Filter Differential In/Out with 10MHz

Cutoff.

LTC1403/LTC1403A

1403fc

For more information www.linear.com/LTC1403

applications inFormation

Figure 1. RC Input Filter

INPUT FILTERING AND SOURCE IMPEDANCE

The noise and the distortion of the input amplifier and other

circuitry must be considered since they will add to the

LTC1403/LTC1403A noise and distortion. The small-signal

bandwidth of the sample-and-hold circuit is 50MHz. Any

noise or distortion products that are present at the analog

inputs will be summed over this entire bandwidth. Noisy

input circuitry should be filtered prior to the analog inputs

to minimize noise. A simple 1-pole RC filter is sufficient for

many applications. For example, Figure 1 shows a 47pF

capacitor from AIN+ to ground and a 51Ω source resistor to

limit the input bandwidth to 47MHz. The 47pF capacitor also

acts as a charge reservoir for the input sample-and-hold

and isolates the ADC input from sampling-glitch sensitive

circuitry. High quality capacitors and resistors should be

used since these components can add distortion. NPO

and silvermica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occur during soldering. Metal film surface mount resistors

are much less susceptible to both problems. When high

amplitude unwanted signals are close in frequency to the

desired signal frequency, a multiple pole filter is required.

High external source resistance, combined with the 13pF of

input capacitance, will reduce the rated 50MHz bandwidth

and increase acquisition time beyond 39ns.

INPUT RANGE

The analog inputs of the LTC1403/LTC1403A may be

driven fully differentially with a single supply. Each input

may swing up to 3VP-P individually. In the conversion

range, the noninverting input of each channel is always

up to 2.5V more positive than the inverting input of each

channel. The 0V to 2.5V range is also ideally suited for

single-ended input use with single supply applications. The

common mode range of the inputs extend from ground to

the supply voltage VDD. If the difference between the AIN+

and AIN– inputs exceeds 2.5V, the output code will stay

fixed at all ones and if this difference goes below 0V, the

output code will stay fixed at all zeros.

INTERNAL REFERENCE

The LTC1403/LTC1403A has an on-chip, temperature

compensated, bandgap reference that is factory trimmed

near 2.5V to obtain 2.5V input span. The reference amplifier

output VREF, (Pin 3) must be bypassed with a capacitor to

ground. The reference amplifier is stable with capacitors

of 1µF or greater. For the best noise performance, a 10µF

ceramic or a 10µF tantalum in parallel with a 0.1µF ceramic

is recommended. The VREF pin can be overdriven with an

external reference as shown in Figure 2. The voltage of

the external reference must be higher than the 2.5V of

the class A pull-up output of the internal reference. The

recommended range for an external reference is 2.55V to

VDD. An external reference at 2.55V will see a DC quiescent

load of 0.75mA and as much as 3mA during conversion.

Figure 2

GND

LTC1403/

LTC1403A

VREF

10µF

3VREF

1403A F02

10µF

AIN–

LTC1403/

LTC1403A

AIN+

47pF

51Ω

GND

VREF

1403A F01

LTC1403/LTC1403A

1403fc

For more information www.linear.com/LTC1403

applications inFormation

INPUT SPAN VERSUS REFERENCE VOLTAGE

The differential input range has a unipolar voltage span that

equals the difference between the voltage at the reference

buffer output VREF at Pin 3, and the voltage at the ground

(Exposed Pad Ground). The differential input range of

the ADC is 0V to 2.5V when using the internal reference.

The internal ADC is referenced to these two nodes. This

relationship also holds true with an external reference.

DIFFERENTIAL INPUTS

The LTC1403/LTC1403A has a unique differential sample-

and-hold circuit that allows inputs from ground to VDD.

The ADC will always convert the unipolar difference of

AIN+ – AIN–, independent of the common mode voltage

at the inputs. The common mode rejection holds up at

extremely high frequencies, see Figure 3. The only require-

ment is that both inputs not go below ground or exceed

VDD. Integral nonlinearity errors (INL) and differential

nonlinearity errors (DNL) are largely independent of the

common mode voltage. However, the offset error will vary.

The change in offset error is typically less than 0.1% of

the common mode voltage.

Figure 4 shows the ideal input/output characteristics for

the LTC1403/LTC1403A. The code transitions occur mid-

way between successive integer LSB values (i.e., 0.5LSB,

1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural

binary with 1LSB = 2.5V/16384 = 153µV for the LTC1403A,

and 1LSB = 2.5V/4096 = 610µV for the LTC1403. The

LTC1403A has 1LSB RMS of random white noise.

Figure 3 Figure 4

CMRR vs Frequency

LTC1403/LTC1403A Transfer

Characteristic

FREQUENCY (Hz)

100

CMRR (dB)

–20

–40

–60

–80

–100

–120 1k 10k 100k 1M

1403A F03

10M 100M

INPUT VOLTAGE (V)

UNIPOLAR OUTPUT CODE

1403A F04

111...111

111...110

111...101

000...000

000...001

000...010

FS – 1LSB0

LTC1403/LTC1403A

1403fc

For more information www.linear.com/LTC1403

applications inFormation

Board Layout and Bypassing

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1403/LTC1403A, a printed circuit

board with ground plane is required. Layout for the printed

circuit board should ensure that digital and analog signal

lines are separated as much as possible. In particular, care

should be taken not to run any digital track alongside an

analog signal track. If optimum phase match between the

inputs is desired, the length of the two input wires should

be kept matched.

High quality tantalum and ceramic bypass capacitors

should be used at the VDD and VREF pins as shown in

the Block Diagram on the first page of this data sheet.

For optimum performance, a 10µF surface mount AVX

capacitor with a 0.1µF ceramic is recommended for the

VDD and VREF pins. Alternatively, 10µF ceramic chip capaci-

tors such as Murata GRM235Y5V106Z016 may be used.

The capacitors must be located as close to the pins as

possible. The traces connecting the pins and the bypass

capacitors must be kept short and should be made as

wide as possible.

Figure 5 shows the recommended system ground connec-

tions. All analog circuitry grounds should be terminated

at the LTC1403/LTC1403A GND (Pins 4, 5, 6 and exposed

pad). The ground return from the LTC1403/LTC1403A (Pins

4, 5, 6 and exposed pad) to the power supply should be

low impedance for noise free operation. Digital circuitry

grounds must be connected to the digital supply com-

mon. In applications where the ADC data outputs and

control signals are connected to a continuously active

microprocessor bus, it is possible to get errors in the

conversion results. These errors are due to feedthrough

from the microprocessor to the successive approximation

comparator. The problem can be eliminated by forcing the

microprocessor into a Wait state during conversion or

by using three-state buffers to isolate the ADC data bus.

POWER-DOWN MODES

Upon power-up, the LTC1403/LTC1403A is initialized to

the active state and is ready for conversion. The Nap and

Sleep mode waveforms show the power-down modes for

the LTC1403/LTC1403A. The SCK and CONV inputs control

the power-down modes (see Timing Diagrams). Two rising

edges at CONV, without any intervening rising edges at SCK,

put the LTC1403/LTC1403A in Nap mode and the power

drain drops from 14mW to 6mW. The internal reference

remains powered in Nap mode. One or more rising edges

at SCK wake up the LTC1403/LTC1403A for service very

quickly, and CONV can start an accurate conversion within

a clock cycle. Four rising edges at CONV, without any

Figure 5. Recommended Layout

LTC1403/LTC1403A

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applications inFormation

intervening rising edges at SCK, put the LTC1403/

LTC1403A in Sleep mode and the power drain drops from

16mW to 10µW. One or more rising edges at SCK wake up

the LTC1403/LTC1403A for operation. The internal refer-

ence (VREF) takes 2ms to slew and settle with a 10µF load.

Note that, using sleep mode more frequently than every

2ms, compromises the settled accuracy of the internal

reference. Note that, for slower conversion rates, the Nap

and Sleep modes can be used for substantial reductions

in power consumption.

DIGITAL INTERFACE

The LTC1403/LTC1403A has a 3-wire SPI (Serial Protocol

Interface) interface. The SCK and CONV inputs and SDO

output implement this interface. The SCK and CONV inputs

accept swings from 3V logic and are TTL compatible, if the

logic swing does not exceed VDD. A detailed description

of the three serial port signals follows:

Conversion Start Input (CONV)

The rising edge of CONV starts a conversion, but subse-

quent rising edges at CONV are ignored by the LTC1403/

LTC1403A until the following 16 SCK rising edges have

occurred and track mode starts again. It is also neces-

sary to have a minimum of 17 rising edges of the clock

input SCK between rising edges of CONV for SDO to go

to the Hi-Z state and to prepare the internal ADC logic for

the next conversion. But to obtain maximum conversion

speed, it is necessary to allow one more clock period

between conversions to allow 39ns of acquisition time

for the internal ADC sample-and-hold circuit. With 17

clock periods per conversion, the maximum conversion

rate is limited to 2.8Msps to allow 39ns for acquisition

time. In either case, the output data stream comes out

within the first 16 clock periods to ensure compatibility

with processor serial ports. The duty cycle of CONV can

be arbitrarily chosen to be used as a frame sync signal for

the processor serial port. A simple approach to generate

CONV is to create a pulse that is one SCK wide to drive

the LTC1403/LTC1403A and then buffer this signal with

the appropriate number of inverters to ensure the correct

delay driving the frame sync input of the processor serial

port. It is good practice to drive the LTC1403/LTC1403A

CONV input first to avoid digital noise interference during

the sample-to-hold transition triggered by CONV at the start

of conversion. It is also good practice to keep the width

of the low portion of the CONV signal greater than 15ns

to avoid introducing glitches in the front end of the ADC

just before the sample-and-hold goes into hold mode at

the rising edge of CONV.

Minimizing Jitter on the CONV Input

In high speed applications where high amplitude sinewaves

above 100kHz are sampled, the CONV signal must have

as little jitter as possible (10ps or less). The square wave

output of a common crystal clock module usually meets

this requirement easily. The challenge is to generate a CONV

signal from this crystal clock without jitter corruption from

other digital circuits in the system. A clock divider and

any gates in the signal path from the crystal clock to the

CONV input should not share the same integrated circuit

with other parts of the system. As shown in the interface

circuit examples, the SCK and CONV inputs should be

driven first, with digital buffers used to drive the serial port

interface. Also note that the master clock in the DSP may

already be corrupted with jitter, even if it comes directly

from the DSP crystal. Another problem with high speed

processor clocks is that they often use a low cost, low

speed crystal (i.e., 10MHz) to generate a fast, but jittery,

phase-locked-loop system clock (i.e., 40MHz). The jitter

in these PLL-generated high speed clocks can be several

nanoseconds. Note that if you choose to use the frame

sync signal generated by the DSP port, this signal will

have the same jitter of the DSP’s master clock.

Serial Clock Input (SCK)

The rising edge of SCK advances the conversion process

and also updates each bit in the SDO data stream. After

CONV rises, the third rising edge of SCK starts clocking out

the 12/14 data bits with the MSB sent first. A simple ap-

proach is to generate SCK to drive the LTC1403/LTC1403A

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

applications inFormation

Figure 6. DSP Serial Interface to TMS320C54x

first and then buffer this signal with the appropriate number

of inverters to drive the serial clock input of the processor

serial port. Use the falling edge of the clock to latch data

from the Serial Data Output (SDO) into your processor

serial port. The 14-bit Serial Data will be received right

justified, in a 16-bit word with 17 or more clocks per frame

sync. It is good practice to drive the LTC1403/LTC1403A

SCK input first to avoid digital noise interference during

the internal bit comparison decision by the internal high

speed comparator. Unlike the CONV input, the SCK input

is not sensitive to jitter because the input signal is already

sampled and held constant.

Serial Data Output (SDO)

Upon power-up, the SDO output is automatically reset to

the high impedance state. The SDO output remains in high

impedance until a new conversion is started. SDO sends

out 12/14 bits in the output data stream beginning at the

third rising edge of SCK after the rising edge of CONV.

SDO is always in high impedance mode when it is not

sending out data bits. Please note the delay specification

from SCK to a valid SDO. SDO is always guaranteed to

be valid by the next rising edge of SCK. The 16-bit output

data stream is compatible with the 16-bit or 32-bit serial

port of most processors.

HARDWARE INTERFACE TO TMS320C54X

The LTC1403/LTC1403A is a serial output ADC whose

interface has been designed for high speed buffered serial

ports in fast digital signal processors (DSPs). Figure 6

shows an example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial

data can be collected in two alternating 1kB segments,

in real time, at the full 2.8Msps conversion rate of the

LTC1403/LTC1403A. The DSP assembly code sets frame

sync mode at the BFSR pin to accept an external positive

going pulse and the serial clock at the BCLKR pin to accept

an external positive edge clock. Buffers near the LTC1403/

LTC1403A may be added to drive long tracks to the DSP

to prevent corruption of the signal to LTC1403/LTC1403A.

This configuration is adequate to traverse a typical system

board, but source resistors at the buffer outputs and ter-

mination resistors at the DSP, may be needed to match the

characteristic impedance of very long transmission lines.

If you need to terminate the SDO transmission line, buffer

it first with one or two 74ACTxx gates. The TTL threshold

inputs of the DSP port respond properly to the 3V swing

from the SDO pin.

1403A F06

3-WIRE SERIAL

INTERFACELINK

VDD

CONV

SCK

LTC1403/

LTC1403A

SDO

VCC

BFSR

BCLKR

TMS320C54x

BDR

GND

CONV

0V TO 3V LOGIC SWING

CLK

3V 5V

B13 B12

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

applications inFormation

; 01-08-01 ******************************************************************

; Files: 014SI.ASM -> 1403A Sine wave collection with Serial Port interface

; bvectors.asm buffered mode to avoid standard mode bug.

; s2k14ini.asm 2k buffer size.

; first element at 1024, last element at 1023, two middles at 2047 and 0000

; unipolar mode

; negative edge BCLKR

; negative BFSR pulse

; -0 data shifted

; 1’ cable from counter to CONV at DUT

; 2’ cable from counter to CLK at DUT

; ***************************************************************************

.widt h 160

.length 110

.title “sineb0 BSP in auto buffer mode”

.mmregs

.setsect “.t e x t”, 0x500,0 ;Set address of executable

.setsect “vectors”, 0x180,0 ;Set address of incoming 1403 data

.setsect “buffer”, 0x800,0 ;Set address of BSP buffer for clearing

.setsect “result”, 0x1800,0 ;Set address of result for clearing

.text ;.text marks start of code

start:

;this label seems necessary

;Make sure /PWRDWN is low at J1-9

;to turn off AC01 adc

tim=#0fh

prd=#0fh

tcr = #10h ; stop timer

tspc = #0h ; stop TDM serial port to AC01

pmst = #01a0h ; set up iptr. Processor Mode STatus register

sp = #0700h ; init stack pointer.

dp = #0 ; data page

ar2 = #1800h ; pointer to computed receive buffer.

ar3 = #0800h ; pointer to Buffered Serial Port receive buffer

ar4 = #0h ; reset record counter

call sineinit ; Double clutch the initialization to insure a proper

sinepeek:

call sineinit ; reset. The external frame sync must occur 2.5 clocks

; or more after the port comes out of reset.

wait goto wait

; ----------------Buffered Receive Interrupt Routine ------------------

breceive:

ifr = #10h ; clear interrupt flags

TC = bit f(@BS P C E,# 4000h) ; check which half (bspce(bit14)) of buffer

if (NTC) goto bufull ; if this still the first half get next half

bspce = #(2023h + 08000h); turn on halt for second half (bspce(bit15))

return _ enable

; --------------mask and shift input data ----------------------------

bufull:

b = *ar3+ << -0 ; load acc b with BSP buffer and shift right -0

b = #03FFFh & b ; mask out the TRISTATE bits with #03FFFh

;

*ar2+ = d at a(#0bh) ; store B to out buffer and advance AR2 pointer

TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h

if (TC) goto start ; restart if out buffer is at 1fffh

goto bufull

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

; -------------------dummy bsend return------------------------

bsend return _ enable ;this is also a dummy return to define bsend

;in vector table file BVECTORS.ASM

; ----------------------- end ISR ----------------------------

.copy “c:\ dskplus\1403\s2k14i ni.asm” ;initialize buffered serial port

.space 16*32 ;clear a chunk at the end to mark the end

;======================================================================

;

; VECTORS

;

;======================================================================

.sect “vectors” ;The vectors start here

.copy “c:\ dskplus\1403\bvectors.asm” ;get BSP vectors

.sect “buffer” ;Set address of BSP buffer for clearing

.s p ac e 16*0x800

.sect “result” ;Set address of result for clearing

.s p ac e 16*0x800

.end

**********************************************************************

* *

* File: s2k 14ini.ASM BSP initialization code for the ‘C54x DSKplus *

* for use with 1403A in standard mode *

* BSPC and SPC are the same in the ‘C542 *

* BSPCE and SPCE seem the same in the ‘C542 *

**********************************************************************

.title “Buffered Serial Port Initialization Routine”

ON .set 1

OFF .set !ON

YES .set 1

NO .set !YES

BIT _ 8 .set 2

BIT _ 10 .set 1

BIT _ 12 .set 3

BIT _ 16 .set 0

GO .set 0x80

**********************************************************************

* This is an example of how to initialize the Buffered Serial Port (BSP).

* The BSP is initialized to require an external CLK and FSX for

* operation. The data format is 16-bits, burst mode, with autobuffering

* enabled.

*****************************************************************************************************

*LTC1403 timing from LCC28 socket board with 10MHz crystal. *

*10MHz, divided from 40MHz, forced to CLKIN by 1403 board. *

*Horizontal scale is 25ns/chr or 100ns period at BCLKR . *

*Timing measured at DSP pins. Jxx pin labels for jumper cable. *

*BFSR Pin J1-20 ~~\ ____/~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\ ____/~~~~~~~~~~~*

*BCLKR Pin J1-14 _ /~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~\ _/~*

*BDR Pin J1-26 _ --- _ --- _ ---<B13-B12-B11-B10-B09-B08-B07-B06-B05-B04-B03-B02-B01-B00>--- _ ---<B13-B12*

*CLKIN Pin J5-09 ~~~~~\ _______/~~~~~~~\ _______/~~~~~~~\ _______/~~~~~~~\ _______/~~~~~~~\

_______/~~~~~*

*C542 read 0 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 0 0 B13 B12*

applications inFormation

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

applications inFormation

* *

* negative edge BCLKR

* negative BFSR pulse

* no data shifted

* 1’ cable from counter to CONV at DUT

* 2’ cable from counter to CLK at DUT

*No right shift is needed to right justify the input data in the main program *

*the two msbs should also be masked ................... *

*****************************************************************************************************

Loopback .set NO ;(digital looback mode?) DLB bit

Format .set BIT _ 16 ;(Data format? 16,12,10,8) F O b it

IntSync .set NO ;(internal Frame syncs generated?) TXM bit

IntCLK .set NO ;(internal clks generated?) MCM bit

BurstMode .set YES ;(if BurstMode=NO, then Continuous) FSM bit

CLKDIV .set 3 ;(3=default value, 1/4 CLOCKOUT)

PCM _ Mode .set NO ;(Turn on PCM mode?)

FS _ polarity .set YES ;(change polarity)YES=^^^\ _/^^^, NO= ___/^\ ___

CLK _ polarity .set NO ;(change polarity)for BCLKR YES= _/^, NO=~\ _

Frame _ ignore .set !YES ;(inverted !YES -ignores frame)

XMTautobuf .set NO ;(transmit autobuffering)

RCVautobuf .set YES ;(receive autobuffering)

XMThalt .set NO ;(transmit buff halt if XMT buff is full)

RCVhalt .set NO ;(receive buff halt if RCV buff is full)

XMTbufAddr .set 0x800 ;(address of transmit buffer)

XMTbufSize .set 0x000 ;(length of transmit buffer)

RCVbufAddr .set 0x800 ;(address of receive buffer)

RCVbufSize .set 0x800 ;(length of receive buffer)works up to 800

* See notes in the ‘C54x CPU and Peripherals Reference Guide on setting up

* valid buffer start and length values. Page 9-44

**********************************************************************

.eval ((Loopback >> 1)|((Format & 2)<<1)|(BurstMode <<3)|(IntCLK <<4)|(IntSync <<5)) ,S P C v a l

.eval (SPCEval|(XMTautobuf<<10)|(XMThalt<<12)|(RCVautobuf<<13)|(RCVhalt<<1 5)), S P C E v a l

sineinit:

bspc = #SPCval ; places buffered serial port in reset

ifr = #10h ; clear interrupt flags

imr = #210h ; Enable HPINT,enable BRINT0

intm = 0 ; all unmasked interrupts are enabled.

bspce = #SPCEval ; programs BSPCE and ABU

axr = #XMTbufAddr ; initializes transmit buffer start address

bkx = #X MTbufSize ; initializes transmit buffer size

arr = #RCVbufAddr ; initializes receive buffer start address

bkr = #RCVbufSize ; initializes receive buffer size

bspc = #(S P C v a l | GO) ; bring buffered serial port out of reset

return ;for transmit and receive because GO=0xC0

; ***************************************************************************

; File: BVECTORS.ASM -> Vector Table for the ‘C54x DSKplus 10.Jul.96

; BSP vectors and Debugger vectors

; TDM vectors just return

; ***************************************************************************

; The vectors in this table can be configured for processing external and

; internal software interrupts. The DSKplus debugger uses four interrupt

; vectors. These are RESET, TRAP2, INT2, and HPIINT.

LTC1403/LTC1403A

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For more information www.linear.com/LTC1403

applications inFormation

; * DO NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER *

; All other vector locations are free to use. When programming always be sure

; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and

; host PC interact. INT2 should normally be masked (IMR(bit 2) = 0) so that the

; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally.

;

.title “Vector Table”

.mmregs

reset goto #80h ;00; RESET * DO NOT MODIFY IF USING DEBUGGER *

nop

nmi return _ enable ;04; non-maskable external interrupt

nop

trap2 goto #88h ;08; trap2 * DO NOT MODIFY IF USING DEBUGGER *

nop

.space 52*16 ;0C-3F: vectors for software interrupts 18-30

int0 return _ enable ;40; external interrupt int0

nop

int1 return _ enable ;44; external interrupt int1

nop

int2 return _ enable ;48; external interrupt int2

nop

tint return _ enable ;4C; internal timer interrupt

nop

brint goto breceive ;50; BSP receive interrupt

nop

bxint goto bsend ;54; BSP transmit interrupt

nop

trint return _ enable ;58; TDM receive interrupt

nop

txint return _ enable ;5C; TDM transmit interrupt

nop

int3 return _ enable ;60; external interrupt int3

nop

hpiint dgoto #0e4h ;64; HPIint * DO NOT MODIFY IF USING DEBUGGER *

nop

.space 24*16 ;68-7 F; reserved area

LTC1403/LTC1403A

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package Description

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

Please refer to http://www.linear.com/product/LTC1403#packaging for the most recent package drawings.

MSOP (MSE) 0213 REV I

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ±0.152

(.193 ±.006)

0.497 ±0.076

(.0196 ±.003)

REF

8910

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ±.0015)

TYP

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.68

(.066)

1.88

(.074)

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

LTC1403/LTC1403A

1403fc

For more information www.linear.com/LTC1403

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision history

REV DATE DESCRIPTION PAGE NUMBER

C 02/17 Updated Timing Characteristics Including tCONV Minimum Conversion Time of 17 Clocks 5, 9, 14, 15

(Revision history begins at Rev C)

LTC1403/LTC1403A

1403fc

For more information www.linear.com/LTC1403

 LINEAR TECHNOLOGY CORPORATION 2007

LT 0217 REV C • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 l FAX: (408) 434-0507 l www.linear.com/LTC1403

relateD parts

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC1608 16-Bit, 500ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD

LTC1604 16-Bit, 333ksps Parallel ADC ±5V Supply, ±2.5V Span, 90dB SINAD

LTC1609 16-Bit, 250ksps Serial ADC 5V, Configurable Bipolar/Unipolar Inputs

LTC1411 14-Bit, 2.5Msps Parallel ADC 5V, Selectable Spans, 80dB SINAD

LTC1414 14-Bit, 2.2Msps Parallel ADC ±5V Supply, ±2.5V Span, 78dB SINAD

LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package

LTC1420 12-Bit, 10Msps Parallel ADC 5V, Selectable Spans, 72dB SINAD

LTC1405 12-Bit, 5Msps Parallel ADC 5V, Selectable Spans, 115mW

LTC1412 12-Bit, 3Msps Parallel ADC ±5V Supply, ±2.5V Span, 72dB SINAD

LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span

LTC1864/LTC1865 16-Bit, 250ksps Serial ADC 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package

DACs

LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time

LTC1592 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans

References

1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift

LT1461-2.5 Precision Voltage Reference 0.04% Initial Accuracy, 3ppm Drift

LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift