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LM4808
Low Voltage High Power Audio Power Amplifier
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1FEATURES DESCRIPTION
The LM4808 is a dual audio power amplifier capable
2• WSON, VSSOP, and SOIC Surface Mount of delivering 105mW per channel of continuous
Packaging average power into a 16Ωload with 0.1% (THD+N)
• Switch On/Off Click Suppression from a 5V power supply.
• Excellent Power Supply Ripple Rejection Boomer audio power amplifiers were designed
• Unity-Gain Stable specifically to provide high quality output power with a
minimal amount of external components using
• Minimum External Components surface mount packaging. Since the LM4808 does
not require bootstrap capacitors or snubber networks,
APPLICATIONS it is optimally suited for low-power portable systems.
• Headphone Amplifier The unity-gain stable LM4808 can be configured by
• Personal Computers external gain-setting resistors.
• Portable Electronic Devices
KEY SPECIFICATIONS
• THD+N at 1kHz at 105mW Continuous Average
Output Power Into 16Ω0.1 % (typ)
• THD+N at 1kHz at 70mW Continuous Average
Output Power Into 32Ω0.1 % (typ)
• Output Power at 0.1% THD+N at 1kHz Into 32Ω
70 mW (typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM4808
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Typical Application
*Refer to the APPLICATION INFORMATION section for information concerning proper selection of the input and
output coupling capacitors.
Figure 1. Typical Audio Amplifier Application Circuit
Connection Diagram
Figure 2. Top View
WSON Package
See Package Number NGL0008B
Figure 3. Top View
SOIC & VSSOP Package
See Package Number D0008A, DGK0008A
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)(2)
Supply Voltage 6.0V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD + 0.3V
Power Dissipation (3) Internally limited
ESD Susceptibility (4) 3500V
ESD Susceptibility (5) 250V
Junction Temperature 150°C
Vapor Phase (60 seconds) 215°C
Soldering Information (6) Small Outline Package Infrared (15 seconds) 220°C
θJC (VSSOP) 56°C/W
θJA (VSSOP) 210°C/W
θJC (SOIC) 35°C/W
Thermal Resistance θJA (SOIC) 170°C/W
θJC (WSON) 15°C/W
θJA (WSON) 117°C/W (7)
θJA (WSON) 150°C/W (8)
(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature
TA. The maximum allowable power dissipation is P DMAX = (TJMAX −TA) / θJA. For the LM4808, TJMAX = 150°C, and the typical junction-
to-ambient thermal resistance, when board mounted, is 210°C/W for package DGK0008A and 170°C/W for package D0008A.
(4) Human body model, 100 pF discharged through a 1.5 kΩresistor.
(5) Machine Model, 220 pF–240 pF discharged through all pins.
(6) See http://www.ti.com for other methods of soldering surface mount devices.
(7) The given θJA is for an LM4808 packaged in an NGL0008B with the Exposed-DAP soldered to a printed circuit board copper pad with an
area equivalent to that of the Exposed-DAP itself.
(8) The given θJA is for an LM4808 packaged in an NGL0008B with the Exposed-DAP not soldered to any printed circuit board copper.
OPERATING RATINGS
Temperature Range TMIN ≤TA≤TMAX −40°C ≤TA≤85°C
Supply Voltage 2.0V ≤VDD ≤5.5V
ELECTRICAL CHARACTERISTICS (1) (2)
The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA= 25°C.
Symbol Parameter Conditions LM4808 Units
(Limits)
Typ (3) Limit (4)
2.0 V (min)
VDD Supply Voltage 5.5 V (max)
IDD Supply Current VIN = 0V, IO= 0A 1.2 3.0 mA (max)
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS (1) (2) (continued)
The following specifications apply for VDD = 5V unless otherwise specified, limits apply to TA= 25°C.
Symbol Parameter Conditions LM4808 Units
(Limits)
Typ (3) Limit (4)
Ptot Total Power Dissipation VIN = 0V, IO= 0A 6 16.5 mW (max)
VOS Input Offset Voltage VIN = 0V 10 50 mV (max)
Ibias Input Bias Current 10 pA
0 V
VCM Common Mode Voltage 4.3 V
GVOpen-Loop Voltage Gain RL= 5kΩ67 dB
Io Max Output Current THD+N < 0.1 % 70 mA
ROOutput Resistance 0.1 Ω
RL= 32Ω, 0.1% THD+N, Min .3
VOOutput Swing V
RL= 32Ω, 0.1% THD+N, Max 4.7
Cb = 1.0µF, Vripple = 100mVPP, f = 89 dB
PSRR Power Supply Rejection Ratio 100Hz
Crosstalk Channel Separation RL= 32Ω75 dB
f = 1 kHz
RL= 16Ω, 0.05 %
VO=3.5VPP (at 0 dB)
THD+N Total Harmonic Distortion + Noise 66 dB
RL= 32Ω, 0.05 %
VO=3.5VPP (at 0 dB) 66 dB
SNR Signal-to-Noise Ratio VO= 3.5Vpp (at 0 dB) 105 dB
fGUnity Gain Frequency Open Loop, RL= 5kΩ5.5 MHz
THD+N = 0.1%, f = 1 kHz
RL= 16Ω105 mW
RL= 32Ω70 60 mW
PoOutput Power THD+N = 10%, f = 1 kHz
RL= 16Ω150 mW
RL= 32Ω90 mW
CIInput Capacitance 3 pF
CLLoad Capacitance 200 pF
SR Slew Rate Unity Gain Inverting 3 V/µs
ELECTRICAL CHARACTERISTICS (1) (2)
The following specifications apply for VDD = 3.3V unless otherwise specified, limits apply to TA= 25°C.
Symbol Parameter Conditions Conditions Units
(Limits)
Typ (3) Limit (4)
IDD Supply Current VIN = 0V, IO= 0A 1.0 mA (max)
VOS Input Offset Voltage VIN = 0V 7 mV (max)
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
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ELECTRICAL CHARACTERISTICS (1) (2) (continued)
The following specifications apply for VDD = 3.3V unless otherwise specified, limits apply to TA= 25°C.
Symbol Parameter Conditions Conditions Units
(Limits)
Typ (3) Limit (4)
THD+N = 0.1%, f = 1 kHz
RL= 16Ω40 mW
RL= 32Ω28 mW
PoOutput Power THD+N = 10%, f = 1 kHz
RL= 16Ω56 mW
RL= 32Ω38 mW
ELECTRICAL CHARACTERISTICS (1) (2)
The following specifications apply for VDD = 2.6V unless otherwise specified, limits apply to TA= 25°C.
Symbol Parameter Conditions Conditions Units
(Limits)
Typ (3) Limit (4)
IDD Supply Current VIN = 0V, IO= 0A 0.9 mA (max)
VOS Input Offset Voltage VIN = 0V 5 mV (max)
THD+N = 0.1%, f = 1 kHz
RL= 16Ω20 mW
RL= 32Ω16 mW
PoOutput Power THD+N = 10%, f = 1 kHz
RL= 16Ω31 mW
RL= 32Ω22 mW
(1) All voltages are measured with respect to the ground pin, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Tested limits are specified to AOQL (Average Outgoing Quality Level). Datasheet min/max specification limits are specified by design,
test, or statistical analysis.
EXTERNAL COMPONENTS DESCRIPTION
(Figure 1)
Components Functional Description
The inverting input resistance, along with Rf, set the closed-loop gain. Ri, along with Ci, form a high pass filter with fc=
1. Ri1/(2πRiCi).
The input coupling capacitor blocks DC voltage at the amplifier's input terminals. Ci, along with Ri, create a highpass filter
2. Ciwith fC= 1/(2πRiCi). Refer to the section, SELECTING PROPER EXTERNAL COMPONENTS, for an explanation of
determining the value of Ci.
3. RfThe feedback resistance, along with Ri, set closed-loop gain.
This is the supply bypass capacitor. It provides power supply filtering. Refer to the APPLICATION INFORMATION section
4. CSfor proper placement and selection of the supply bypass capacitor.
This is the half-supply bypass pin capacitor. It provides half-supply filtering. Refer to the section, SELECTING PROPER
5. CBEXTERNAL COMPONENTS, for information concerning proper placement and selection of CB.
This is the output coupling capacitor. It blocks the DC voltage at the amplifier's output and forms a high pass filter with RLat
6. COfO= 1/(2πRLCO)
7. RBThis is the resistor which forms a voltage divider that provides 1/2 VDD to the non-inverting input of the amplifier.
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TYPICAL PERFORMANCE CHARACTERISTICS
THD+N vs Frequency THD+N vs Frequency
Figure 4. Figure 5.
THD+N vs Frequency THD+N vs Frequency
Figure 6. Figure 7.
THD+N vs Frequency THD+N vs Frequency
Figure 8. Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Frequency THD+N vs Frequency
Figure 10. Figure 11.
THD+N vs Frequency THD+N vs Frequency
Figure 12. Figure 13.
THD+N vs Output Power THD+N vs Output Power
Figure 14. Figure 15.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power THD+N vs Output Power
Figure 16. Figure 17.
THD+N vs Output Power THD+N vs Output Power
Figure 18. Figure 19.
THD+N vs Output Power THD+N vs Output Power
Figure 20. Figure 21.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
THD+N vs Output Power Output Power vs Load Resistance
Figure 22. Figure 23.
Output Power vs Load Resistance Output Power vs Load Resistance
Figure 24. Figure 25.
Output Power vs Supply Voltage Output Power vs Power Supply
Figure 26. Figure 27.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Output Power vs Power Supply Clipping Voltage vs Supply Voltage
Figure 28. Figure 29.
Power Dissipation vs Output Power Power Dissipation vs Output Power
Figure 30. Figure 31.
Power Dissipation vs Output Power Channel Separation
Figure 32. Figure 33.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Channel Separation Noise Floor
Figure 34. Figure 35.
Power Supply Rejection Ratio Frequency Response
Figure 36. Figure 37.
Open Loop Frequency Response Open Loop Frequency Response
Figure 38. Figure 39.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Supply Current vs Supply Voltage Frequency Response vs Output Capacitor Size
Figure 40. Figure 41.
Frequency Response vs Output Capacitor Size Frequency Response vs Output Capacitor Size
Figure 42. Figure 43.
Typical Application Frequency Response Typical Application Frequency Response
Figure 44. Figure 45.
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APPLICATION INFORMATION
EXPOSED-DAP PACKAGE PCB MOUNTING CONSIDERATION
The LM4808's exposed-dap (die attach paddle) package (LD) provides a low thermal resistance between the die
and the PCB to which the part is mounted and soldered. This allows rapid heat transfer from the die to the
surrounding PCB copper traces, ground plane, and surrounding air.
The LD package should have its DAP soldered to a copper pad on the PCB. The DAP's PCB copper pad may be
connected to a large plane of continuous unbroken copper. This plane forms a thermal mass, heat sink, and
radiation area.
However, since the LM4808 is designed for headphone applications, connecting a copper plane to the DAP's
PCB copper pad is not required. The LM4808's Power Dissipation vs Output Power Curve in the TYPICAL
PERFORMANCE CHARACTERISTICS shows that the maximum power dissipated is just 45mW per amplifier
with a 5V power supply and a 32Ωload.
Further detailed and specific information concerning PCB layout, fabrication, and mounting an LD (WSON)
package is available from Texas Instruments' Package Engineering Group under application note AN-1187
(literature number SNOA401).
POWER DISSIPATION
Power dissipation is a major concern when using any power amplifier and must be thoroughly understood to
ensure a successful design. Equation 1 states the maximum power dissipation point for a single-ended amplifier
operating at a given supply voltage and driving a specified output load.
PDMAX = (VDD)2/ (2π2RL) (1)
Since the LM4808 has two operational amplifiers in one package, the maximum internal power dissipation point
is twice that of the number which results from Equation 1. Even with the large internal power dissipation, the
LM4808 does not require heat sinking over a large range of ambient temperature. From Equation 1, assuming a
5V power supply and a 32Ωload, the maximum power dissipation point is 40mW per amplifier. Thus the
maximum package dissipation point is 80mW. The maximum power dissipation point obtained must not be
greater than the power dissipation that results from Equation 2:
PDMAX = (TJMAX −TA) / θJA
where
•θJA = 210°C/W for package DGK0008A
• TJMAX = 150°C for the LM4808 (2)
Depending on the ambient temperature, TA, of the system surroundings, Equation 2 can be used to find the
maximum internal power dissipation supported by the IC packaging. If the result of Equation 1 is greater than
that of Equation 2, then either the supply voltage must be decreased, the load impedance increased or TA
reduced. For the typical application of a 5V power supply, with a 32Ωload, the maximum ambient temperature
possible without violating the maximum junction temperature is approximately 133.2°C provided that device
operation is around the maximum power dissipation point. Power dissipation is a function of output power and
thus, if typical operation is not around the maximum power dissipation point, the ambient temperature may be
increased accordingly. Refer to the TYPICAL PERFORMANCE CHARACTERISTICS curves for power
dissipation information for lower output powers.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 0.1µF supply bypass capacitor, CS, connected
between the LM4808's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4808's power supply pin and ground as short as possible. Connecting a 1.0µF capacitor, CB,
between the IN A(+) / IN B(+) node and ground improves the internal bias voltage's stability and improves the
amplifier's PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large,
however, increases the amplifier's turn-on time. The selection of bypass capacitor values, especially CB, depends
on desired PSRR requirements, click and pop performance (as explained in the section, SELECTING PROPER
EXTERNAL COMPONENTS), system cost, and size constraints.
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SELECTING PROPER EXTERNAL COMPONENTS
Optimizing the LM4808's performance requires properly selecting external components. Though the LM4808
operates well when using external components with wide tolerances, best performance is achieved by optimizing
component values.
The LM4808 is unity-gain stable, giving a designer maximum design flexibility. The gain should be set to no more
than a given application requires. This allows the amplifier to achieve minimum THD+N and maximum signal-to-
noise ratio. These parameters are compromised as the closed-loop gain increases. However, low gain demands
input signals with greater voltage swings to achieve maximum output power. Fortunately, many signal sources
such as audio CODECs have outputs of 1VRMS (2.83VP-P). Please refer to the AUDIO POWER AMPLIFIER
DESIGN section for more information on selecting the proper gain.
Input and Output Capacitor Value Selection
Amplifying the lowest audio frequencies requires high value input and output coupling capacitors (CIand COin
Figure 1). A high value capacitor can be expensive and may compromise space efficiency in portable designs. In
many cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little
improvement by using high value input and output capacitors.
Besides affecting system cost and size, Cihas an effect on the LM4808's click and pop performance. The
magnitude of the pop is directly proportional to the input capacitor's size. Thus, pops can be minimized by
selecting an input capacitor value that is no higher than necessary to meet the desired −3dB frequency.
As shown in Figure 1, the input resistor, RIand the input capacitor, CI, produce a −3dB high pass filter cutoff
frequency that is found using Equation 3. In addition, the output load RL, and the output capacitor CO, produce a
-3db high pass filter cutoff frequency defined by Equation 4.
fI-3db=1/2πRICI(3)
fO-3db=1/2πRLCO(4)
Also, careful consideration must be taken in selecting a certain type of capacitor to be used in the system.
Different types of capacitors (tantalum, electrolytic, ceramic) have unique performance characteristics and may
affect overall system performance.
Bypass Capacitor Value
Besides minimizing the input capacitor size, careful consideration should be paid to the value of the bypass
capacitor, CB. Since CBdetermines how fast the LM4808 settles to quiescent operation, its value is critical when
minimizing turn-on pops. The slower the LM4808's outputs ramp to their quiescent DC voltage (nominally 1/2
VDD), the smaller the turn-on pop. Choosing CBequal to 1.0µF or larger, will minimize turn-on pops. As discussed
above, choosing Cino larger than necessary for the desired bandwidth helps minimize clicks and pops.
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AUDIO POWER AMPLIFIER DESIGN
Design a Dual 70mW/32ΩAudio Amplifier
Given:
Power Output 70mW
Load Impedance 32Ω
Input Level 1Vrms (max)
Input Impedance 20kΩ
Bandwidth 100Hz–20kHz ± 0.50dB
The design begins by specifying the minimum supply voltage necessary to obtain the specified output power.
One way to find the minimum supply voltage is to use the Output Power vs Supply Voltage curve in the TYPICAL
PERFORMANCE CHARACTERISTICS section. Another way, using Equation 5, is to calculate the peak output
voltage necessary to achieve the desired output power for a given load impedance. To account for the amplifier's
dropout voltage, two additional voltages, based on the Dropout Voltage vs Supply Voltage in the TYPICAL
PERFORMANCE CHARACTERISTICS curves, must be added to the result obtained by Equation 5. For a single-
ended application, the result is Equation 6.
(5)
VDD ≥(2VOPEAK + (VODTOP + VODBOT)) (6)
The Output Power vs Supply Voltage graph for a 32Ωload indicates a minimum supply voltage of 4.8V. This is
easily met by the commonly used 5V supply voltage. The additional voltage creates the benefit of headroom,
allowing the LM4808 to produce peak output power in excess of 70mW without clipping or other audible
distortion. The choice of supply voltage must also not create a situation that violates maximum power dissipation
as explained above in the POWER DISSIPATION section. Remember that the maximum power dissipation point
from Equation 1 must be multiplied by two since there are two independent amplifiers inside the package. Once
the power dissipation equations have been addressed, the required gain can be determined from Equation 7.
(7)
Thus, a minimum gain of 1.497 allows the LM4808 to reach full output swing and maintain low noise and THD+N
perfromance. For this example, let AV=1.5.
The amplifiers overall gain is set using the input (Ri) and feedback (Rf) resistors. With the desired input
impedance set at 20kΩ, the feedback resistor is found using Equation 8.
AV= Rf/Ri(8)
The value of Rfis 30kΩ.
The last step in this design is setting the amplifier's −3db frequency bandwidth. To achieve the desired ±0.25dB
pass band magnitude variation limit, the low frequency response must extend to at lease one−fifth the lower
bandwidth limit and the high frequency response must extend to at least five times the upper bandwidth limit. The
gain variation for both response limits is 0.17dB, well within the ±0.25dB desired limit. The results are an
fL= 100Hz/5 = 20Hz (9)
and afH= 20kHz∗5 = 100kHz (10)
As stated in the EXTERNAL COMPONENTS DESCRIPTION section, both Riin conjunction with Ci, and Cowith
RL, create first order highpass filters. Thus to obtain the desired low frequency response of 100Hz within ±0.5dB,
both poles must be taken into consideration. The combination of two single order filters at the same frequency
forms a second order response. This results in a signal which is down 0.34dB at five times away from the single
order filter −3dB point. Thus, a frequency of 20Hz is used in the following equations to ensure that the response
is better than 0.5dB down at 100Hz.
Ci≥1 / (2π* 20 kΩ* 20 Hz) = 0.397µF; use 0.39µF.
Co≥1 / (2π* 32Ω* 20 Hz) = 249µF; use 330µF.
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The high frequency pole is determined by the product of the desired high frequency pole, fH, and the closed-loop
gain, AV. With a closed-loop gain of 1.5 and fH= 100kHz, the resulting GBWP = 150kHz which is much smaller
than the LM4808's GBWP of 900kHz. This figure displays that if a designer has a need to design an amplifier
with a higher gain, the LM4808 can still be used without running into bandwidth limitations.
Demonstration Board Layout
Figure 46. Recommended SO PC Board Layout: Figure 47. Recommended LD PC Board Layout:
Top Silkscreen Top Silkscreen
Figure 48. Recommended SOIC PC Board Layout: Figure 49. Recommended LD PC Board Layout:
Top Layer Top Layer
Figure 50. Recommended SOIC PC Board Layout: Figure 51. Recommended LD PC Board Layout:
Bottom Layer Bottom Layer
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REVISION HISTORY
Changes from Revision C (May 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 16
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PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM4808M/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LM48
08M
LM4808MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 G08
LM4808MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 G08
LM4808MX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN | CU SN Level-1-260C-UNLIM -40 to 85 LM48
08M
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4808MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM4808MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM4808MX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4808MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LM4808MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LM4808MX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-May-2013
Pack Materials-Page 2
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