IS61LP12832-166B - Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI®

This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Linear burst sequence control using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

• Single +3.3V, +10%, –5% power supply

• Power-down snooze mode

• 2.5V I/O supply voltage

• Industrial temperature available

DESCRIPTION

The ISSI IS61LP12832 and IS61LP12836 is a high-speed

synchronous static RAM designed to provide a burstable,

high-performance memory for high speed networking and

communication applications. It is organized as 131,072

words by 32 bits and 36 bits, fabricated with ISSI's

advanced CMOS technology. The device integrates a 2-bit

burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be from

one to four bytes wide as controlled by the write control

inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQa, BW2 controls DQb, BW3 controls

DQc, BW4 controls DQd, conditioned by BWE being

LOW. A LOW on GW input would cause all bytes to be

written.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

PRELIMINARY INFORMATION

SEPTEMBER 2001

FAST ACCESS TIME

Symbol Parameter -200 -166 -133 Units

tKQ Clock Access Time 3.1 3.5 4 ns

tKC Cycle Time 5 6 7.5 ns

Frequency 200 166 133 MHz

128K x 32, 128K x 36 SYNCHRONOUS

PIPELINED STATIC RAM

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

BLOCK DIAGRAM

BINARY

COUNTER

A16-A0

BW1

CLR

CLK Q0

MODE

A0'

A1 A1'

CLK

ADV

ADSC

ADSP

15 17

ADDRESS

CLK

DQd

BYTE WRITE

REGISTERS

CLK

DQc

BYTE WRITE

REGISTERS

CLK

DQb

BYTE WRITE

REGISTERS

CLK

DQa

BYTE WRITE

REGISTERS

CLK

ENABLE

CLK

ENABLE

DELAY

CLK

BWE

BW4

CE2

BW2

BW3

128K x 32/128K x 36

MEMORY ARRAY

32 or 36

INPUT

REGISTERS

CLK

OUTPUT

REGISTERS

CLK

32 or 36

432 or 36

DQ[31:0]

DQ[35:0]

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

PIN CONFIGURATION

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

A2-A16 Synchronous Address Inputs

CLK Synchronous Clock

ADSP Synchronous Processor Address

Status

ADSC Synchronous Controller Address

Status

ADV Synchronous Burst Address Advance

BW1-BW4 Individual Byte Write Enable

BWE Synchronous Byte Write Enable

GW Synchronous Global Write Enable

CE, CE2, CE2 Synchronous Chip Enable

OE Output Enable

DQa-DQd Synchronous Data Input/Output

MODE Burst Sequence Mode Selection

VCC +3.3V Power Supply

GND Ground

VCCQ Isolated Output Buffer Supply: 2.5V

ZZ Snooze Enable

VCCQ

DQc1

DQc2

VCCQ

DQc5

DQc7

VCCQ

DQd1

DQd4

VCCQ

DQd6

DQd8

VCCQ

CE2

DQc3

DQc4

DQc6

DQc8

VCC

DQd2

DQd3

DQd5

DQd7

GND

BW3

GND

BW4

GND

MODE

A10

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

A11

A12

GND

BW2

GND

BW1

GND

A14

A16

CE2

A15

DQb6

DQb5

DQb4

DQb2

VCC

DQa7

DQa5

DQa4

DQa3

A13

VCCQ

DQb8

DQb7

VCCQ

DQb3

DQb1

VCCQ

DQa8

DQa6

VCCQ

DQa2

DQa1

VCCQ

1 2 3 4 5 6 7

DQb8

DQb7

VCCQ

GND

DQb6

DQb5

DQb4

DQb3

GND

VCCQ

DQb2

DQb1

GND

VCC

DQa8

DQa7

VCCQ

GND

DQa6

DQa5

DQa4

DQa3

GND

VCCQ

DQa2

DQa1

CE2

BW4

BW3

BW2

BW1

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQc1

DQc2

VCCQ

GND

DQc3

DQc4

DQc5

DQc6

GND

VCCQ

DQc7

DQc8

VCC

GND

DQd1

DQd2

VCCQ

GND

DQd3

DQd4

DQd5

DQd6

GND

VCCQ

DQd7

DQd8

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

128K x 32

119-pin PBGA (Top View) 100-Pin TQFP

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

PIN CONFIGURATION

PIN DESCRIPTIONS

A0, A1 Synchronous Address Inputs. These

pins must tied to the two LSBs of the

address bus.

A16 Synchronous Address Inputs

CLK Synchronous Clock

ADSP Synchronous Processor Address

Status

ADSC Synchronous Controller Address

Status

ADV Synchronous Burst Address Advance

BW1-BW4 Individual Byte Write Enable

BWE Synchronous Byte Write Enable

GW Synchronous Global Write Enable

CE, CE2, CE2 Synchronous Chip Enable

OE Output Enable

DQa-DQd Synchronous Data Input/Output

MODE Burst Sequence Mode Selection

VCC +3.3V Power Supply

GND Ground

VCCQ

Isolated Output Buffer Supply:

2.5V

ZZ Snooze Enable

DQPa-DQPd Parity Data I/O

VCCQ

DQc1

DQc2

VCCQ

DQc5

DQc7

VCCQ

DQd1

DQd4

VCCQ

DQd6

DQd8

VCCQ

CE2

DQPc

DQc3

DQc4

DQc6

DQc8

VCC

DQd2

DQd3

DQd5

DQd7

DQPd

GND

BW3

GND

BW4

GND

MODE

A10

ADSP

ADSC

VCC

ADV

VCC

CLK

BWE

VCC

A11

A12

GND

BW2

GND

BW1

GND

A14

A16

CE2

A15

DQPb

DQb6

DQb5

DQb4

DQb2

VCC

DQa7

DQa5

DQa4

DQa3

DQPa

A13

VCCQ

DQb8

DQb7

VCCQ

DQb3

DQb1

VCCQ

DQa8

DQa6

VCCQ

DQa2

DQa1

VCCQ

1 2 3 4 5 6 7

DQPb

DQb8

DQb7

VCCQ

GND

DQb6

DQb5

DQb4

DQb3

GND

VCCQ

DQb2

DQb1

GND

VCC

DQa8

DQa7

VCCQ

GND

DQa6

DQa5

DQa4

DQa3

GND

VCCQ

DQa2

DQa1

DQPa

CE2

BW4

BW3

BW2

BW1

CE2

VCC

GND

CLK

BWE

ADSC

ADSP

ADV

DQPc

DQc1

DQc2

VCCQ

GND

DQc3

DQc4

DQc5

DQc6

GND

VCCQ

DQc7

DQc8

VCC

GND

DQd1

DQd2

VCCQ

GND

DQd3

DQd4

DQd5

DQd6

GND

VCCQ

DQd7

DQd8

DQPd

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

A16

46 47 48 49 50

128K x 36

119-pin PBGA (Top View) 100-Pin TQFP

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

TRUTH TABLE

Address

Operation Used CE CE2 CE2 ADSP ADSC ADV WRITE OE DQ ZZ

Deselected, Power-down None H X X X L X X X High-Z L

Deselected, Power-down None L X H L X X X X High-Z L

Deselected, Power-down None L L X L X X X X High-Z L

Deselected, Power-down None X X H H L X X X High-Z L

Deselected, Power-down None X L X H L X X X High-Z L

Read Cycle, Begin Burst External L H L L X X X X Q L

Read Cycle, Begin Burst External L H L H L X Read X Q L

Write Cycle, Begin Burst External L H L H L X Write X D L

Read Cycle, Continue Burst Next X X X H H L Read L Q L

Read Cycle, Continue Burst Next X X X H H L Read H High-Z L

Read Cycle, Continue Burst Next H XXXHLRead L Q L

Read Cycle, Continue Burst Next H XXXHLRead H High-Z L

Write Cycle, Continue Burst Next X X X H H L Write X D L

Write Cycle, Continue Burst Next H XXXHLWrite X D L

Read Cycle, Suspend Burst Current X X X H H H Read L Q L

Read Cycle, Suspend Burst Current X X X H H H Read H High-Z L

Read Cycle, Suspend Burst Current H XXXHHRead L Q L

Read Cycle, Suspend Burst Current H XXXHHRead H High-Z L

Write Cycle, Suspend Burst Current X X X H H H Write X D L

Write Cycle, Suspend Burst Current H XXXHHWrite X D L

Snooze Mode —XXXXXXXXHigh-ZH

PARTIAL TRUTH TABLE

Function GW BWE BW1 BW2 BW3 BW4

Read H H XXXX

Read H L HHHH

Write Byte 1 H L L H H H

Write All Bytes H LLLLL

Write All Bytes L XXXXX

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)

External Address 1st Burst Address 2nd Burst Address 3rd Burst Address

A1 A0 A1 A0 A1 A0 A1 A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

LINEAR BURST ADDRESS TABLE (MODE = GND)

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameter Value Unit

TBIAS Temperature Under Bias –40 to +85 °C

TSTG Storage Temperature –55 to +150 °C

PDPower Dissipation 1.6 W

IOUT Output Current (per I/O) 100 mA

VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.5 V

VIN Voltage Relative to GND for –0.5 to VCC + 0.5 V

for Address and Control Inputs

VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V

Notes:

1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-

nent damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

2. This device contains circuitry to protect the inputs against damage due to high static voltages

or electric fields; however, precautions may be taken to avoid application of any voltage higher

than maximum rated voltages to this high-impedance circuit.

3. This device contains circuitry that will ensure the output devices are in High-Z at power up.

0,0

1,0

0,1A1', A0' = 1,1

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

OPERATING RANGE

Range Ambient Temperature VCC VCCQ

Commercial 0°C to +70°C 3.3V, +10%, –5% 2.5V ±5%

Industrial –40°C to +85°C 3.3V, +10%, –5% 2.5V ±5%

POWER SUPPLY CHARACTERISTICS (Over Operating Range)

-200 -166 -133

Symbol Parameter Test Conditions Max. Max. Max. Unit

ICC AC Operating Device Selected, Com. 300 290 230 mA

Supply Current All Inputs = VIL or VIH Ind. 310 300 240 mA

OE = VIH, Vcc = Max.

Cycle Time ≥ tKC min.

ISB Standby Current Device Deselected, Com. 70 70 70 mA

TTL VCC = Max., Ind. 80 80 80 mA

All Inputs = VIH or VIL

CLK Cycle Time ≥ tKC min.

IZZ Power-down Mode ZZ = VCC Com. 15 15 15 mA

Current Clock Running Ind. 20 20 20 mA

All Inputs ≤ GND + 0.2V

or ≥ Vcc – 0.2V

Notes:

1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC.

2. The MODE pin could be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to ≤ GND + 0.2V

or ≥ Vcc – 0.2V.

DC ELECTRICAL CHARACTERISTICS (Over Operating Range)

Symbol Parameter Test Conditions Min. Max. Unit

VOH Output HIGH Voltage IOH = -1.0 mA 2.0 —V

VOL Output LOW Voltage IOL = 1.0 mA —0.4 V

VIH Input HIGH Voltage 1.7 VCC + 0.3 V

VIL Input LOW Voltage –0.3 0.7 V

ILI Input Leakage Current GND ≤ VIN ≤ VCC –11 µA

ILO Output Leakage Current GND ≤ VOUT ≤ VCCQ,–11 µA

Outputs disabled

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

CAPACITANCE(1,2)

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Input/Output Capacitance VOUT = 0V 8 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.

2.5V I/O AC TEST CONDITIONS

Parameter Unit

Input Pulse Level for Input Pins 0V to 3.0V

Input Pulse Level for I/O Pins 0V to 2.5V

Input Rise and Fall Times 1.5 ns

Input Timing Reference Level 1.5V

I/O Timing Reference Level 1.25V

Output Load See Figures 1 and 2

= 50Ω

1.25V

50Ω

OUTPUT

1,667 Ω

5 pF

Including

jig and

scope

1,538 Ω

OUTPUT

+2.5V

Figure 1 Figure 2

I/O OUTPUT LOAD EQUIVALENT

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200 -166 -133

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

fMAX(3) Clock Frequency —200 —166 —133 MHz

tKC(3) Cycle Time 5 —6—7.5 —ns

tKH Clock High Time 2 —2.4 —2.8 —ns

tKL(3) Clock Low Time 2 —2.4 —2.8 —ns

tKQ(3) Clock Access Time —3.1 —3.5 —4ns

tKQX(1) Clock High to Output Invalid 1 —1.5 —1.5 —ns

tKQLZ(1,2) Clock High to Output Low-Z 0 —0—0—ns

tKQHZ(1,2) Clock High to Output High-Z 1.5 2.8 1.5 3.5 1.5 3.5 ns

tOEQ(3) Output Enable to Output Valid —2.8 —3.5 —3.8 ns

tOEQX(1) Output Disable to Output Invalid 0 —0—0—ns

tOELZ(1,2) Output Enable to Output Low-Z 0 —0—0—ns

tOEHZ(1,2) Output Disable to Output High-Z 0 2.8 1.5 3.5 1.5 3.8 ns

tAS(3) Address Setup Time 1.5 —1.5 —1.5 —ns

tSS(3) Address Status Setup Time 1.5 —1.5 —1.5 —ns

tWS(3) Write Setup Time 1.5 —1.5 —1.5 —ns

tCES(3) Chip Enable Setup Time 1.5 —1.5 —1.5 —ns

tAVS(3) Address Advance Setup Time 1.5 —1.5 —1.5 —ns

tAH(3) Address Hold Time 0.5 —0.5 —0.5 —ns

tSH(3) Address Status Hold Time 0.5 —0.5 —0.5 —ns

tWH(3) Write Hold Time 0.5 —0.5 —0.5 —ns

tCEH(3) Chip Enable Hold Time 0.5 —0.5 —0.5 —ns

tAVH(3) Address Advance Hold Time 0.5 —0.5 —0.5 —ns

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

3. Tested with load in Figure 1.

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

READ/WRITE CYCLE TIMING

Single Read

High-Z

DATAOUT

DATAIN

CE2

BW4-BW1

BWE

A16-A0

ADV

ADSC

ADSP

CLK

RD1 RD2

1a 2c 2d 3a

Unselected

Burst Read

tKQX

tKC

tKLtKH

tSS tSH

tAS tAH

tWS tWH

RD3

tCES tCEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

tOEQ

tOEQX

tOELZ

tKQLZ

tKQ

tOEHZ

tKQHZ

ADSC initiate read

ADSP is blocked by CE inactive

tAVH

tAVS

Suspend Burst

Pipelined Read

2a 2b

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

-200 -166 -133

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tKC(1) Cycle Time 5 —6—7—ns

tKH(1) Clock High Time 2.0 —2.4 —2.8 —ns

tKL(1) Clock Low Time 2.0 —2.4 —2.8 —ns

tAS(1) Address Setup Time 1.5 —1.5 —1.5 —ns

tSS(1) Address Status Setup Time 1.5 —1.5 —1.5 —ns

tWS(1) Write Setup Time 1.5 —1.5 —1.5 —ns

tDS(1) Data In Setup Time 1.5 —1.5 —1.5 —ns

tCES(1) Chip Enable Setup Time 1.5 —1.5 —1.5 —ns

tAVS(1) Address Advance Setup Time 1.5 —1.5 —1.5 —ns

tAH(1) Address Hold Time 0.5 —0.5 —0.5 —ns

tSH(1) Address Status Hold Time 0.5 —0.5 —0.5 —ns

tDH(1) Data In Hold Time 0.5 —0.5 —0.5 —ns

tWH(1) Write Hold Time 0.5 —0.5 —0.5 —ns

tCEH(1) Chip Enable Hold Time 0.5 —0.5 —0.5 —ns

tAVH(1) Address Advance Hold Time 0.5 —0.5 —0.5 —ns

Note:

1. Tested with load in Figure 1.

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

WRITE CYCLE TIMING

Single Write

DATAOUT

DATAIN

CE2

BW4-BW1

BWE

A16-A0

ADV

ADSC

ADSP

CLK

WR1 WR2

Unselected

Burst Write

WR3

CES

CEH

CES

CEH

CES

CEH

CE2 and CE2 only sampled with ADSP or ADSC

CE Masks ADSP

Unselected with CE2

ADSC initiate Write

ADSP is blocked by CE inactive

AVH

AVS

ADV must be inactive for ADSP Write

WR1 WR2

WR3

High-Z

High-Z 1a 3a

BW4-BW1 only are applied to first cycle of WR2

Write

2c 2d2b2a

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS

(Over Operating Range)

-200 -166 -133

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tKC(3) Cycle Time 5 —6—7.5 —ns

tKH(3) Clock High Time 2 —2.4 —2.8 —ns

tKL(3) Clock Low Time 2 —2.4 —2.8 —ns

tKQ(3) Clock Access Time —3.1 —3.5 —4ns

tKQX(1) Clock High to Output Invalid 1 —1.5 —1.5 —ns

tKQLZ(1,2) Clock High to Output Low-Z 0 —0—0—ns

tKQHZ(1,2) Clock High to Output High-Z 1.5 2.8 1.5 3.5 1.5 3.5 ns

tOEQ(3) Output Enable to Output Valid —2.8 —3.5 —3.8 ns

tOEQX(1) Output Disable to Output Invalid 0 —0—0—ns

tOELZ(1,2) Output Enable to Output Low-Z 0 —0—0—ns

tOEHZ(1,2) Output Disable to Output High-Z 2 2.8 2 3.5 1.5 3.8 ns

tAS(3) Address Setup Time 1.5 —1.5 —1.5 —ns

tSS(3) Address Status Setup Time 1.5 —1.5 —1.5 —ns

tCES(3) Chip Enable Setup Time 1.5 —1.5 —1.5 —ns

tAH(3) Address Hold Time 0.5 —0.5 —0.5 —ns

tSH(3) Address Status Hold Time 0.5 —0.5 —0.5 —ns

tCEH(3) Chip Enable Hold Time 0.5 —0.5 —0.5 —ns

tZZS ZZ Standby 2 —2—2—cyc

tZZREC ZZ Recovery 2 —2—2—cyc

Notes:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

3. Tested with load in Figure 1.

IS61LP12832

IS61LP12836 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

SNOOZE AND RECOVERY CYCLE TIMING

Single Read

High-Z

DATAOUT

DATAIN

CE2

BW4-BW1

BWE

A16-A0

ADV

ADSC

ADSP

CLK

RD1

Read

Snooze with Data Retention

tKC

tKLtKH

tSS tSH

tAS tAH

RD2

tCES tCEH

tOEQ

tOEQX

tOELZ

tKQLZ

tKQ

tOEHZ

tKQX

tKQHZ

tZZS tZZREC

Integrated Silicon Solution, Inc. — 1-800-379-4774

PRELIMINARY INFORMATION Rev. 00B

09/25/01

IS61LP12832

IS61LP12836 ISSI

Commercial Range: 0°C to +70°C

Speed Order Part Number Package

200 MHz IS61LP12836-200TQ TQFP

IS61LP12836-200B PBGA

166 MHz IS61LP12836-166TQ TQFP

IS61LP12836-166B PBGA

133MHz IS61LP12836-133TQ TQFP

IS61LP12836-133B PBGA

Industrial Range: –40°C to +85°C

Speed Order Part Number Package

200 MHz IS61LP12836-200TQI TQFP

IS61LP12836-200BI PBGA

166 MHz IS61LP12836-166TQI TQFP

IS61LP12836-166BI PBGA

133 MHz IS61LP12836-133TQI TQFP

IS61LP12836-133BI PBGA

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774

Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

ORDERING INFORMATION

Commercial Range: 0°C to +70°C

Speed Order Part Number Package

200 MHz IS61LP12832-200TQ TQFP

IS61LP12832-200B PBGA

166 MHz IS61LP12832-166TQ TQFP

IS61LP12832-166B PBGA

133 MHz IS61LP12832-133TQ TQFP

IS61LP12832-133B PBGA

Industrial Range: –40°C to +85°C

Speed Order Part Number Package

200 MHz IS61LP12832-200TQI TQFP

IS61LP12832-200BI PBGA

166 MHz IS61LP12832-166TQI TQFP

IS61LP12832-166BI PBGA

133 MHz IS61LP12832-133TQI TQFP

IS61LP12832-133BI PBGA