T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 1 /42 PROJECT SPACE GENERAL TITLE INTEGRATED CIRCUIT, SILICON MONOLITHIC CMOS 16 BITS ERROR DETECTION AND CORRECTION UNIT BASED ON TYPE 29C516 E Page 1 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 2 /42 Page 2 DOCUMENTATION CHANGE NOTICE Rev. Letter Rev. Date Issue 1 Rev A Reference CHANGE Item New document 18/12/97 Amendment of fig 2(b), page 11 Correction of para.4.5.3 page 21 (component number) Amendment of Table 4, page 35 Amendment of table 7, page 41 Rev B 9/01/98 Amendment of para.4.2.2 page 20 Amendment of figure 5 page 37 Amendment of Notes of Table 6, page 39 Amendment of figure 6 page 40 Amendment of Table 7, page 41 Rev C 23/12/99 Amendment of Table 4, page 35 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 3 /42 Page 3 TABLE OF CONTENTS Page 1 GENERAL 6 6 1.1. Scope 6 1.2. Type Variants 6 1.3. Maximum Ratings 6 1.4. Parameter Derating Information 6 1.5. Physical Dimensions 6 1.6. Pin Assignment 6 1.7. Truth Table/Instruction set/ Programming procedure 6 1.8. Circuits Description 6 1.9. Functional Diagram 6 1.10. Handling Precautions (for information only) 6 1.11. Input Protection Network 6 1.12. Bondind diagram 6 2. APPLICABLE DOCUMENTS 18 3 TERMS, DEFINITIONS, ABBREVIATIONS, SYMBOLS AND UNITS 18 4. REQUIREMENTS 20 4.1. General 20 4.2. Deviations from ESA / SCC Generic Specification N 9000 20 4.2.1. Deviations from Special In-Process Controls 20 4.2.2. Deviations from Final Productions Tests (Charts II) 20 4.2.3. Deviations from Burn-in Tests (Chart III) 20 4.2.4. Deviations from Qualification, Environmental and Endurance Test (Chart IV) 20 4.2.5. Deviations from Lot Acceptance Tests (Chart V) 20 4.3. Mechanical Requirements 20 4.3.1. Dimension Check 20 4.3.2. Weight 20 4.4. Material and Finishes 20 4.4.1. Case 20 4.4.2. lead Material and finish 21 4.4.3. Technology 21 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 4 /42 Page 4 4.4.4. Die Attachment 21 4.5. Marking 21 4.5.1. General 21 4.5.2. Lead Identification 21 4.5.3. The Component Number 21 4.5.4. Traceability Information 22 4.6. Electrical Measurements 22 4.6.1. Electrical Measurements at Room Temperature 22 4.6.2. Electrical Measurements at High and Low Temperature 22 4.6.3. Circuits for Electrical Measurements 22 4.7. Burn-in Tests 22 4.7.1. Parameter Drift Values 22 4.7.2. Conditions for Power Burn-in 22 4.7.3. Electrical Circuits for Power Burn-in 22 4.8. Environmental and Endurance Tests 38 4.8.1. Electrical Measurements at Completion of Environmental Tests 38 4.8.2. Electrical Measurements at Intermediate Point during Endurance Tests 38 4.8.3. Electrical Measurements on Completion of Endurance Tests 38 4.8.4. Conditions for Operating Life-Tests 38 4.8.5. Electrical Circuits for Operating Life-Tests 38 4.8.6. Condition For High Temperature Storage Test 38 4.9. Total Dose irradiation Testing 38 4.9.1. Application 38 4.9.2. Bias Condition 38 4.9.3. Electrical Measurements 38 TABLES 1 (a) Type Variants 7 1 (b) Maximum Ratings 7 1 (c) Dynamic electrical characteristics 8 2 Electrical measurements at room Temperature - dc Parameters Electrical measurements at room Temperature - ac Parameters 23 24 Electrical Measurements at High and Low Temperature - dc Parameters 26 Electrical Measurements at High and Low Temperature - ac Parameters 27 4 Parameter Drift Values 35 5 Conditions for Power Burn-in and Operating Life-Test 36 3 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 5 /42 Page 5 6 Electrical measurements at Intermediate Points and on Completion of Endurance Testing 39 7 Electrical measurements During and on Completion of Irradiation Testing 41 FIGURES 1 Parameter Derating Information 2 Physical Dimensions 10 3(a) Pin Assignment 13 3(b) Functional diagram 14 3(c) Input / Output Protection Network 15 3(d) Bonding Diagram 16 4 Circuits for Electrical Measurements 28 5 Electrical Circuit for Power Burn-in and Operating Life-Test 37 6 Bias Conditions for Irradiation Testing 40 9 APPENDICES (Applicable to Specific Manufacturers only) 'A' AGREED DEVIATION FOR MATRA MHS (F) 42 T EM I C Semiconductors 1 GENERAL 1.1 SCOPE Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 6 /42 Page 6 This specification details the ratings, physical and electrical characteristics, tests and inspection data for a CMOS monolithic 16 bits flow-through Error Detection And Correction circuit based on type 29C516E. It shall be read in conjunction with ESA/SCC Generic Specification N9000, the requirements of which are supplemented herein. 1.2 TYPE VARIANTS Variants of the basic type integrated circuits specified herein , which are also covered by this specification, are given in Table 1(a). 1.3 MAXIMUM RATINGS The maximum ratings, which shall not exceeded at any time during use or storage, applicable to the integrated circuits specified herein, are scheduled in Table 1(b). 1.4 PARAMETER DERATING INFORMATION As per Figure 1. Parameters are specified at room temperature in Table 2 . in Table 3 parameters are specified over the full temperature range : -55C to +125C. 1.5 PHYSICAL DIMENSIONS As per Figure 2. 1.6 PIN ASSIGNMENT As per Figure 3(a). 1.7 TRUTH TABLE Not applicable 1.8 CIRCUITS DESCRIPTION Not applicable 1.9 FUNCTIONAL DIAGRAM As per Figure 3(b). 1.10 HANDLING PRECAUTIONS (FOR INFORMATION ONLY) These devices are susceptible to damage by electrostatic discharge. Therefore, suitable precaution shall be taken for protection during all phases of manufacture, testing, packaging, shipment and any handling. These components are categorised as Class 1 with Minimum Critical Path Failure Voltage of 1000 Volts. 1.11 INPUT PROTECTION NETWORKS ESD protection shall be incorporated into each input as shown in figure 3(c) 1.12 BONDING DIAGRAM As per figure 3(d) T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 7 /42 Page 7 TABLE 1(a) COMPONENT TYPE VARIANTS VARIANT FUNCTION CASE LEAD MATERIAL AND/OR FINISH 1 EDAC 16 MQFPF 100 (flats leads) G2 2 EDAC 16 MQFPL 100 (L leads) G2 TABLE 1(b) - MAXIMUM RATINGS (Note 1) N CHARACTERISTICS SYMBOL MAXIMUM RATING 1 Supply voltage VDD -0.5 to 2 Input voltage range VIN -0.5 to VDD+0.5 3 Input Current per signal pin per power pin IIN -10 -50 4 Output short circuit current VOUT = VDD VOUT = GND IOS to to +7.0 +10 +50 UNIT NOTE V 2 V 2.3 mAdc mAdc 5 + 80 - 75 300 mAdc mAdc 5 Soldering temperature TSOL 6 Storage Temperature TSTG 7 Device Power Dissipation PD 8 Operating Supply Voltage VDD 4.5 to 5.5 V 9 Operating Temperature (Ambient) TOP -55 to 125 C 10 11 Junction Temperature Max. Thermal Resistance TJMAX RTJC -65 to 150 1.8 175 27 C 4 C W 6 C C/W NOTES 1] Absolute maximum ratings : Stresses exceeding those listed as absolute maximum rating may cause permanent damage to the device. Functional performance for extend periods at the absolute maximum ratings may adversely affect device reliability. 2] All voltage values are with respect to VSS (Ground). 3] VDD+0.5V shall not exceed +7.0V. 4] Duration 10 seconds maximum at a distance of not less than 1.6 mm from the package. 5] The maximum output current of any single output in short condition for a maximum duration of 1 second. 6] PD = (TJMAX - TOP)/RTJC . This value represent the maximum device power dissipation , The real power dissipation could be far less than this maximum value . T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 8 /42 Page 8 TABLE 1(C) DYNAMIC ELECTRICAL CHARACTERISTICS PARAMETER CONDITION Idd + Idd2 Operating Current (Array + buffers) MIN NOM MAX UNIT F = 10 MHz Sim n1, first 1000 test vectors 20 mA tr,tf Input rise time and fall time (Except Schmitt trigger and clock inputs) 10% to 90% 500 ns tt Output transition BUF 10% to 90% CL = 50 pF 5 ns Timing variations versus temperature and voltage are given in Figure 1. The following table shows the typical buffer propagation delay variation versus capacitive load of the figures given in table 2(b) and 3(b). Output buffers of output and I/O pins are specified in paragraph 3 (Signal definitions). Measurements according to applicable MIL STD 883 test method, see Tables 2(b) and 3(b). BUFFER SYMBOL CAPACITIVE LOAD BUF Tplh / pF 2.6 ns / 100 pF Tphl / pF 1.9 ns / 100 pF T EM I C Semiconductors FIGURE 1 Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 9 /42 TIMING VARIATIONS VERSUS TEMPERATURE AND VOLTAGE Page 9 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 10 /42 FIGURE 2(a) PHYSICAL DIMENSIONS 100-PIN MULTILAYER QUAD FLAT PACK (MQFPF) Page 10 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 11 /42 FIGURE 2(b) PHYSICAL DIMENSIONS 100-PIN MULTILAYER QUAD FLAT PACK (MQFPL) Page 11 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 12 /42 Page 12 STANDARD NOTES FOR CERQUAD PACK 1/ THE CONTROLLING DIMENSION IS THE INCH. 2/ UNLESS OTHERWISE SPECIFIED, A MINIMUM CLEARANCE OF .015 INCH (0.381 mm) SHALL BE MAINTENED BETWEEN ALL METALLIZED FEATURES (E.G., LID, TERMINALS, THERMAL PADS, ETC..). 3/ DIMENSIONS "A" CONTROLS THE OVERALL PACKAGE HEIGHT. 4/ THIS DIMENSION ALLOWS FOR PACKAGE EDGE ANOMALIES CAUSED BY MATERIAL PROTUSIONS, SUCH AS ROUGH CERAMIC, MISSALIGNED CERAMIC LAYERS AND LIDS, MINESCUS, AND GLASS OVERRUN. 5/ THE CORNER SHAPE (SQUARE, NOTCH, RADIUS, ETC...) MAY VARY AT THE MANUFACTURER'S OPTION, FROM THAT SHOWN ON THE DRAWING. 6/ DIMENSION "L" MEASURED BETWEEN : * INTERSECTION OF LINE TANGENT TO REAR SIDE OF FOOT AND PERPENDICULAR LINE TANGENT TO BOTTOM END OF FOOT EXTREMITY. * AND FOOT EXTREMITY . 7/ DIMENSIONS "D1/E1" DEFINE MAX. CERAMIC BODY DIMENSIONS INCLUDING MISMATCH OF CERAMIC LAYERS. 8/ DIMENSIONS "D1/E1" INCLUDE LID TO PACKAGE MISALI GNEMENT 9/ DATUM "C" IS REFERENCED AT THE POINT OF LEAD EXIT FROM THE PACKAGE EXTREMITY T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 13 /42 FIGURE 3(a) PIN ASSIGNMENT Page 13 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 14 /42 FIGURE 3(b) FONCTIONAL DIAGRAM Page 14 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 15 /42 Page 15 FIGURE 3(c) INPUT/ OUTPUT PROTECTION NETWORK EQUIVALENT OF EACH OUTPUT EQUIVALENT OF EACH INPUT VDD R = 900 R = 900 PAD PAD GND T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 16 /42 FIGURE 3(d) - BONDING DIAGRAM MQFPF 100 Page 16 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 17 /42 FIGURE 3(d) (Continued) - BONDING DIAGRAM MQFPL 100 Page 17 T EM I C Document number MHS/SCC 021 Semiconductors 2 Date Issue 23/12/1999 Rev C Rev C 18 /42 Page 18 APPLICABLE DOCUMENTS The following documents forms are part of thisspecification and shall be read in conjunction with it : (a) ESA / SCC Generic Specification N 9000 for Integrated Circuits. (b) MIL-STD-883 Test Methods and Procedures for Micro-electronics. (c) ESA/SCC Basic Specification N22900. Total dose Steady-state irradiation test method. (d) Test Program (Sentry 15),T65TA2 for HiRel (level B and C) and T65TA1 for engineering models (EM, -2) The issues and revisions of applicable documents that apply are those that are validat the date of the purchase order. In case of confict between purchase order and specification, the requirements in the purchase order shall have precedence. 3 TERMS, DEFINITIONS, ABBREVIATIONS , SYMBOLS AND UNITS For the purpose of this specification, the terms, definitions, abbreviations, symbols and units mentioned in ESA / SCC Basic Specification N 21300 and N 21390 shall be applied. In addition, the following abbreviations are used : Signal name Pin Type Active state Description U1D(15:0) 28, 33-35, 37-40, 42-45, 47-49, 53 I/O, BUF High User 1 Data bus U2D(15:0) 5-8, 10-13, 15-18, 20-23 I/O, BUF High User 2 Data bus MD(15:0) 59-62, 64-67, 69-72, 74-77 I/O, BUF High Memory Data bus MC(7:0) 83, 86, 88-91 I/O, BUF High Memory Check-bit bus R/W1N 55 I High/Low User 1 Read/Write signal EN1N 56 I Low User 1 Output Enable M1N 57 I Low User 1 Memory Select R/W2N 99 I High/Low User 2 Read/Write signal EN2N 94 I Low User 2 Output Enable M2N 3 I Low User 2 Memory Select T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 19 /42 Page 19 Signal name Pin Type Active state Description TN 96 I High/Low Transfer : Select the data path to be used. If this signal is high the EDAC accesses the memory, ant if it is low it accesses the Transfer buffer U2/U1N 95 I High/Low Selects who is the master of User1 and User 2. The Master is responsible for applying R/WxN, MxN and ENxN signals in a correct way. CORRECT 98 I High Selects CORRECTION mode. If Low, the EDAC is in DETECT mode. SYCHN 97 I Low Selects the SYndrome bits (high byte) and the CHeck bits (low byte) to be driven on the selected user data bus. N22 27 I High When active the EDAC uses six check bits, when inactive the EDAC uses eight check bits in memory read. CERRN 26 O, BUF Low Correctable error flag. NCERRN 25 O, BUF Low Uncorrectable error flag. VCCB (VDD) 9, 19, 32, 41, 54, 63, 73, 87 PS Buffer supply (5V nominal) GNDB (VSS) 4, 14, 24, 36, 46, 58, 68, 78, 92 PS Buffers 0V reference VCCC (VDD) 100 PS Core supply (5V nominal) GNDC 93 PS Core 0V reference The EDAC has 69 signal pins, whereof 11 are inputs, 2 are outputs and 56 are I/Os. T EM I C Semiconductors 4 REQUIREMENTS 4.1 GENERAL Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 20 /42 Page 20 The complete requirements for procurement of the integrated circuits specified herein are stated in this specification and ESA / SCC Generic Specification N 9000 for Integrated Circuits. Deviations from the generic specification applicable to this specification only, are listed in Par.4 . 2. Deviations from applicable Generic Specifications and this Detail Specification, formally agreed with specific manufacturers on the basis that the alternative requirements are equivalent to ESA / SCC requirements and do not affect the components reliability, are listed in the appendices attached to this specification. 4.1.1 Deviation from Applicable Specifications other than ESA/SCC N9000 None 4.2 DEVIATIONS FROM ESA / SCC GENERIC SPECIFICATION N 9000 4.2.1 Deviations from Special In-Process Controls None 4.2.2 Deviation from Final Production Tests (Chart II) None 4.2.3 Deviations from Burn-in Tests(Chart III) High Temperature Reverse Bias (HTRB) shall not be performed. 4.2.4 Deviations from Qualification, Environmental and Endurance Test (Chart IV) None. 4.2.5 Deviations from Lot Acceptance Tests(Chart V) None 4.3 MECHANICAL REQUIREMENTS 4.3.1 Dimension Check The dimension of the integrated circuit specified herein shall be checked . They shall conform to those shown in Figure 2. 4.3.2 Weight The maximum weight of the integrated circuits specified herein shall be 3.0 grams. 4.4 MATERIAL AND FINISHES The materials and finishes shall be as specified herein. Where a definite material is not specified, a material which will enable the integrated circuits specified herein to meet the performance requirements of this specification shall be used. Acceptance or approval of any constituent material does not guarantee acceptance of the finished product. T EM I C Document number MHS/SCC 021 Semiconductors 4.4.1 Date Issue 23/12/1999 Rev C Rev C 21 /42 Page 21 Case The case shall be hermetically sealed and have a ceramic body. The lids shall be brazed . 4.4.2 Lead Material and finish The lead materialshall be type G with type2 finish in accordance with the requirements of ESA / SCC Basic Specification N 23500. (See table 1(a) for type Variants) . 4.4.3 Technology Devices supplied against this specificationshall be 1.0 micron (drawn or 0.8 micron effective gate length) CMOS / epi Technology, with radiation tolerance. 4.4.4 Die Attachment Devices supplied against this specification shall employ silver-glass as their die attach material. 4.5 MARKING 4.5.1 General The marking of all components delivered to this specification shall be in accordance with the requirement of ESA / SCC Basic Specification N 21700. Each component shall be marked in respect of : 4.5.2 (a) Lead Identification (b) The Component Number (c) Traceability Information Lead Identification An index shall be located at the top of the package in the position defined in figure 2 to identify the pin number 1 . The pin numbering shallbe read in a counter clockwise order starting with pin N 1. 4.5.3 The Component Number Each component shall bear the Component number which shall be constituted and marked as follow : SMFR-29C516ESB Package : FR : MQFPL100 KR : MQFPF100 Testing Level : SB : level B SC : level C T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 22 /42 Page 22 The Total Dose Radiation Level designator shall be added for those devices for which a letter sample has been successfully tested to the level in questionFor . these devices a code shall be added in accordance with the requirements of ESA/SCC basic specification N 22900 . 4.5.4 Traceability Information Each component shall be marked in respect of traceability information in accordance with ESA / SCC Basic Specification N 21700. 4.6 ELECTRICAL MEASUREMENTS 4.6.1 Electrical Measurements at Room Temperature The parameters to be measured with respect of electrical characteristics are scheduled in Table 2. Unless otherwise specified, the measurements shall be performed at Tamb = +22 +3C 4.6.2 Electrical Measurements at High and Low Temperature s The parameters to be measured at high and low temperature are scheduled in Table 3. The measurements shall be performed atTamb = + 125 (+0/-5) C and -55 (+5/-0) C respectively. 4.6.3 Circuits for Electrical Measurements Circuits for use in performing electrical measurements listed in Table 2 and 3 of this specification are shown in Figure 4. 4.7 BURN-IN TESTS 4.7.1 Parameter Drift Values The parameter drift values applicable to burn-in are specified in Table 4 of this specification . Unless otherwise stated, measurements shall be performed at + 22 + 3 C. The parameter drift values (), applicable to the parameters scheduled, shall not be exceeded. In addition to these drift value requirements, the appropriate limit value specified for a given parameter in Table 2 shall not be exceeded. 4.7.2 Conditions for Power Burn-in The requirements for power burn-in are specified in Section 7 of ESA/SCC Generic Specification N 9000. The conditions for power burn-in shall be as specified in Table 5 of this specification. 4.7.3 Electrical Circuits for Power Burn-in Circuits for use in performing the power burn-in tests are shown in Figure 5 of this specification. T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 23 /42 Page 23 TABLE 2 ELECTRICAL MEASUREMENTS AT ROOM TEMPERATURE - d.c. PARAMETERS N Characteristics Symbol 1 Functional Test - VCCmin 2 Functional Test - 3 Functional Test - VCCtyp. VCCmax 4 Low level input 5 6 7 8 9 10 11 12 13 14 15 IILPU current. Pull_up inputs High level input IIH current Output leakage IOZLPU Low current Pull Up Output Output leakage IOZH High current Supply current IDDSB stand-by Supply current IDDOP operating Low level input VIL voltage High level input VIH voltage Low level Output VOL voltage High level output VOH voltage Input CI Capacitance Output CIO Capacitance, NOTES : See Page 25 Test Test Test Method Fig. Conditions Mil-Std-883 3014 3(b) VDD= 4.5V Sim1 to Sim 2 VIH=VDD, VIL=GND 3014 3(b) VDD= 5.0 V Sim1 to Sim 2 ViH=VDD, VIL=GND 3014 3(b) VDD= 5.5V Sim1 to Sim 2 VIH=VDD, VIL=GND 3009 4(c) VIN=GND, VDD=5.5V 3010 Limits Unit Note Min - Max - - - - - - - - -100 - A 3 4(a) VIN= VDD=5.5V - 10 A 3 4(d) Outputs disabled Vout=GND -100 - A 3 - 10 A 3 20 A 3 20 mA 3 - 0.8 V 1 2.2 - V 1 - 0.4 V 3 3013 4(d) Outputs disabled Vout=VDD 4(h) VDD=5.5V , Static mode Output = 0 mA 4(g) VDD=5.5V , Output = 0 mA, F= 10MHz 3(b) Functional verification 3013 3(b) Functional verification 3007 4(e) VDD=5.5 V IOL=+12.8 mA 3006 4(f) VDD=4.5 V IOH=-12.8 mA 3.7 - V 3 3012 4(i) VDD= 0V 8 pF 2 3012 4(j) VDD= 0V 12 pF 2 3005 3005 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 24 /42 Page 24 TABLE 2 ELECTRICAL MEASUREMENTS AT ROOM TEMPERATURE - a.c. PARAMETERS N Characteristics Symbol Test Test Method Fig. Mil-Std-883 Test Conditions Limits Unit Note Min Max 1 U1D to MC Propagation delay TPBUS_MC 3003 4(k) VDD= 4.5 V 26 nS 3-4 2 Propagation delay MD to CERRN TPCERRN 3003 4(k) VDD= 4.5 V 33 nS 3-4 3 Propagation delay MD to U1D TPBUS_U1 3003 4(k) VDD= 4.5 V 33 nS 3-4 4 Propagation delay U1D to MD TPBUS_MD 3003 4(k) VDD= 4.5 V 15 nS 3-4 5 Propagation delay Correct,sync to U2D TPBUS_U2 3003 4(k) VDD= 4.5 V 22 nS 3-4 6 Enable time from TN to U1D TPZ1BUS_U1 3003 4(k) VDD= 4.5 V 23 nS 3-4 7 Disable time from TN to U1D TPZ2BUS_U1 3003 4(k) VDD= 4.5 V 23 nS 3-4 8 Enable time from U2X1N to MC TPZ1BUS_MC 3003 4(k) VDD= 4.5 V 22 nS 3-4 9 Disable time from TN to MC TPZ2BUS_MC 3003 4(k) VDD= 4.5 V 22 nS 3-4 10 Enable time from U2X1N to MD TPZ1BUS_MD 3003 4(k) VDD= 4.5 V 22 nS 3-4 11 Disable time from TN to MD TPZ2BUS_MD 3003 4(k) VDD= 4.5 V 22 nS 3-4 12 Enable time from U2X1N to U2D TPZ1BUS_U2 3003 4(k) VDD= 4.5 V 22 nS 3-4 13 Disable time from TN to U2D TPZ2BUS_U2 3003 4(k) VDD= 4.5 V 23 nS 3-4 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 25 /42 Page 25 NOTES : 1]Forcing conditions of the functional test, assure that these limits are met, but they will not be individually recorded . 2]May not be measured, but shall be guaranteed . Tested at initial design and after major process changes 3]Read & Record measurements for level B and Go/No_Go tests for level C 4]The timings correspond to :Supply voltage = 4.5V . Input Conditions are Vil = 0V , VIH = VDD timing description figure 4(l) T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 26 /42 Page 26 TABLE 3 ELECTRICAL MEASUREMENTS AT HIGH AND LOW TEMPERATURES-d.c. PARAMETERS N Characteristics 1 Functional Test Symbol - VCCmin 2 Functional Test - 3 Functional Test - VCCtyp. VCCmax 4 Low level input 5 6 7 8 9 10 11 12 13 14 15 IILPU current. Pull_up inputs High level input IIH current Output leakage IOZLPU Low current Pull Up Output Output leakage IOZH High current Supply current IDDSB stand-by Supply current IDDOP operating Low level input VIL voltage High level input VIH voltage Low level Output VOL voltage High level output VOH voltage Input CI Capacitance Output CIO Capacitance, Test Test Test Method Fig. Conditions Mil-Std-883 3014 VDD= 4.5V Sim1 to Sim 2 VIH=VDD, VIL=GND 3014 VDD= 5.0 V Sim1 to Sim 2 ViH=VDD, VIL=GND 3014 VDD= 5.5V Sim1 to Sim 2 VIH=VDD, VIL=GND 3009 4(c) VIN=GND VDD=5.5V 3010 3005 3005 3013 Limits Unit Note Min - Max - - - - - - - - -100 - A 3 4(a) VIN= VDD=5.5V - 10 A 3 4(d) Outputs disabled Vout=GND -100 - A 3 - 10 A 3 20 A 3 20 mA 3 - 0.8 V 1 4(d) Outputs disabled Vout=VDD 4(h) VDD=5.5V , Static mode Output = 0 mA 4(g) VDD=5.5V , Output = 0 mA, F= 10MHz Functional verification 3013 Functional verification 2.2 - V 1 3007 4(e) VDD=5.5 V IOL=+12.8 mA - 0.4 V 3 3006 4(f) VDD=4.5 V IOH=-12.8 mA 3.7 - V 3 3012 4(i) VDD= 0V 8 pF 2 3012 4(j) VDD= 0V 12 pF 2 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 27 /42 Page 27 TABLE 3 ELECTRICAL MEASUREMENTS AT HIGH AND LOW TEMPERATURES- a.c. PARAMETERS N 1 2 3 4 5 6 7 8 9 10 11 12 13 Characteristics Propagation delay U1D to MC Propagation delay MD to CERRN Propagation delay MD to U1D Propagation delay U1D to MD Propagation delay Correct,sync to U2D Enable time from TN to U1D Disable time from TN to U1D Enable time from U2X1N to MC Disable time from TN to MC Enable time from U2X1N to MD Disable time from TN to MD Enable time from U2X1N to U2D Disable time from TN to U2D NOTES : See Page 25 Symbol TPBUS_MC Test Test Test Method Fig. Conditions Mil-Std-883 3003 4(k) VDD= 4.5 V Limits Min Unit Note Max 26 nS 3-4 TPCERRN 3003 4(k) VDD= 4.5 V 33 nS 3-4 TPBUS_U1 3003 4(k) VDD= 4.5 V 33 nS 3-4 TPBUS_MD 3003 4(k) VDD= 4.5 V 15 nS 3-4 TPBUS_U2 3003 4(k) VDD= 4.5 V 22 nS 3-4 TPZ1BUS_U1 3003 4(k) VDD= 4.5 V 23 nS 3-4 TPZ2BUS_U1 3003 4(k) VDD= 4.5 V 23 nS 3-4 TPZ1BUS_MC 3003 4(k) VDD= 4.5 V 22 nS 3-4 TPZ2BUS_MC 3003 4(k) VDD= 4.5 V 22 nS 3-4 TPZ1BUS_MD 3003 4(k) VDD= 4.5 V 22 nS 3-4 TPZ2BUS_MD 3003 4(k) VDD= 4.5 V 22 nS 3-4 TPZ1BUS_U2 3003 4(k) VDD= 4.5 V 22 nS 3-4 TPZ2BUS_U2 3003 4(k) VDD= 4.5 V 23 nS 3-4 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 28 /42 Page 28 FIGURE 4 CIRCUITS FOR ELECTRICAL MEASUREMENTS FIGURE 4(a) - INPUT HIGH CURRENT FIGURE 4(b) - INPUT CLAMP VOLTAGE VDD VDD Ii Vin OUTPUTS OUTPUTS OPEN VIC(-) NOTE : EACH PIN TESTED SEPARATELY NOTE : FIGURE 4(c) - INPUT LOW CURRENT FOR VIC(-) GND=VDD=0V FIGURE 4(d) - OUTPUT OFF-STATE CURRENT VDD VDD Ii Vin OUTPUTS INPUT AS PER TRUTH TABLE TO GIVE OFFSTATE AT OUTPUT. NOTE : EACH PIN TESTED SEPARATELY NOTE : EACH OUTPUT TO BE TESTED SEPARATELY IOZL IOZH T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 29 /42 Page 29 FIGURE 4 CIRCUITS FOR ELECTRICAL MEASUREMENTS (CONTINUED) FIGURE 4(e) - OUTPUT VOLTAGE LOW FIGURE 4(f) - OUTPUT VOLTAGE HIGH VDD VDD IOH IOL INPUTS AS PER TRUTH TABLE TO GIVE OUTPUT LOW. VOL V INPUTS AS PER TRUTH TABLE TO GIVE OUTPUT LOW. NOTE : EACH OUTPUT SEPARATELY VOH NOTE : EACH OUTPUT SEPARATELY FIGURE 4(g) - OPERATING SUPPLY CURRENT FIGURE 4(h) - STANDBY CURRENT VDD VDD IDDOP IDDSB OUTPUTS OUTPUTS OPEN OPEN T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 30 /42 Page 30 FIGURE 4 CIRCUITS FOR ELECTRICAL MEASUREMENTS (CONTINUED) FIGURE 4(i) - INPUT CAPACITANCE FIGURE 4(j) - OUTPUT CAPACITANCE VDD VDD CAPACITANCE BRIDGE OUTPUT OPEN Remaining inputs All Inputs CAPACITANCE BRIDGE NOTE : EACH INPUT TESTED SEPARATELY f=100 MHz to 1 MHz FIGURE 4(k) - PROPAGATION DELAY VDD INPUT CONDITIONS (SEE FIGURE 3(b) ) OUTPUTS (SEE NOTE 4 TO TABLE 2) NOTE :EACH OUTPUT TESTED SEPARATELY f=100 MHz to 1 MHz T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 31 /42 FIGURE 4(l) - TIMING WAVEFORMS Memory Write Page 31 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 32 /42 FIGURE 4(m) - TIMING WAVEFORMS (CONTINUED) Transfer Write Timing Diagram Page 32 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 33 /42 FIGURE 4(n) - TIMING WAVEFORMS (CONTINUED) Memory Read Timing Diagram Page 33 T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 34 /42 FIGURE 4(o) - TIMING WAVEFORMS (CONTINUED) Transfert Read Timing Diagram Page 34 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 35 /42 Page 35 TABLE 4 - PARAMETER DRIFT VALUES N 4 5 6 7 8 12 13 CHARACTERISTICS SYMBOL SPEC. AND/OR TEST METHOD TEST CONDITIONS CHANGE LIMITS UNIT Low Level Input Current, IILPU Pull_Up High level input current IIH Output Leakage Low IOZLPU Current Pull Up Output Output leakage high IOZH current Supply Current IDDSBA Stand-By Ouput voltage low level VOL Output voltage high VOH level As per Table 2 As per Table 2 5 A As per table 2 As per Table 2 As per Table 2 As per Table 2 1 5 A A As per table 2 As per Table 2 1 A As per Table 2 As per Table 2 5 A As per table 2 As per table 2 As per Table 2 As per Table 2 100 100 mV mV T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 36 /42 Page 36 TABLE 5 - CONDITIONS FOR POWER BURN-IN AND OPERATING LIFE-TEST N 1 6 6 CHARACTERISTICS Ambient Temperature Positive Supply Voltage Negative Supply Voltage SYMBOL CONDITIONS UNIT Tamb VDD VSS + 125(+0 -5) 5.0 (+0.5-0) 0 C V V NOTES : 1] Input Protection Resistor = 1.0 K ohms 2] Output Load Resistors = 1.0 K ohms 3] Clock signals (S1 to S10) have a square waveform and the frequencies are the following S1 = 1.65MHz, S2 = 825.00 kHz, S3 = 412.50 kHz, S4 = 206.25 kHz, S5 = 103.12 kHz, S6 = 51.56 kHz, S7 = 25.78 kHz, S8 = 12.89 kHz, S9 = 100.70 Hz, S10 = 50.30 Hz T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 37 /42 Page 37 FIGURE 5 - ELECTRICAL CIRCUIT FOR POWER BURN-IN AND OPERATING LIFE TEST Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Connection NC NC S5 GND S4 S3 S4 S3 VDD S2 S1 S1 S1 GND S1 S2 S2 S2 VDD S1 S1 S3 S1 GND R VDD Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Connection R VDD R GND S1 NC NC NC VDD S2 S3 S4 GND S3 S2 S1 S1 VDD S2 S2 S4 S3 GND S2 S1 S2 NC Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Connection NC NC S1 VDD S8 R GND S7 GND S1 S2 S2 S3 VDD S4 S2 S1 S4 GND S3 S1 S3 S1 VDD S1 S4 Notes : NC: GND : VDD : R GND : R VDD : S1 to S10 : No connected Ground Positive supply voltage Connected to GND through 1Kohm resistor Connected to VDD through 1Kohm resistor As per Table 5 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Connection S2 S2 GND NC NC NC NC S2 S2 S1 S3 VDD S4 S1 S2 S3 GND GND R GND S10 S9 R VDD R VDD S6 VDD T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 38 /42 4.8 ENVIRONMENTAL AND ENDURANCE TESTS 4.8.1 Electrical Measurements at Completion of Environmental Tests Page 38 The parameters to be measured on completion of environmental tests are scheduled in Table 6. Unless otherwise stated, the measurements shall be performed atambT = 22 +3C 4.8.2 Electrical Measurements at Intermediate Point during Endurance Tests The parameters to be measured at intermediate points during endurance tests are scheduled in Table 6 of this specification . Unless otherwise stated, the measurements shall be performed at Tamb = 22+3C 4.8.3 Electrical Measurements on Completion ofEndurance Tests The parameters to be measured on Completion of endurance testing are scheduled in Table 6 of this specification . Unless otherwise stated, the measurements shall be performed at Tamb = 22+3C 4.8.4 Conditions for Operating LifeTests The requirements for operating life testing are specified in para . 9.21 of ESA/SCC Generic Specification N 9000 . The conditions for operating life testing shall be as specified in Table 5 of this specification . 4.8.5 Electrical Circuits for Operating Life-Tests Circuits for use in performing life-tests are shown in Figure 5 of this specification . 4.8.6 Condition For High Temperature Storage Test The requirements for high temperature storage test are specified in ESA/SCC Generic Specification N 9000 . The temperature to be applied shall be the maximum storage temperature specified in Table 1(b) of this specification . 4.9 TOTAL DOSE IRRADIATION TESTING 4.9.1 Application If specified in Par.. 4.2.1 of this specification, total dose irradiation testing shall be performed in accordance with the requirements of ESA/SCC Basic Specification N 22900. 4.9.2 Bias Conditions Continuous bias shall be applied during irradiation testing as shown in Figure 6 of this specification . 4.9.3 Electrical Measurements The parameters to be measured prior to irradiation exposure are scheduled in Table 2 of this specification . Only devices which meet the requirements of Table 2 shall be included in the test sample . The parameters to be measured during and on completion of irradiation testing are scheduled in Table 7 of this specification . T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 39 /42 Page 39 TABLE 6 -ELECTRICAL MEASUREMENTS AT INTERMEDIATE POINTS AND ON COMPLETION OF ENDURANCE TESTING N CHARACTERISTICS SYMBOL SPEC. AND/OR TEST METHOD TEST CONDITIONS N Characteristics Symbol As per table 2 As per table 2 Functional Test VCCmin Functional Test VCCtyp. Functional Test VCCmax Low level input current, IILPU Pull_up High level input current IIH Output leakage Low IOZLPU current Pull Up Output Output leakage High IOZH current Supply current stand-by IDDSB Supply current operating IDDOP Low level input voltage VIL High level input voltage VIH Low level Output voltage VOL High level output voltage VOH Input Capacitance CI Output Capacitance, CIO As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As As As As As As As As 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NOTES : per per per per per per per per As per table 2, see page 25 table table table table table table table table 2 2 2 2 2 2 2 2 LIMITS UNIT MIN MAX A -100 10 A A As per table 2 10 A As As As As As As As As 20 20 0.8 A mA V V V V pF pF per per per per per per per per table table table table table table table table 2 2 2 2 2 2 2 2 -100 2.2 0.4 3.7 8 12 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 40 /42 Page FIGURE 6 - BIAS CONDITIONS FOR IRRADIATION TESTING Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Connection NC NC S5 GND S4 S3 S4 S3 VDD S2 S1 S1 S1 GND S1 S2 S2 S2 VDD S1 S1 S3 S1 GND R VDD Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Connection R VDD R GND S1 NC NC NC VDD S2 S3 S4 GND S3 S2 S1 S1 VDD S2 S2 S4 S3 GND S2 S1 S2 NC Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Connection NC NC S1 VDD S8 R GND S7 GND S1 S2 S2 S3 VDD S4 S2 S1 S4 GND S3 S1 S3 S1 VDD S1 S4 Notes : NC: GND : VDD : R GND : R VDD : No connected Ground Positive supply voltage Connected to GND through 1Kohm resistor Connected to VDD through 1Kohm resistor - Supply voltage : 4.9V < VDD < 5.1V - Signals S1 to S10 are connected to a 10Hz square wave. Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Connection S2 S2 GND NC NC NC NC S2 S2 S1 S3 VDD S4 S1 S2 S3 GND GND R GND S10 S9 R VDD R VDD S6 VDD 40 T EM I C Document number MHS/SCC 021 Semiconductors Date Issue 23/12/1999 Rev C Rev C 41 /42 Page 41 TABLE 7 -ELECTRICAL MEASUREMENTS DURING AND ON COMPLETION OF IRRADIATION TESTING N 1 2 3 4 5 6 7 8 10 11 12 13 CHARACTERISTICS SYMBOL SPEC. AND/OR TEST METHOD Functional Test VCCmin Functional Test VCCtyp. Functional Test VCCmax Low level input current, IILPU Pull_up High level input current IIH Output leakage Low IOZLPU current Pull Up Output Output leakage High IOZH current Supply current stand-by IDDSB Low level input voltage VIL High level input voltage VIH Low level Output VOL voltage High level output VOH voltage As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As per table 2 As As As As NOTES : As per table 2, see page 25 per per per per table table table table 2 2 2 2 As per table 2 TEST CONDITIONS LIMITS UNIT MIN MAX A -100 10 A A As per table 2 10 A As As As As 5 0.8 mA V V V per per per per table table table table 2 2 2 2 As per table 2 -100 2.2 0.4 3.7 V T EM I C Semiconductors Document number MHS/SCC 021 Date Issue 23/12/1999 Rev C Rev C 42 /42 APPENDIX 'A' AGREED DEVIATIONS FOR MHS (F) Par. 9.9.3 , Electrical measurements may be done at high temperature (130 C) Page 42