1.2 A, DC-to-DC Inverting Regulator ADP5073 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT CVREF AVIN VIN VREF PVIN RFB CIN ADP5073 FB RFT ON EN OFF VOUT SW CVREG D1 VREG COUT L1 RPG SS PWRGD PWRGD SLEW CC RC COMP APPLICATIONS SYNC/FREQ GND 12817-001 Wide input voltage range: 2.85 V to 15 V Adjustable negative output to VIN - 39 V Integrated 1.2 A main switch 1.2 MHz/2.4 MHz switching frequency with optional external frequency synchronization from 1.0 MHz to 2.6 MHz Resistor programmable soft start timer Slew rate control for lower system noise Precision enable control Power-good output UVLO, OCP, OVP, and TSD protection 3 mm x 3 mm, 16-lead LFCSP -40C to +125C junction temperature Supported by the ADIsimPower tool set Figure 1. Bipolar amplifiers, ADCs, digital-to-analog converters (DACs), and multiplexers High speed converters Radio frequency (RF) power amplifier (PA) bias Optical modules GENERAL DESCRIPTION The ADP5073 is a high performance dc-to-dc inverting regulator used to generate negative supply rails. The input voltage range of 2.85 V to 15 V supports a wide variety of applications. The integrated main switch enables the generation of an adjustable negative output voltage down to 39 V below the input voltage. The ADP5073 operates at a pin selected 1.2 MHz/2.4 MHz switching frequency. The ADP5073 can synchronize with an external oscillator from 1.0 MHz to 2.6 MHz to ease noise filtering in sensitive applications. The regulator implements programmable slew rate control circuitry for the MOSFET driver stage to reduce electromagnetic interference (EMI). The ADP5073 includes a fixed internal or resistor programmable soft start timer to prevent inrush current at power-up. During shutdown, the regulator completely disconnects the load from the input supply to provide a true shutdown. A power-good pin is available to indicate the output is stable. Rev. A Other key safety features in the ADP5073 include overcurrent protection (OCP), overvoltage protection (OVP), thermal shutdown (TSD), and input undervoltage lockout (UVLO). The ADP5073 is available in a 16-lead LFCSP and is rated for a -40C to +125C operating junction temperature range. Table 1. Related Devices Device ADP5070 Boost Switch (A) 1.0 Inverter Switch (A) 0.6 ADP5071 2.0 1.2 ADP5073 Not applicable Not applicable Not applicable 1.2 ADP5074 ADP5075 2.4 0.8 Package 20-lead LFCSP (4 mm x 4 mm) and TSSOP 20-lead LFCSP (4 mm x 4 mm) and TSSOP 16-lead LFCSP (3 mm x 3 mm) 16-lead LFCSP (3 mm x 3 mm) 12-ball WLCSP (1.61 mm x 2.18 mm) Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. 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Technical Support www.analog.com ADP5073 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Internal Regulators ..................................................................... 10 Applications ....................................................................................... 1 Precision Enabling...................................................................... 11 Typical Application Circuit ............................................................. 1 Soft Start ...................................................................................... 11 General Description ......................................................................... 1 Slew Rate Control ....................................................................... 11 Revision History ............................................................................... 2 Current-Limit Protection ............................................................ 11 Specifications..................................................................................... 3 Overvoltage Protection .............................................................. 11 Absolute Maximum Ratings ............................................................ 5 Power Good ................................................................................ 11 Thermal Resistance ...................................................................... 5 Thermal Shutdown .................................................................... 11 ESD Caution .................................................................................. 5 Applications Information .............................................................. 12 Pin Configuration and Function Descriptions ............................. 6 ADIsimPower Design Tool ....................................................... 12 Typical Performance Characteristics ............................................. 7 Component Selection ................................................................ 12 Theory of Operation ...................................................................... 10 Common Applications .............................................................. 15 PWM Mode ................................................................................. 10 Layout Considerations ............................................................... 16 Skip Mode .................................................................................... 10 Outline Dimensions ....................................................................... 17 Undervoltage Lockout (UVLO) ............................................... 10 Ordering Guide .......................................................................... 17 Oscillator and Synchronization ................................................ 10 REVISION HISTORY 10/2017--Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 10/2015--Revision 0: Initial Version Rev. A | Page 2 of 17 Data Sheet ADP5073 SPECIFICATIONS PVIN = AVIN = 2.85 V to 15 V, VOUT = -15 V, fSW = 1200 kHz, TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 2. Parameter INPUT SUPPLY VOLTAGE RANGE QUIESCENT CURRENT Operating Quiescent Current PVIN, AVIN (Total) Shutdown Current UVLO System UVLO Threshold Rising Falling Hysteresis OSCILLATOR CIRCUIT Switching Frequency SYNC/FREQ Input Input Clock Range Input Clock Minimum On Pulse Width Input Clock Minimum Off Pulse Width Input Clock High Logic Input Clock Low Logic PRECISION ENABLING (EN) High Level Threshold Low Level Threshold Shutdown Mode Pull-Down Resistance INTERNAL REGULATOR VREG Output Voltage INVERTING REGULATOR Reference Voltage Accuracy Symbol VIN Min 2.85 Typ Max 15 Unit V Test Conditions/Comments PVIN, AVIN IQ 1.8 4.0 mA ISHDN 5 10 A No switching, EN = high, PVIN = AVIN = 5V No switching, EN = low, PVIN = AVIN = 5 V, -40C TJ +85C VUVLO_RISING VUVLO_FALLING VHYS 2.85 2.5 2.8 2.55 0.25 V V V fSW 1.130 2.240 1.200 2.400 1.270 2.560 MHz MHz fSYNC tSYNC_MIN_ON tSYNC_MIN_OFF VH (SYNC) VL (SYNC) 1.000 100 100 2.600 MHz ns ns V V VTH_H VTH_L VTH_S REN 1.125 1.025 0.4 AVIN 1.3 0.4 VREG VREF 1.15 1.05 1.175 1.075 1.48 V V V M 4.25 V 1.60 -0.5 -1.5 +0.5 +1.5 Feedback Voltage Accuracy VREF - VFB Feedback Bias Current Overvoltage Protection Threshold Power-Good Threshold IFB VOV VPG (GOOD) VPG (BAD) RDS_PG (ON) VDS_PG (MAX) 0.74 0.7 0.68 28 VPG (SUPPLY) 1.4 (VREF - VFB)/ ILOAD (VREF - VFB)/ VIN 0.0025 %/A 0.02 %/V Power-Good FET On Resistance Power-Good FET Maximum Drain Source Voltage Power-Good Supply Voltage Load Regulation Line Regulation 0.8 V % % V % % A V V V V -0.5 -1.5 +0.5 +1.5 0.1 5.5 Rev. A | Page 3 of 17 SYNC/FREQ = low SYNC/FREQ = high (connect to VREG) Internal circuitry disabled to achieve ISHDN TJ = 25C TJ = -40C to +125C TJ = 25C TJ = -40C to +125C At the FB pin after soft start is complete VREF - VFB VPG (GOOD) VREF - VFB VPG (BAD) Voltage required on PVIN pin for powergood FET to pull down ILOAD = 100 mA to 500 mA (regulator not in skip mode) VIN = 2.85 V to 14.5 V, ILOAD = 15 mA (regulator not in skip mode_ ADP5073 Data Sheet Parameter Error Amplifier (EA) Transconductance Power FET On Resistance Power FET Maximum Drain Source Voltage Current-Limit Threshold Minimum On Time Minimum Off Time SOFT START Soft Start Timer Symbol gM RDS (ON) VDS (MAX) ILIM Hiccup Time THERMAL SHUTDOWN Threshold Hysteresis tSS Min 270 1.2 Typ 300 200 1.375 55 50 Max 330 39 1.6 Unit A/V m V A ns ns tHICCUP 4 32 8 x tSS ms ms ms TSHDN THYS 150 15 C C Rev. A | Page 4 of 17 Test Conditions/Comments VIN = 5 V SS = open SS resistor = 50 k to GND Data Sheet ADP5073 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter PVIN, AVIN SW GND VREG EN, FB, SYNC/FREQ, PWRGD COMP, SLEW, SS, VREF Operating Junction Temperature Range Storage Temperature Range Soldering Conditions Rating -0.3 V to +18 V PVIN - 40 V to PVIN + 0.3 V -0.3 V to +0.3 V -0.3 V to lower of AVIN + 0.3 V or +6 V -0.3 V to +6 V -0.3 V to VREG + 0.3 V -40C to +125C JA and JT are based on a 4-layer printed circuit board (PCB) (two signals and two power planes) with thermal vias connecting the exposed pad to a ground plane as recommended in the Layout Considerations section. JC is measured at the top of the package and is independent of the PCB. The JT value is more appropriate for calculating junction to case temperature in the application. Table 4. Thermal Resistance Package Type 16-Lead LFCSP -65C to +150C JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A | Page 5 of 17 JA 75.01 JC 55.79 JT 0.95 Unit C/W ADP5073 Data Sheet 13 AVIN 14 NIC 15 NIC 16 NIC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SW 1 PWRGD 3 12 PVIN ADP5073 TOP VIEW (Not to Scale) 10 GND VREF FB 8 COMP 7 SS 5 9 EN 6 SYNC/FREQ 4 11 VREG NOTES. 1. NIC = NO INTERNAL CONNECTION. FOR IMPROVED THERMAL PERFORMANCE, CONNECT THESE PINS TO THE PCB GROUND PLANE. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND. 12817-002 SLEW 2 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 Mnemonic SW SLEW 3 PWRGD 4 SYNC/FREQ 5 SS 6 EN 7 COMP 8 FB 9 10 11 12 13 14, 15, 16 EPAD VREF GND VREG PVIN AVIN NIC EPAD Description Switching Node for the Inverting Regulator. Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the FET driving the SW pin. For the fastest slew rate (best efficiency), leave the SLEW pin open. For a normal slew rate, connect the SLEW pin to VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to GND. Power-Good Output (Open-Drain). Pull this pin up to VREG with a resistor to provide a high output when power is good. Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ pin high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the switching frequency, connect the SYNC/FREQ pin to an external clock. Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower soft start time, connect a resistor between the SS pin and GND. Inverting Regulator Precision Enable. The EN pin is compared to an internal precision reference to enable the inverting regulator output. Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between this pin and GND. Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the inverting regulator output capacitor and VREF to program the output voltage. Inverting Regulator Reference Output. Connect a 1.0 F ceramic filter capacitor between the VREF pin and GND. Ground. Internal Regulator Output. Connect a 1.0 F ceramic filter capacitor between the VREG pin and GND. Power Input for the Inverting Regulator. System Power Supply for the ADP5073. No Internal Connection. For improved thermal performance, connect these pins to the PCB ground plane. Exposed Pad. Connect the exposed pad to GND. Rev. A | Page 6 of 17 Data Sheet ADP5073 TYPICAL PERFORMANCE CHARACTERISTICS Typical performance characteristics are generated using the standard bill of materials for each input/output combination listed in Table 9. 800 90 VIN = 3.3V, L = 5.6H VIN = 3.3V, L = 6.8H VIN = 5V, L = 6.8H VIN = 5V, L = 10H VIN = 12V, L = 15H VIN = 12V, L = 22H VIN = 15V, L = 15H 500 70 400 300 200 -25 -20 -15 -10 -5 0 0 0.001 VIN = 12V, 1.2MHz VIN = 12V, 2.4MHz 0.01 0.1 Figure 6. Efficiency vs. Current Load (IOUT), VIN = 12 V, VOUT = -5 V, TA = 25C 90 VIN = 3.3V, L = 2.2H VIN = 3.3V, L = 3.3H VIN = 5V, L = 3.3H VIN = 5V, L = 5.6H VIN = 12V, L = 6.8H VIN = 12V, L = 10H VIN = 15V, L = 6.8H 80 200 60 50 40 30 VIN = 12V, 1.2MHz VIN = 12V, 2.4MHz VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 20 100 -30 -25 -20 -15 -10 -5 12817-004 10 0 VOUT (V) 0.1 1 Figure 7. Efficiency vs. Current Load (IOUT), VIN = 12 V and 5 V, VOUT = -15 V, TA = 25C 80 90 70 80 60 70 50 40 30 20 60 50 40 30 20 VIN = 12V, 1.2MHz VIN = 12V, 2.4MHz 0.01 0.1 IOUT (A) 1 VIN = 5V, 1.2MHz VIN = 5V, 2.4MHz 10 10 12817-005 10 0 0.001 0.01 IOUT (A) EFFICIENCY (%) EFFICIENCY (%) Figure 4. Maximum Output Current, fSW = 2.4 MHz, TA = 25C, Based on Target of 70% ILIM (MIN) 0 0.001 12817-007 EFFICIENCY (%) 70 300 0 -35 1 IOUT (A) 600 IOUT (MAX) (mA) 30 12817-006 -30 12817-003 -35 Figure 3. Maximum Output Current, fSW = 1.2 MHz, TA = 25C, Based on Target of 70% ILIM (MIN) 400 40 10 VOUT (V) 500 50 20 100 0 -40 60 0 0.001 0.01 0.1 IOUT (A) Figure 5. Efficiency vs. Current Load (IOUT), VIN = 12 V, VOUT = -2.5 V, TA = 25C 1 12817-008 IOUT (MAX) (mA) 600 80 EFFICIENCY (%) 700 Figure 8. Efficiency vs. Current Load (IOUT), VIN = 5 V, VOUT = -30 V, TA = 25C Rev. A | Page 7 of 17 ADP5073 Data Sheet 2.54 90 TA = +125C TA = +25C TA = -40C 80 60 50 40 30 20 +125C +25C -40C 0.01 0.1 1 IOUT (A) 2.39 2.34 2.29 2.24 0 4 6 8 10 12 14 16 VIN (V) Figure 9. Efficiency vs. Current Load (IOUT) for Various Temperatures, VIN = 5 V, VOUT = -15 V, fSW = 1.2 MHz Figure 12. Oscillator Frequency vs. Input Voltage (VIN) for Various Temperatures, SYNC/FREQ Pin = High 0.50 1.27 OSCILLATOR FREQUENCY (MHz) 0.30 0.10 -0.10 -0.30 TA = +125C TA = +25C TA = -40C 1.25 1.23 1.21 1.19 1.17 0 2 4 6 8 10 12 14 VIN (V) 12817-030 1.13 -0.50 0 4 6 8 VIN (V) 10 12 14 16 Figure 13. Oscillator Frequency vs. Input Voltage (VIN) for Various Temperatures, SYNC/FREQ Pin = Low Figure 10. Line Regulation, VOUT = -5 V, fSW = 1.2 MHz, 15 mA Load, TA = 25C (Skip Mode Not Shown) 18 0.50 SHUTDOWN QUIESCENT CURRENT (A) 1.2 MHz 2.4 MHz 0.30 0.10 -0.10 -0.30 -0.50 0 0.1 0.2 0.3 0.4 0.5 0.6 LOAD (A) 0.7 0.8 0.9 1 Figure 11. Load Regulation, VIN = 12 V, VOUT = -5 V, fSW = 1.2 MHz, TA = 25C (Skip Mode Not Shown) +80C +25C -40C 16 14 12 10 8 6 4 2 0 12817-031 VARIATION IN VREF (VFB) (%) 2 12817-014 1.15 0 2 4 6 8 VIN (V) 10 12 14 16 12817-015 VARIATION IN VREF (VFB) (%) 2 12817-013 0 0.001 2.44 12817-010 10 2.49 OSCILLATOR FREQUENCY (MHz) EFFICIENCY (%) 70 Figure 14. Shutdown Quiescent Current (ISHDN) vs. Input Voltage (VIN) for Various Temperatures, EN Pin Below Shutdown Threshold Rev. A | Page 8 of 17 Data Sheet ADP5073 +125C +25C -40C 2.2 2.1 IINDUCTOR 3 2.0 1.9 1 VSW 1.8 1.7 2 1.5 0 2 4 6 8 VIN (V) 10 12 14 16 CH1 5.00V CH2 500mV CH3 100mA Figure 15. Operating Quiescent Current (IQ) vs. Input Voltage (VIN) for Various Temperatures, EN Pin On M 4.00s T 63.60% B W 2.50GS/s 1M POINTS CH1 10.0V 12817-019 VOUT 1.6 12817-016 OPERATING QUIESCENT CURRENT (mA) 2.3 Figure 18. Skip Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage (VSW), and Output Ripple (VOUT), VIN = 12 V, VOUT = -5 V, ILOAD = 1 mA, fSW = 1.2 MHz, TA = 25C VIN IINDUCTOR 3 2 VOUT 1 1 VSW VFB 4 VOUT M 4.00ms T 20.00% 2.50MS/s CH1 100k POINTS 5.00V CH1 5.00V CH2 500mV CH3 200mA Figure 16. Line Transient Showing VIN, VOUT, and VFB, VIN = 4.5 V to 5.5 V Step, VOUT = -5 V, RLOAD = 300 , fSW = 1.2 MHz, TA = 25C B M 200ns T 37.70% W 2.50GS/s 1M points CH1 7.00V 12817-020 CH1 1.00V BW CH2 100mV BW CH4 20.0mV BW 12817-017 2 Figure 19. Discontinuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage (VSW), and Output Ripple (VOUT), VIN = 12 V, VOUT = -5 V, ILOAD = 50 mA, fSW = 1.2 MHz, TA = 25C IINDUCTOR ILOAD 3 VOUT 2 3 1 VSW VFB 4 VOUT B W B W B W 2.50MS/s M 4.00ms CH3 T 12.48ms 100k POINTS 40.0mA CH1 5.00V CH2 500mV CH3 200mA 12817-018 CH2 50.0mV CH3 10.0mA CH4 5.00mV Figure 17. Load Transient Showing ILOAD, VOUT, and VFB, VIN = 12 V, VOUT = -5 V, ILOAD = 35 mA to 45 mA Step, fSW = 1.2 MHz, TA = 25C B W B W 2.50GS/s M 200ns CH1 T -13.0020s 1M POINTS 7.70V 12817-021 2 Figure 20. Continuous Conduction Mode Operation Showing Inductor Current (IINDUCTOR), Switch Node Voltage (VSW), and Output Ripple (VOUT), VIN = 12 V, VOUT = -5 V, ILOAD = 200 mA, fSW = 1.2 MHz, TA = 25C Rev. A | Page 9 of 17 ADP5073 Data Sheet THEORY OF OPERATION VIN CIN CVREG SYNC/ FREQ PVIN VREG AVIN CURRENT SENSE HIGH VOLTAGE REGULATOR EN INVERTER PWM CONTROL HIGH VOLTAGE BAND GAP SLEW L1 SLEW PLL D1 SW COUT RFT ERROR AMP REF OSCILLATOR RPG (OPTIONAL) RFB CONTROL EN REF PWRGD REF_1.6V VREG THERMAL FB SHUTDOWN COMP 4A POWER GOOD VREF CVREF UVLO START-UP TIMERS OVP REFERENCE GENERATOR REF REF_1.6V CC GND SS RC 12817-023 VREG FB RSS (OPTIONAL) Figure 21. Functional Block Diagram PWM MODE OSCILLATOR AND SYNCHRONIZATION The inverting regulator in the ADP5073 operates at a fixed frequency set by an internal oscillator. At the start of each oscillator cycle, the MOSFET switch turns on, applying a positive voltage across the inductor. The inductor current (IINDUCTOR) increases until the current sense signal crosses the peak inductor current threshold that turns off the MOSFET switch; this threshold is set by the error amplifier output. During the MOSFET off time, the inductor current declines through the external diode until the next oscillator clock pulse starts a new cycle. The ADP5073 regulates the output voltage by adjusting the peak inductor current threshold. A phase-locked loop (PLL)-based oscillator generates the internal clock and offers a choice of two internally generated frequency options or external clock synchronization. The switching frequency is configured using the SYNC/FREQ pin options shown in Table 6. SKIP MODE During light load operation, the regulator can skip pulses to maintain output voltage regulation. Skipping pulses increases the device efficiency. The COMP voltage is monitored internally and when it falls below a threshold (due to the output voltage rising above the target during a switching cycle), the next switching cycle is skipped. This voltage is monitored on a cycle-by-cycle basis. During skip operation, the output ripple is increased and the ripple frequency varies. The choice of inductor defines the output current below which skip mode occurs. UNDERVOLTAGE LOCKOUT (UVLO) The UVLO circuitry monitors the AVIN pin voltage level. If the input voltage drops below the VUVLO_FALLING threshold, the regulator turns off. After the AVIN pin voltage rises above the VUVLO_RISING threshold, the soft start period initiates, and the regulator is enabled. For external synchronization, connect the SYNC/FREQ pin to a suitable clock source. The PLL locks to an input clock within the range specified by fSYNC. Table 6. SYNC/FREQ Pin Options SYNC/FREQ Pin High Low External Clock Switching Frequency 2.4 MHz 1.2 MHz 1x clock frequency INTERNAL REGULATORS The internal VREG regulator in the ADP5073 provides a stable power supply for the internal circuitry. The VREG supply provides a high signal for device configuration pins but must not be used to supply external circuitry. The VREF regulator provides a reference voltage for the inverting regulator feedback network to ensure a positive feedback voltage on the FB pin. A current-limit circuit is included for both internal regulators to protect the circuit from accidental loading. Rev. A | Page 10 of 17 Data Sheet ADP5073 PRECISION ENABLING The ADP5073 has an enable pin that features a precision enable circuit with an accurate reference voltage. This reference allows the ADP5073 to be sequenced easily from other supplies. It can also be used as a programmable UVLO input by using a resistor divider. The enable pin has an internal pull-down resistor that defaults to off when the pin is floating. When the voltage at the enable pin is greater than the VTH_H reference level, the regulator is enabled. SOFT START The regulator in the ADP5073 includes soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current. The soft start time is internally set to the fastest rate when the SS pin is open. Connecting a resistor between SS and ground allows the adjustment of the soft start delay. The ADP5073 uses programmable output driver slew rate control circuitry. This circuitry reduces the slew rate of the switching node as shown in Figure 22, resulting in reduced ringing and lower EMI. To program the slew rate, connect the SLEW pin to the VREG pin for normal mode, to the GND pin for slow mode, or leave it open for fast mode. This logic allows the use of an open-drain output from a noise sensitive device to switch the slew rate from fast to slow, for example, during analog-to-digital converter (ADC) sampling. Note that slew rate control causes a trade-off between efficiency and low EMI. SLOWEST OVERVOLTAGE PROTECTION An overvoltage protection mechanism is present on the FB pin for the inverting regulator. When the voltage on the FB pin drops below the VOV threshold, the switching stops until the voltage rises above the threshold. This functionality is enabled after the soft start period has elapsed. POWER GOOD The ADP5073 provides an open-drain power-good output to indicate when the output voltage reaches a target level. SLEW RATE CONTROL FASTEST When the peak inductor current exceeds the current-limit threshold, the power MOSFET switch is turned off for the remainder of that switch cycle. If the peak inductor current continues to exceed the overcurrent limit, the regulator enters hiccup mode. The regulator stops switching and then restarts with a new soft start cycle after tHICCUP and repeats until the overcurrent condition is removed. A pull-up voltage must be provided on the PWRGD pin through an external resistor to provide a high output when the power is good. The pull-up voltage is typically sourced from the VREG pin, although an external supply may be used with a maximum voltage of VDS_PG (MAX). The power-good FET pulls down when the supply on the PVIN pin rises above VPG (SUPPLY) and the FET remains on until the enable is brought high and soft start has completed. Note that if an external supply is used, the power-good output may be high until PVIN reaches VDS_PG (MAX). As soon as the device is enabled and soft start is complete, the power-good function monitors the voltage on the FB pin. If the voltage VREF - VFB is greater than the VPG (GOOD) threshold, the power-good FET turns off, allowing the power-good output to be pulled up to VREG or an external supply signaling a powergood valid condition. If the voltage VREF - VFB is less than the VPG (BAD) threshold, the power-good FET turns on, pulling the output to GND, indicating the power output is not good. 12817-024 THERMAL SHUTDOWN Figure 22. Switching Node at Various Slew Rate Settings CURRENT-LIMIT PROTECTION The inverting regulator in the ADP5073 includes current-limit protection circuitry to limit the amount of forward current allowed through the MOSFET switch. In the event that the ADP5073 junction temperature rises above TSHDN, the thermal shutdown circuit turns off the IC. Extreme junction temperatures can be the result of prolonged high current operation, poor circuit board design, and/or high ambient temperature. Hysteresis is included so that when thermal shutdown occurs, the ADP5073 does not return to operation until the onchip temperature drops below TSHDN - THYS. When resuming from thermal shutdown, a soft start is performed. Rev. A | Page 11 of 17 ADP5073 Data Sheet APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL Output Capacitor The ADP5073 is supported by the ADIsimPowerTM design tool set. ADIsimPower is a collection of tools that produce complete power designs optimized to a specific design goal. These tools allow the user to generate a full schematic, bill of materials, and calculate performance in minutes. ADIsimPower can optimize designs for cost, area, efficiency, and device count while taking into consideration the operating conditions and limitations of the IC and all real external components. The ADIsimPower tool can be found at www.analog.com/adisimpower, and the user can request an unpopulated board through the tool. Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to the output voltage dc bias. COMPONENT SELECTION Feedback Resistors The ADP5073 provides an adjustable output voltage. An external resistor divider sets the output voltage, where the divider output must equal the feedback reference voltage, VFB. To limit the output voltage accuracy degradation due to feedback bias current, ensure that the current through the divider is at least 10 x IFB. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 25 V or 50 V (depending on output) are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. Calculate the worst case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage using the following equation: CEFFECTIVE = CNOMINAL x (1 - TEMPCO) x (1 - DCBIASCO) x (1 - Tolerance) Set the negative output for the inverting regulator by VOUT = VFB - where: CEFFECTIVE is the effective capacitance at the operating voltage. CNOMINAL is the nominal data sheet capacitance. TEMPCO is the worst case capacitor temperature coefficient. DCBIASCO is the dc bias derating at the output voltage. Tolerance is the worst case component tolerance. RFT (VREF - VFB ) RFB where: VOUT is the negative output voltage. VFB is the FB reference voltage. RFT is the feedback resistor from VOUT to FB. RFB is the feedback resistor from FB to VREF. VREF is the VREF pin reference voltage. Table 7 shows recommended values for common output voltages using standard resistor values. Table 7. Recommended Feedback Resistor Values Desired Output Voltage (V) -1.8 -3 -3.3 -4.2 -5 -9 -12 -13 -15 -18 -20 -24 -30 -35 RFT (M) 0.332 0.475 0.523 0.715 1.15 1.62 1.15 2.8 2.32 2.67 2.94 3.16 4.12 5.11 RFB (k) 102 100 102 115 158 133 71.5 162 118 113 113 102 107 115 Actual Output Voltage (V) -1.804 -3.000 -3.302 -4.174 -5.023 -8.944 -12.067 -13.027 -14.929 -18.103 -20.014 -23.984 -30.004 -34.748 To guarantee the performance of the device, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. Capacitors with lower effective series resistance (ESR) and effective series inductance (ESL) are preferred to minimize output voltage ripple. Note that the use of large output capacitors may require a slower soft start to prevent current limit during startup. A 10 F capacitor is suggested as a good balance between performance and size. Input Capacitor Higher value input capacitors help reduce the input voltage ripple and improve transient response. To minimize supply noise, place the input capacitor as close as possible to the AVIN and PVIN pins. A low ESR capacitor is recommended. For stability, the use of a good quality 10 F ceramic capacitor with low dc bias effects is recommended. If the power pins are individually decoupled, it is recommended to use a minimum of a 5.6 F capacitor on the PVIN pin and a 3.3 F capacitor on the AVIN pin. Rev. A | Page 12 of 17 Data Sheet ADP5073 VREG Capacitor For the inductor ripple current in continuous conduction mode (CCM) operation, the input (VIN) and output (VOUT) voltages determine the switch duty cycle (Duty) by the following equation: A 1.0 F ceramic capacitor (CVREG) is required between the VREG pin and GND. | VOUT | + VDIODE Duty = VIN + | VOUT | + VDIODE VREF Capacitor A 1.0 F ceramic capacitor (CVREF) is required between the VREF pin and GND. Soft Start Resistor A resistor (RSS) can be connected between the SS pin and the GND pin to increase the soft start time. The soft start time can be set using this resistor between 4 ms (268 k) and 32 ms (50 k). Leaving the SS pin open selects the fastest time of 4 ms. Figure 23 shows the behavior of this operation. Calculate the soft start time (tSS) using the following formula: tSS = 38.4 x 10-3 - 1.28 x 10-7 x RSS () where VDIODE is the forward voltage drop of the Schottky diode (D1). Determine the dc current in the inductor in CCM (IL1) using the following equation: I OUT (1 - Duty ) I L1 = Using the duty cycle (Duty) and switching frequency (fSW), determine the on time (tON) using the following equation: where 50 k RSS 268 k. t ON = SOFT START TIMER Duty f SW The inductor ripple current (IL1) in steady state is calculated by 32ms I L1 = VIN x t ON L1 Solve for the inductance value (L1) using the following equation: 4ms R2 R1 SOFT START RESISTOR L1 = 12817-025 SS PIN OPEN Figure 23. Soft Start Behavior VIN x t ON I L1 Assuming an inductor ripple current of 30% of the maximum dc current in the inductor results in Diodes A Schottky diode with low junction capacitance is recommended for D1. At higher output voltages and especially at higher switching frequencies, the junction capacitance is a significant contributor to efficiency. Higher capacitance diodes also generate more switching noise. As a guide, a diode with less than 40 pF junction capacitance is preferred when the output voltage is in the range of -5 V to -37 V. Inductor Selection The inductor stores energy during the on time of the power switch, and transfers that energy to the output through the output rectifier during the off time. To balance the trade-offs between small inductor current ripple and efficiency, inductance values in the range of 1 H to 22 H are recommended. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in a higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. A peak-to-peak inductor ripple current close to 30% of the maximum dc current in the inductor typically yields an optimal compromise. L1 = VIN x t ON x (1 - Duty ) 0.3 x I OUT Ensure that the peak inductor current (the maximum input current plus half the inductor ripple current) is below the rated saturation current of the inductor. Likewise, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. When operating the ADP5073 inverting regulator in CCM, for stable current mode operation, ensure that the selected inductance is equal to or greater than the minimum calculated inductance, LMIN, for the application parameters in the following equation: 0.27 L1 > L MIN = VIN x - 0.33 (H) (1 - Duty ) Table 9 suggests a series of inductors to use with the ADP5073 inverting regulator. For the smallest solution size, inductors with a saturation current below ILIM may be used when the output current in the application is such that the inductor current stays below the saturated region. Rev. A | Page 13 of 17 ADP5073 Data Sheet Loop Compensation The ADP5073 uses external components to compensate the regulator loop, allowing the optimization of the loop dynamics for a given application. It is recommended to use the ADIsimPower tool to calculate compensation components. The inverting converter, produces a right half plane zero in the regulation feedback loop. This feedback loop requires compensating the regulator such that the crossover frequency occurs well below the frequency of the right half plane zero. The right half plane zero frequency is determined by the following equation: where fC is the crossover frequency. To solve for RC, use the following equation: RC = RLOAD(1 - Duty) 2 2 x L1 x Duty 2 x f C x COUT x |VOUT | x (VIN + (2 x | VOUT |) VFB x VIN x G M x GCS where GCS = 6.25 A/V. where: fZ (RHP) is the right half plane zero frequency. RLOAD is the equivalent load resistance or the output voltage divided by the load current. Using typical values for VFB and GM results in RC = |VOUT | + VDIODE Duty = VIN + |VOUT | + VDIODE where VDIODE is the forward voltage drop of the Schottky diode (D1). To stabilize the regulator, ensure that the regulator crossover frequency is less than or equal to one-tenth of the right half plane zero frequency. The regulator loop gain is AVL VIN VFB x x GM x |VOUT | (VIN + 2 x | VOUT |) 1 RC x GCS x =1 2 x f C x COUT AVL = 4188 x f C x COUT x | VOUT | x (VIN + (2 x | VOUT |) VIN For better accuracy, it is recommended to use the value of output capacitance (COUT) that takes into account the capacitance reduction from dc bias in the calculation for RC. After the compensation resistor is known, set the zero formed by CC and RC to one-fourth of the crossover frequency, or CC = 2 x f C x RC where CC is the compensation capacitor. VIN V = FB x x GM x |VOUT | (VIN + 2 x | VOUT |) FB ERROR AMPLIFIER COMP gM REF ROUT || Z COMP x GCS x Z OUT RC CB CC where: AVL is the regulator loop gain. VFB is the feedback regulation voltage. VOUT is the regulated negative output voltage. VIN is the input voltage. GM is the error amplifier transconductance gain. ROUT is the output impedance of the error amplifier and is 33 M. ZCOMP is the impedance of the series RC network from COMP to GND. GCS is the current sense transconductance gain (the inductor current divided by the voltage at COMP), which is internally set by the ADP5073 and is 6.25 A/V. ZOUT is the impedance of the load in parallel with the output capacitor. To determine the crossover frequency, it is important to note that, at that frequency, the compensation impedance (ZCOMP) is dominated by a resistor, RC, and the output impedance (ZOUT) is dominated by the impedance of the output capacitor (COUT). 12817-026 f Z (RHP) = Therefore, when solving for the crossover frequency, the equation (by definition of the crossover frequency) is simplified to Figure 24. Compensation Components The optional capacitor, CB, is chosen to cancel the zero introduced by the ESR of the output capacitor. For low ESR capacitors such as ceramic chip capacitors, CB can be omitted from the design. Solve for CB as follows: CB = ESR x COUT RC For optimal transient performance, RC and CC may need to be adjusted by observing the load transient response of the ADP5073. For most applications, RC is within the range of 1 k to 200 k, and CC is within the range of 1 nF to 68 nF. Rev. A | Page 14 of 17 Data Sheet ADP5073 COMMON APPLICATIONS Table 8. Recommended Common Components Selections Table 8 and Table 9 list a number of common component selections for typical VIN and VOUT conditions. These have been bench tested and provide an off the shelf solution. To optimize components for an application, it is recommended to use the ADIsimPower tool set. Reference CIN CVREG CVREF Value (F) 10 1 1 Part Number TMK316B7106KL-TD GRM188R71A105KA61D GRM188R71A105KA61D Manufacturer Taiyo Yuden Murata Murata Figure 25 shows the schematic referenced by Table 8 and Table 9 with example component values for a +5 V input to a -15 V output. Table 8 shows the components common to all VIN and VOUT conditions. CVREF 1F AVIN PVIN CIN 10F RFB 158k ADP5073 FB RFT 1.15M ON CVREG 1F OFF EN D1 DFLS240L VREG SS RPG 1M PWRGD PWRGD COMP CC 470nF VOUT -5V SW RC 240 COUT 10F L1 4.7H SLEW SYNC/FREQ 12817-027 VIN +12V VREF GND Figure 25. Typical +12 V Input to -5 V Output, 1.2 MHz Application Table 9. Recommended Inverting Regulator Components VIN (V) 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 12 12 12 12 12 12 VOUT (V) -2.5 -2.5 -3.3 -3.3 -5 -5 -5 -5 -15 -15 -30 -30 -2.5 -2.5 -5 -5 -15 -15 Freq. (MHz) 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 1.2 2.4 L1 (H) 4.7 2.2 4.7 2.2 4.7 3.3 6.8 3.3 10 5.6 10 10 6.8 3.3 10 5.6 22 10 L1, Coilcraft(R) XAL4030-472ME_ XAL4020-222ME_ XAL4030-472ME XAL4020-222ME_ XAL4030-472ME XAL4030-332ME_ XAL4030-682ME_ XAL4030-332ME_ XAL4040-103ME_ LPS5030-562MR_ XAL4040-103ME_ XAL4040-103ME_ XAL4030-682ME_ XAL4030-332ME_ XAL4040-103ME_ LPS5030-562MR_ XAL5050-223ME_ XAL4040-103ME_ COUT (F) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 COUT, Murata GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L GRM32ER71H106KA12L Rev. A | Page 15 of 17 D1, Diodes, Inc. DFLS240L DFLS240L DFLS240L DFLS240L DFLS240L DFLS240L DFLS240L DFLS240L DFLS240 DFLS240 DFLS240 DFLS240 DFLS240L DFLS240L DFLS240L DFLS240L DFLS240 DFLS240 RFT (M) 0.432 0.432 0.532 0.532 1.15 1.15 1.15 1.15 2.32 2.32 4.12 4.12 0.432 0.432 1.15 1.15 2.32 2.32 RFB (k) 107 107 102 102 158 158 158 158 118 118 107 107 107 107 158 158 118 118 CC (nF) 150 33 68 15 22 12 47 10 6.8 2.2 1.5 1 220 47 68 20 22 3.3 RC (k) 1 2.2 2 4.3 4.7 6.8 3 6.8 20 36 91 91 0.68 1.3 2 3.3 9 20 ADP5073 Data Sheet LAYOUT CONSIDERATIONS PCB layout is important for all switching regulators but is particularly important for regulators with high switching frequencies. To achieve high efficiency, good regulation, good stability, and low noise, a well designed PCB layout is required. Follow these guidelines when designing PCBs: 14mm VOUT GND COUT VIN D1 CIN L1 CVREG U1 GND CC CVREF RC RFT RFB 12817-028 Keep the input bypass capacitor, CIN, close to the PVIN pin and the AVIN pin. Route each of these pins individually to the pad of this capacitor to minimize noise coupling between the power inputs, rather than connecting the two pins at the device. A separate capacitor can be used on the AVIN pin for the best noise performance. Keep the high current paths as short as possible. These paths include the connections between CIN, L1, D1, COUT, and GND and their connections to the ADP5073. Keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and EMI. 18mm Avoid routing high impedance traces near any node connected to the SW pin or near Inductor L1 to prevent radiated switching noise injection. Place the feedback resistors as close to the FB pin as possible to prevent high frequency switching noise injection. Route a trace to RFT directly from the COUT pad for optimum output voltage sensing. Place the compensation components as close as possible to COMP. Do not share vias to the ground plane with the feedback resistors to avoid coupling high frequency noise into the sensitive COMP pin. Place the CVREF and CVREG capacitors as close to the VREG and VREF pins as possible. Ensure that short traces are used between VREF and RFB. Figure 26. Suggested Layout for 18 mm x 14 mm, +12 V Input to -5 V Output Application (Dashed Line Is Connected on the Internal Layer of the PCB; Other Vias Connected to the Ground Plane; SS, EN, PWRGD, SLEW, and SYNC/FREQ Connections Not Shown for Clarity and Are Typically Connected on an Internal Layer) Rev. A | Page 16 of 17 Data Sheet ADP5073 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.23 0.18 0.50 BSC 13 PIN 1 INDICATOR AREA OPTIONS 16 (SEE DETAIL A) 12 1 1.75 1.60 SQ 1.45 EXPOSED PAD 9 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-005138 SEATING PLANE 0.50 0.40 0.30 4 8 5 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 02-23-2017-E PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm x 3 mm Body and 0.75 mm Package Height (CP-16-22) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5073ACPZ-R7 ADP5073CP-EVALZ 1 Temperature Range -40C to +125C Package Description 16-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. (c)2015-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12817-0-10/17(A) Rev. A | Page 17 of 17 Package Option CP-16-22 Branding Code LR1