30 V, 8 MHz, Low Bias Current,
Single-Supply, RRO, Precision Op Amps
Data Sheet
ADA4622-1/ADA4622-2/ADA4622-4
Rev. D Document Feedback
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FEATURES
Next generation of the AD820/AD822/AD824
Wide gain bandwidth product: 8 MHz typical
High slew rate
23 V/µs typical (low to high)
−18 V/µs typical (high to low)
Low input bias current: ±10 pA maximum at TA = 25°C
Low offset voltage
A grade: ±0.8 mV maximum at TA = 25°C
B grade: ±0.35 mV maximum at TA = 25°C
Low offset voltage drift
A grade: ±2 µV/°C typical, ±15 µV/°C maximum
B grade: ±2 µV/°C typical, ±5 µV/°C maximum
Input voltage range includes Pin V−
Rail-to-rail output
Electromagnetic interference rejection ratio (EMIRR)
90 dB typical at f = 1000 MHz and f = 2400 MHz
Industry-standard package and pinouts
APPLICATIONS
High output impedance sensor interfaces
Photodiode sensor interfaces
Transimpedance amplifiers
ADC drivers
Precision filters and signal conditioning
PIN CONFIGURATION
1
2
3
4
–IN A
+IN A
V–
OUT A
8
7
6
5
OUT B
–IN B
+I N B
V+
13502-001
ADA4622-2
(No t t o Scal e)
TOP VIEW
Figure 1. 8-Lead Mini Small Outline Package [MSOP] Pin Configuration
(See the Pin Configurations and Function Descriptions Section
for Additional Pin Configurations)
GENERAL DESCRIPTION
The ADA4622-1/ADA4622-2/ADA4622-4 are the next generation
of the AD820/AD822/AD824 single-supply, rail-to-rail output
(RRO), precision junction field effect transistors (JFET) input
op amps. The ADA4622-1/ADA4622-2/ADA4622-4 include
many improvements that make them desirable as upgrades
without compromising the flexibility and ease of use that makes
the AD820/AD822/AD824 useful for a wide variety of applications.
The input voltage range includes the negative supply and the
output swings rail-to-rail. Input EMI filters increase the signal
robustness in the face of closely located switching noise sources.
The speed, in terms of bandwidth and slew rate, increases along
with a strong output drive to improve settling time performance
and enables the devices to drive the inputs of modern single-
ended, successive approximation register (SAR) analog-to-
digital converters (ADCs).
Voltage noise is reduced; although the supply current remains
the same as the AD820/AD822/AD824, broadband noise is
reduced by 25%, and 1/f is reduced by half. DC precision in the
ADA4622-1/ADA4622-2/ADA4622-4 improved from the
AD820/AD822/AD824 with half the offset and a maximum
thermal drift specification added to the ADA4622-1/ADA4622-2/
ADA4622-4. The common-mode rejection ratio (CMRR) is
improved from the AD820/AD822/AD824 to make the
ADA4622-1/ADA4622-2/ADA4622-4 more suitable when used in
noninverting gain and difference amplifier configurations.
The ADA4622-1/ADA4622-2/ADA4622-4 are specified for
operation over the extended industrial temperature range of −40°C
to +125°C, and operate from 5 V to 30 V, with specifications at
+5 V, ±5 V, and ±15 V. The ADA4622-1 is available in a 5-lead
SOT-23 package and an 8-lead LFCSP package. The ADA4622-2
is available in an 8-lead SOIC package, an 8-lead MSOP package,
and an 8-lead LFCSP package. The ADA4622-4 is available in a
14-lead SOIC and a 16-lead, 4 × 4 mm LFCSP.
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 2 of 37
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configuration ............................................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics, VSY = ±15 V ...................................... 3
Electrical Characteristics, VSY = ±5 V ........................................ 5
Electrical Characteristics, VSY = 5 V .......................................... 7
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 14
Theory Of Operation ..................................................................... 26
Input Characteristics .................................................................. 26
Output Characteristics............................................................... 27
Shutdown Operation .................................................................. 28
Applications Information .............................................................. 29
Recommended Power Solution ................................................ 29
Maximum Power Dissipation ................................................... 29
Second-Order Low-Pass Filter.................................................. 29
Wideband Photodiode Preamplifier ........................................ 29
Peak Detector .............................................................................. 32
Multiplexing Inputs .................................................................... 32
Full Wave Rectifier ..................................................................... 33
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 36
REVISION HISTORY
4/2018—Rev. C to Rev. D
Changes to Figure 69 Caption to Figure 71 Caption ...................... 24
Updated Outline Dimensions, CP-16-20 .................................... 36
Changes to Ordering Guide .......................................................... 36
7/2017—Rev. B to Rev. C
Added ADA4622-4 ........................................................ Throughout
Changes to Features Section, General Description Section, and
Figure 2 Caption ................................................................................. 1
Deleted Figure 1; Renumbered Sequentially ................................. 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to Table 5 ............................................................................ 9
Added Figure 7 and Table 10; Renumbered Sequentially ......... 12
Added Figure 8 and Table 11......................................................... 13
Changes to Figure 12 Caption ....................................................... 14
Changes to Figure 25 and Figure 26 ............................................. 16
Changes to Figure 28, Figure 29, Figure 30 Caption, Figure 31
Caption, and Figure 32 Caption ................................................... 17
Changes to Figure 33 Caption ....................................................... 18
Changes to Figure 53 and Figure 54 ............................................. 21
Changes to Figure 80 ...................................................................... 26
Changes to Figure 84 and Figure 85 ............................................. 27
Changes to Figure 92 and Figure 94 ............................................. 29
Changes to Figure 97 ...................................................................... 31
Changes to Figure 99 and Peak Detector Section ...................... 32
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 37
2/2017—Rev. A to Rev. B
Added ADA4622-1 ........................................................ Throughout
Changed AD822 to AD820/AD822 ............................ Throughout
Changed ADA4622-2 to ADA4622-1/ADA4622-2 .. Throughout
Changed 7.5 MHz to 8 MHz in Product Title .............................. 1
Added Figure 1; Renumbered Sequentially ................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 5
Changes to Table 3 ............................................................................. 7
Changes to Table 5 ............................................................................. 9
Added Figure 3, Table 6, Figure 4, and Table 7; Renumbered
Sequentially ..................................................................................... 10
Changes to Figure 11 and Figure 12............................................. 12
Added Figure 13 ............................................................................. 12
Added Figure 78 ............................................................................. 23
Added Shutdown Operation and Figure 86 to Figure 89 .......... 26
Added Multiplexing Inputs Section, Figure 99, and Figure 100 ..... 30
Added Full Wave Rectifier Section, Figure 101, and Figure 102 ..... 31
Updated Outline Dimensions ....................................................... 32
Change to Ordering Guide ............................................................ 34
2/2016—Rev. 0 to Rev. A
Added 8-Lead LFCSP ......................................................... Universal
Changes to General Description Section ....................................... 1
Changes to Settling Time to 0.1% Parameter and Settling Time
to 0.01% Parameter, Table 1 ............................................................. 4
Changes to Table 5 ............................................................................. 9
Added Pin Configurations and Function Descriptions Section,
Figure 2, Figure 3, Table 6, Figure 4, and Table 7; Renumbered
Sequentially ..................................................................................... 10
Changes to Figure 9 ........................................................................ 11
Changes to Input Characteristics Section ................................... 23
Changes to Recommended Power Solution Section ................. 25
Changes to Wideband Photodiode Preamplifier Section ......... 26
Change to Figure 85 ....................................................................... 26
Change to Figure 86 ....................................................................... 27
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 30
10/2015—Revision 0: Initial Version
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 3 of 37
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, VSY = ±15 V
Supply voltage (VSY) = ±15 V, common-mode voltage (VCM) = output voltage (VOUT) = 0 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
A Grade +0.04 ±0.8 mV
−40°C < TA < +125°C ±2 mV
B Grade +0.04 ±0.35 mV
ADA4622-1 −40°C < TA < +125°C ±1 mV
ADA4622-2 −40°C < TA < +125°C ±0.8 mV
Offset Voltage Match ±1 mV
Offset Voltage Drift ΔVOS/ΔT
A Grade −40°C < TA < +125°C ±2 ±15 µV/°C
B Grade −40°C < TA < +125°C ±2 ±5 µV/°C
Input Bias Current IB +2 ±10 pA
−40°C < TA < +125°C ±1.5 nA
VCM = −15 V −15 pA
Input Offset Current
I
OS
±10
pA
−40°C < TA < +125°C ±0.5 nA
Input Voltage Range IVR −15.2 +14 V
Common-Mode Rejection Ratio CMRR
A Grade VCM = −15 V to +12 V 84 100 dB
−40°C < T
A
< +125°C
81
dB
B Grade VCM = −15 V to +12 V 87 100 dB
−40°C < TA < +125°C 85 dB
Open-Loop Voltage Gain AVO RL = 10 kΩ, VOUT = −14.5 V to +14.5 V 117 122 dB
−40°C < TA < +125°C 109 dB
RL = 1 kΩ, VOUT = −14 V to +14 V 102 110 dB
−40°C < TA < +125°C 93 dB
Input Capacitance CINDM Differential mode 0.4 pF
CINCM Common mode 3.6 pF
Input Resistance RDIFF Differential mode 1013 Ω
RCM Common mode 1013 Ω
OUTPUT CHARACTERISTICS
Output Voltage
High VOH ISOURCE = 1 mA 14.95 14.97 V
−40°C < T
A
< +125°C
14.9
V
ISOURCE = 15 mA 14.3 14.5 V
−40°C < TA < +125°C 14.1 V
Low VOL ISINK = 1 mA −14.955 −14.935 V
−40°C < TA < +125°C −14.88 V
ISINK = 15 mA −14.685 −14.55 V
−40°C < TA < +125°C −14.25 V
Output Current IOUT VDROPOUT < 1 V 20 mA
Short-Circuit Current ISC Sourcing 42 mA
Sinking −51 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, gain (AV) = 1 0.1 Ω
AV = 10 0.4 Ω
AV = 100 3 Ω
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 4 of 37
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4 V to ±18 V 87 103 dB
−40°C < TA < +125°C 81 dB
Supply Current per Amplifier ISY
ADA4622-1/ADA4622-4 715 750 μA
−40°C < TA < +125°C 775 μA
ADA4622-2 665 700 μA
−40°C < TA < +125°C 725 μA
Shutdown Current ADA4622-1 only 60 μA
DYNAMIC PERFORMANCE
Slew Rate SR VOUT = ±12.5 V, RL = 2 kΩ, load capacitor
(CL) = 100 pF, AV = 1
Low to high transition 23 V/μs
High to low transition −18 V/μs
Gain Bandwidth Product GBP AV = 100, CL = 35 pF 8 MHz
Unity-Gain Crossover UGC AV = 1 7 MHz
−3 dB Bandwidth −3 dB AV = 1 15.5 MHz
Phase Margin ФM 53 Degrees
Settling Time tS Input voltage (VIN) = 10 V step, RL = 2 kΩ,
CL = 15 pF, AV = −1
To 0.1% 1.5 μs
To 0.01% 2 μs
EMI REJECTION RATIO EMIRR VIN = 100 mV p-p
f = 1000 MHz 90 dB
f = 2400 MHz 90 dB
NOISE PERFORMANCE
Voltage Noise eN p-p 0.1 Hz to 10 Hz 0.75 μV p-p
Voltage Noise Density eN f = 10 Hz 30 nV/√Hz
f = 100 Hz 15 nV/√Hz
f = 1 kHz 12.5 nV/√Hz
f = 10 kHz 12 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 fA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz,
VIN = 7 V rms at 1 kHz
Bandwidth (BW) = 80 kHz 0.0003 %
BW = 500 kHz 0.00035 %
MATCHING SPECIFICATIONS
Maximum Offset Voltage over
Temperature
0.5 mV
Offset Voltage Temperature Drift 2.5 μV/°C
Input Bias Current 0.5 5 pA
CROSSTALK CS R
L = 5 kΩ, VIN = 20 V p-p
ADA4622-1/ADA4622-2 f = 1 kHz −112 dB
f = 100 kHz −72 dB
ADA4622-4 f = 1 kHz −106 dB
f = 100 kHz −66 dB
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 5 of 37
ELECTRICAL CHARACTERISTICS, VSY = ±5 V
VSY = ±5 V, VCM = VOUT = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
A Grade +0.04 ±0.8 mV
−40°C < TA < +125°C ±2 mV
B Grade +0.04 ±0.35 mV
ADA4622-1 −40°C < TA < +125°C ±1 mV
ADA4622-2 −40°C < TA < +125°C ±0.8 mV
Offset Voltage Match ±1 mV
Offset Voltage Drift ΔVOS/ΔT
A Grade −40°C < TA < +125°C ±2 ±15 µV/°C
B Grade −40°C < TA < +125°C ±2 ±5 µV/°C
Input Bias Current IB +2 ±10 pA
−40°C < TA < +125°C ±1.5 nA
VCM = V− −5 pA
Input Offset Current IOS ±10 pA
−40°C < T
A
< +125°C
±0.5
nA
Input Voltage Range IVR −5.2 +4 V
Common-Mode Rejection Ratio CMRR
A Grade VCM = − 5 V to +2 V 75 91 dB
−40°C < TA < +125°C 73 dB
B Grade VCM = − 5 V to +2 V 78 91 dB
−40°C < TA < +125°C 75 dB
Open-Loop Voltage Gain AVO RL = 10 kΩ, VOUT = −4.4 V to +4.4 V 113 118 dB
−40°C < TA < +125°C 105 dB
RL = 1 kΩ, VOUT = −4.4 V to +4.4 V 100 105 dB
−40°C < TA < +125°C 91 dB
Input Capacitance CINDM Differential mode 0.4 pF
C
INCM
Common mode
3.6
pF
Input Resistance RDIFF Differential mode 1013 Ω
RCM Common mode 1013 Ω
OUTPUT CHARACTERISTICS
Output Voltage
High VOH ISOURCE = 1 mA 4.95 4.97 V
−40°C < TA < +125°C 4.9 V
ISOURCE = 15 mA 4.3 4.51 V
−40°C < TA < +125°C 4.1 V
Low VOL ISINK = 1 mA −4.955 −4.935 V
−40°C < TA < +125°C −4.88 V
ISINK = 15 mA −4.685 −4.55 V
−40°C < TA < +125°C −4.25 V
Output Current IOUT VDROPOUT < 1 V 20 mA
Short-Circuit Current
I
SC
Sourcing
31
mA
Sinking −40 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
AV = 10 0.4 Ω
AV = 100 4 Ω
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 6 of 37
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4 V to ±18 V 87 103 dB
−40°C < TA < +125°C 81 dB
Supply Current per Amplifier ISY
ADA4622-1/ADA4622-4 660 725 μA
−40°C < TA < +125°C 750 μA
ADA4622-2 610 675 μA
−40°C < TA < +125°C 700 μA
Shutdown Current ADA4622-1 only 50 μA
DYNAMIC PERFORMANCE
Slew Rate SR VOUT = ±3 V, RL = 2 kΩ, CL = 100 pF,
AV = 1
Low to high transition 21 V/μs
High to low transition −16 V/μs
Gain Bandwidth Product GBP AV = 100, CL = 35 pF 7.8 MHz
Unity-Gain Crossover UGC AV = 1 6.5 MHz
−3 dB Bandwidth −3 dB AV = 1 10 MHz
Phase Margin ФM 50 Degrees
Settling Time tS VIN = 8 V step, RL = 2 kΩ, CL = 15 pF,
AV = −1
To 0.1% 1.5 μs
To 0.01% 2 μs
EMI REJECTION RATIO EMIRR VIN = 100 mV p-p
f = 1000 MHz 90 dB
f = 2400 MHz 90 dB
NOISE PERFORMANCE
Voltage Noise eN p-p 0.1 Hz to 10 Hz 0.75 μV p-p
Voltage Noise Density eN f = 10 Hz 30 nV/√Hz
f = 100 Hz 15 nV/√Hz
f = 1 kHz 12.5 nV/√Hz
f = 10 kHz 12 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 pA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz,
VIN = 1.5 V rms at 1 kHz
BW = 80 kHz 0.0005 %
BW = 500 kHz 0.0008 %
MATCHING SPECIFICATIONS
Maximum Offset Voltage over
Temperature
0.5 mV
Offset Voltage Temperature Drift 2.5 μV/°C
Input Bias Current 0.5 5 pA
CROSSTALK CS R
L = 5 kΩ, VIN = 6 V p-p
ADA4622-1/ADA4622-2 f = 1 kHz −112 dB
f = 100 kHz −72 dB
ADA4622-4 f = 1 kHz −106 dB
f = 100 kHz −66 dB
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 7 of 37
ELECTRICAL CHARACTERISTICS, VSY = 5 V
VSY = 5 V, VCM = 0 V, VOUT = VSY/2, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS
A Grade +0.04 ±0.8 mV
−40°C < TA < +125°C ±2 mV
B Grade +0.04 ±0.35 mV
ADA4622-1 −40°C < TA < +125°C ±1 mV
ADA4622-2 −40°C < TA < +125°C ±0.8 mV
Offset Voltage Match ±1 mV
Offset Voltage Drift ΔVOS/ΔT
A Grade −40°C < TA < +125°C ±2 ±15 µV/°C
B Grade −40°C < TA < +125°C ±2 ±5 µV/°C
Input Bias Current IB 2 ±10 pA
−40°C < TA < +125°C ±1.5 nA
Input Offset Current IOS ±10 pA
−40°C < TA < +125°C ±0.5 nA
Input Voltage Range
IVR
−0.2
+4
V
Common-Mode Rejection Ratio CMRR
A Grade VCM = 0 V to 2 V 70 87 dB
−40°C < TA < +125°C 67 dB
B Grade VCM = 0 V to 2 V 73 87 dB
−40°C < TA < +125°C 70 dB
Open-Loop Voltage Gain AVO RL = 10 kΩ to V−, VOUT = 0.2 V to 4.6 V 110 115 dB
−40°C < TA < +125°C 99 dB
RL = 1 kΩ to V−, VOUT = 0.2 V to 4.6 V 96 104 dB
−40°C < TA < +125°C 87 dB
Input Capacitance CINDM Differential mode 0.4 pF
CINCM Common mode 3.6 pF
Input Resistance
R
DIFF
Differential mode
10
13
Ω
RCM Common mode 1013 Ω
OUTPUT CHARACTERISTICS
Output Voltage
High VOH ISOURCE = 1 mA 4.95 4.97 V
−40°C < TA < +125°C 4.9 V
ISOURCE = 15 mA 4.3 4.5 V
−40°C < TA < +125°C 4.1 V
Low VOL ISINK = 1 mA 45 65 mV
−40°C < TA < +125°C 120 mV
ISINK = 15 mA 310 450 mV
−40°C < TA < +125°C 750 mV
Output Current IOUT VDROPOUT < 1 V 20 mA
Short-Circuit Current ISC Sourcing 27 mA
Sinking
−35
mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
AV = 10 0.6 Ω
AV = 100 5 Ω
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 8 of 37
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = 4 V to 15 V 80 95 dB
−40°C < TA < +125°C 74 dB
Supply Current per Amplifier ISY
ADA4622-1/ADA4622-4 650 700 μA
−40°C < TA < +125°C 725 μA
ADA4622-2 600 650 μA
−40°C < TA < +125°C 675 μA
Shutdown Current ADA4622-1 only 50 μA
DYNAMIC PERFORMANCE
Slew Rate SR VOUT = 0.5 V to 3.5 V, RL = 2 kΩ,
CL = 100 pF, AV = 1
Low to high transition 20 V/μs
High to low transition −15 V/μs
Gain Bandwidth Product GBP AV = 100, CL = 35 pF 7.2 MHz
Unity-Gain Crossover UGC AV = 1 6 MHz
−3 dB Bandwidth −3 dB AV = 1 9 MHz
Phase Margin ФM 50 Degrees
Settling Time tS VIN = 4 V step, RL = 2 kΩ, CL = 15 pF,
AV = −1
To 0.1% 1.5 μs
To 0.01% 2.0 μs
EMI REJECTION RATIO EMIRR VIN = 100 mV p-p
f = 1000 MHz 90 dB
f = 2400 MHz 90 dB
NOISE PERFORMANCE
Voltage Noise eN p-p 0.1 Hz to 10 Hz 0.75 μV p-p
Voltage Noise Density eN f = 10 Hz 30 nV/√Hz
f = 100 Hz 15 nV/√Hz
f = 1 kHz 12.5 nV/√Hz
f = 10 kHz 12 nV/√Hz
Current Noise Density iN f = 1 kHz 0.8 pA/√Hz
Total Harmonic Distortion + Noise THD + N AV = 1, f = 10 Hz to 20 kHz,
VIN = 0.5 V rms at 1 kHz
BW = 80 kHz 0.0025 %
BW = 500 kHz 0.0025 %
MATCHING SPECIFICATIONS
Maximum Offset Voltage over
Temperature
0.5 mV
Offset Voltage Temperature Drift 2.5 μV/°C
Input Bias Current 0.5 5 pA
CROSSTALK CS R
L = 5 kΩ, VIN = 3 V p-p
ADA4622-1/ADA4622-2 f = 1 kHz −112 dB
f = 100 kHz −72 dB
ADA4622-4 f = 1 kHz −106 dB
f = 100 kHz −66 dB
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 9 of 37
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 36 V
Input Voltage (V−) − 0.3 V to
(V+) + 0.2 V
Differential Input Voltage 36 V
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range
−65°C to +150°C
Lead Temperature, Soldering (10 sec)
300°C
ESD Rating, Human Body Model (HBM) 4 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
Table 5. Thermal Resistance1, 2
Package Type
θ
JA
θ
JC3
Unit
8-Lead SOIC
1-Layer JEDEC Board
N/A
63
°C/W
2-Layer JEDEC Board 120 N/A °C/W
8-Lead MSOP
1-Layer JEDEC Board N/A 115 °C/W
2-Layer JEDEC Board 185 N/A °C/W
8-Lead LFCSP
1-Layer JEDEC Board N/A 63 °C/W
2-Layer JEDEC Board 145 N/A °C/W
2-Layer JEDEC Board with 2 × 2 Vias 55 N/A °C/W
5-Lead SOT-23
1-Layer JEDEC Board N/A 82 °C/W
2-Layer JEDEC Board 339 N/A °C/W
14-Lead SOIC
1-Layer JEDEC Board N/A 42 °C/W
2-Layer JEDEC Board 72 N/A °C/W
16-Lead, 4 × 4 mm LFCSP
1-Layer JEDEC Board
N/A
2.2
°C/W
2-Layer JEDEC Board
48
N/A
°C/W
1 Thermal impedance simulated values are based on a JEDEC thermal test
board. See JEDEC JESD51.
2 N/A means not applicable.
3 For θJC test, 100 μm thermal interface material (TIM) is used. TIM is assumed
to have 3.6 W/mK
ESD CAUTION
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 10 of 37
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
O
UT
1
+IN
3
V–
2
V+
5
–IN
4
ADA4622-1
TOP VIEW
(Not to Scale)
13502-202
Figure 2. 5-Lead SOT-23 Pin Configuration, ADA4622-1
Table 6. 5-Lead SOT-23 Pin Function Descriptions, ADA4622-1
Pin No. Mnemonic Description
1 OUT Output.
2 V− Negative Supply Voltage.
3 +IN Noninverting Input.
4 −IN Inverting Input.
5 V+ Positive Supply Voltage.
13502-203
1
2
3
4
8
7
6
5
ADA4622-1
TOP VIEW
(Not to Scale)
–IN
+IN
V–
NIC
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
V+
OUT
NIC
DISABLE
Figure 3. 8-Lead SOIC Pin Configuration, ADA4622-1
Table 7. 8-Lead SOIC Pin Function Descriptions, ADA4622-1
Pin No. Mnemonic Description
1, 5 NIC Not Internally Connected.
2 −IN Inverting Input.
3 +IN Noninverting Input.
4 V− Negative Supply Voltage.
6 OUT Output.
7 V+ Positive Supply Voltage.
8 DISABLE Disable Input (Active Low).
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 11 of 37
1
2
3
4
–IN A
+IN A
V–
OUT A
8
7
6
5
OUT B
–IN B
+IN B
V+
13502-101
ADA4622-2
(Not to S cale)
TOP VIEW
Figure 4. 8-Lead MSOP Pin Configuration, ADA4622-2
1
2
3
4
8
7
6
5
13502-201
ADA4622-2
(Not t o Scale)
TOP VIEW
–IN A
+IN A
V–
OUT A
OUT B
–IN B
+IN B
V+
Figure 5. 8-Lead SOIC Pin Configuration, ADA4622-2
Table 8. 8-Lead MSOP and 8-Lead SOIC Pin Function Descriptions, ADA4622-2
Pin No. Mnemonic Description
1 OUT A Output, Channel A.
2 −IN A Inverting Input, Channel A.
3
+IN A
Noninverting Input, Channel A.
4 V− Negative Supply Voltage.
5 +IN B Noninverting Input, Channel B.
6 −IN B Inverting Input, Channel B.
7 OUT B Output, Channel B.
8 V+ Positive Supply Voltage.
13502-102
3
+IN A
4V–
1
OUT A
NOTES
1. IT IS RECOMMENDED TO CONNECT THE
EXPOSED PAD TO THE V+ PIN.
2–IN A
6–IN B
5+IN B
8 V+
7OUT B
ADA4622-2
TOP VIEW
(Not to Scal e)
Figure 6. 8-Lead LFCSP Pin Configuration, ADA4622-2
Table 9. 8-Lead LFCSP Pin Function Descriptions, ADA4622-2
Pin No. Mnemonic Description
1 OUT A Output, Channel A.
2 −IN A Inverting Input, Channel A.
3 +IN A Noninverting Input, Channel A.
4
V−
Negative Supply Voltage.
5 +IN B Noninverting Input, Channel B.
6 −IN B Inverting Input, Channel B.
7 OUT B Output, Channel B.
8 V+ Positive Supply Voltage.
EPAD Exposed Pad. It is recommended to connect the exposed pad to the V+ pin.
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 12 of 37
13502-407
12
11
10
1
3
49
2
6
5
7
8
16
15
14
13
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2
. THE EXPOSED PAD MUST BE CONNECTED TO V+.
–IN A
+IN A
V+
+IN B
–IN D
NIC
OUT D
OUT A
NIC
+IN D
V–
+IN C
–IN B
OUT B
OUT C
–IN C
ADA4622-4
TOP VIEW
(Not to Scale)
Figure 7. 16-Lead LFCSP Pin Configuration, ADA4622-4
Table 10. 16-Lead LFCSP Pin Function Descriptions, ADA4622-4
Pin No. Mnemonic Description
1 −IN A Inverting Input, Channel A.
2 +IN A Noninverting Input, Channel A.
3 V+ Positive Supply Voltage.
4 +IN B Noninverting Input, Channel B.
5 −IN B Inverting Input, Channel B.
6 OUT B Output, Channel B.
7 OUT C Output, Channel C.
8 −IN C Inverting Input, Channel C.
9 +IN C Noninverting Input, Channel C.
10 V− Negative Supply Voltage.
11 +IN D Noninverting Input, Channel D.
12 −IN D Inverting Input, Channel D.
13, 16 NIC Not Internally Connected.
14 OUT D Output, Channel D.
15 OUT A Output, Channel A.
EPAD Exposed Pad. The exposed pad must be connected to the V+ pin.
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 13 of 37
OUT A
1
–IN A
2
+IN A
3
V+
4
OUT D
14
–IN D
13
+IN D
12
V–
11
+IN B
5
+IN C
10
–IN B
6
–IN C
9
OUT B
7
OUT C
8
13502-408
ADA4622-4
(No t t o Scal e)
TOP VIEW
Figure 8. 14-Lead SOIC Pin Configuration, ADA4622-4
Table 11. 14-Lead SOIC Pin Function Descriptions, ADA4622-4
Pin No. Mnemonic Description
1 OUT A Output, Channel A.
2 −IN A Inverting Input, Channel A.
3 +IN A Noninverting Input, Channel A.
4 V+ Positive Supply Voltage.
5 +IN B Noninverting Input, Channel B.
6 −IN B Inverting Input, Channel B.
7 OUT B Output, Channel B.
8 OUT C Output, Channel C.
9 −IN C Inverting Input, Channel C.
10
+IN C
Noninverting Input, Channel C.
11 V− Negative Supply Voltage.
12 +IN D Noninverting Input, Channel D.
13 −IN D Inverting Input, Channel D.
14 OUT D Output, Channel D.
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 14 of 37
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
NUMBER OF AMPLIFIERS
V
OS
(mV)
V
CM
= 0V
V
OUT
= 0V
V
SY
= ±15V
13502-002
Figure 9. Input Offset Voltage (VOS) Distribution, VSY = ±15 V
NUMBER OF AMPLIFIERS
V
OS
(mV)
V
CM
= 0V
V
OUT
= 0V
V
SY
= ±5V
13502-003
Figure 10. Input Offset Voltage (VOS) Distribution, VSY = ±5 V
NUMBER OF AMPLIFIERS
V
OS
(mV)
V
CM
= 0V
V
OUT
= 2.5V
V
SY
= 5V
13502-004
Figure 11. Input Offset Voltage (VOS) Distribution, VSY = 5 V
13502-011
–10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0
NUMBER OF AMPLIFIERS
TCV
OS
(µV/°C)
V
SY
= ±15V
Figure 12. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C),
VSY = ±15 V
13502-012
–10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
V
SY
= ±5V
Figure 13. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C),
VSY = ±5 V
13502-013
–10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0
TCV
OS
(µV/°C)
0
5
10
15
20
25
NUMBER OF AMPLIFIERS
V
SY
= 5V
Figure 14. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C),
VSY = 5 V
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 15 of 37
–1000
–500
0
500
1000
–15 –10 –5 0510 15
V
OS
(µV)
V
CM
(V)
13502-008
V
SY
= ±15V
Figure 15. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = ±15 V
–1000
–500
0
500
1000
–5 –4 –3 –2 –1 012345
V
OS
(µV)
V
CM
(V)
13502-009
V
SY
= ±5V
Figure 16. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = ±5 V
–1000
–500
0
500
1000
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V
OS
(µV)
V
CM
(V)
13502-010
V
SY
= 5V
Figure 17. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 5 V
NUMBER OF AMPLIFIERS
I
B
(p A)
V
CM
= 0V
V
OUT
= 0V
13502-014
V
SY
= ±15V
Figure 18. Input Bias Current (IB) Distribution, VSY = ±15 V
I
B
(p A)
NUMBER OF AMPLIFIERS
V
CM
= 0V
V
OUT
= 0V
V
SY
= ±5V
13502-015
Figure 19. Input Bias Current (IB) Distribution, VSY = ±5 V
NUMBER O F AMPLIFIERS
I
B
(p A)
V
CM
= 0V
V
SY
= 5V
V
OUT
= 2.5V
13502-016
Figure 20. Input Bias Current (IB) Distribution, VSY = 5 V
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 16 of 37
–30
–20
–10
0
10
–15 –10 –5 0 5 10 15
I
B
(pA)
V
CM
(V)
V
SY
= ±15V
13502-017
Figure 21. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM),
VSY = ±15 V
–6
–4
–2
0
2
4
–5 –4 –3 –2 –1 0 1 2 3 4 5
I
B
(pA)
V
CM
(V)
V
SY
= ±5V
13502-018
Figure 22. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM),
VSY = ±5 V
0 0.51.01.52.02.53.03.54.04.55.0
I
B
(pA)
V
CM
(V)
V
SY
= 5V
13502-019
Figure 23. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM),
VSY = 5 V
V
OL
(V)
I
LOAD
(A)
–40°C
+25°C
+85°C
+125°C
V
SY
= ±15V
13502-020
Figure 24. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±15 V
1m
10m
100m
1
10
1µ 10µ 100µ 1m 10m 100m
VOL (V)
ILOAD (A)
–40°C
+25°C
+85°C
+125°C
13502–021
VSY = ±5V
Figure 25. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±5 V
1m
10m
100m
1
10
1µ 10µ 100µ 1m 10m 100m
VOL (V)
ILOAD (A)
–40°C
+25°C
+85°C
+125°C
13502–022
VSY = 5V
Figure 26. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = 5 V
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 17 of 37
VOH (V)
ILOAD (A)
–40°C
+25°C
+85°C
+125°C
V
SY
= ±15V
13502-023
Figure 27. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±15 V
1m
10m
100m
1
10
1µ 10µ 100µ 1m 10m 100m
V
OH
(V)
I
LOAD
(A)
–40°C
+25°C
+85°C
+125°C
13502–024
V
SY
= ±5V
Figure 28. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = ±5 V
1m
10m
100m
1
10
1µ 10µ 100µ 1m 10m 100m
V
OH
(V)
I
LOAD
(A)
–40°C
+25°C
+85°C
+125°C
13502–025
V
SY
= 5V
Figure 29. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD)
over Temperature, VSY = 5 V
GAI N (dB)
LOAD RESISTANCE (kΩ)
V
SY
= 5V
V
SY
= ±5V
V
SY
= ±15V
13502-026
Figure 30. Open-Loop Voltage Gain (AVO) vs. Load Resistance
–135
–90
–45
0
45
90
135
180
225
–40
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PHASE ( Degrees)
GAI N ( dB)
FREQUENCY (Hz)
VSY = ±15V
13502-027
Figure 31. Open-Loop Voltage Gain (AVO) and Phase vs. Frequency,
VSY = ±15 V
–135
–90
–45
0
45
90
135
180
225
–40
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PHASE ( Degrees)
GAI N ( dB)
FREQUENCY (Hz)
V
SY
= ±5V
13502-028
Figure 32. Open-Loop Voltage Gain (AVO) and Phase vs. Frequency,
VSY = ±5 V
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 18 of 37
–135
–90
–45
0
45
90
135
180
225
–40
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PHASE (Degrees)
GAIN (dB)
FREQUENCY (Hz)
V
SY
= 5V
13502-029
Figure 33. Open-Loop Voltage Gain (AVO) and Phase vs. Frequency, VSY = 5 V
–20
–10
0
10
20
30
40
50
60
10 100 1k 10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
V
SY
= ±15V
A
V
= +100
A
V
= +10
A
V
= +1
13502-030
Figure 34. Closed-Loop Gain (AV) vs. Frequency, VSY = ±15 V
–20
–10
0
10
20
30
40
50
60
10 100 1k 10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
V
SY
= ±5V
A
V
= +100
A
V
= +10
A
V
= +1
13502-031
Figure 35. Closed-Loop Gain (AV) vs. Frequency, VSY = ±5 V
–20
–10
0
10
20
30
40
50
60
10 100 1k 10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
V
SY
= 5V
A
V
= +100
A
V
= +10
A
V
= +1
13502-032
Figure 36. Closed-Loop Gain (AV) vs. Frequency, VSY = 5 V
0.01
0.1
1
10
100
1000
10 100 1k 10k 100k 1M 10M
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
GAIN = 1
GAIN = 10
GAIN = 100
13502-033
V
SY
= ±15V
Figure 37. Output Impedance vs. Frequency, VSY = ±15 V
0.01
0.1
1
10
100
1000
10 100 1k 10k 100k 1M 10M
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
GAIN = 1
GAIN = 10
GAIN = 100
13502-034
V
SY
= ±5V
Figure 38. Output Impedance vs. Frequency, VSY = ±5 V
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 19 of 37
0.01
0.1
1
10
100
1000
10 100 1k 10k 100k 1M 10M
OUTPUT IMPEDANCE (Ω)
FREQUENCY (Hz)
GAIN = 1
GAIN = 10
GAIN = 100
13502-035
VSY = 5V
Figure 39. Output Impedance vs. Frequency, VSY = 5 V
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
CMRR (dB)
FREQUENCY (Hz)
13502-036
VSY = ± 15V
Figure 40. CMRR vs. Frequency, VSY = ±15 V
0
20
40
60
80
120
100
140
10 100 1k 10k 100k 1M 10M 100M
CMRR (dB)
FREQUENCY (Hz)
13502-037
VSY = ± 5V
Figure 41. CMRR vs. Frequency, VSY = ±5 V
0
20
40
60
80
100
10 100 1k 10k 100k 1M 10M 100M
CMRR (dB)
FREQUENCY (Hz)
13502-038
VSY = 5V
Figure 42. CMRR vs. Frequency, VSY = 5 V
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PSRR (dB)
FREQUENCY (Hz)
V
SY
= ±15V
13502-039
–PSRR
+PSRR
Figure 43. PSRR vs. Frequency, VSY = ±15 V
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PSRR (dB)
FREQUENCY (Hz)
V
SY
= ±5V
13502-040
–PSRR
+PSRR
Figure 44. PSRR vs. Frequency, VSY = ±5 V
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 20 of 37
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PSRR (dB)
FREQUENCY (Hz)
V
SY
= 5V
13502-041
–PSRR
+PSRR
Figure 45. PSRR vs. Frequency, VSY = 5 V
0
5
10
15
20
25
30
35
40
45
50
1 10 100 1000
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
+OS
–OS
13502-042
V
SY
= ±15V
Figure 46. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = ±15 V
0
5
10
15
20
25
30
35
40
45
50
1 10 100 1000
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
+OS
–OS
13502-043
V
SY
= ±5V
Figure 47. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = ±5 V
0
10
20
30
40
50
60
1 10 100 1000
OVERSHOOT (%)
LOAD CAPACITANCE (pF)
+OS
–OS
13502-044
V
SY
= 5V
Figure 48. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = 5 V
–15
–10
–5
0
5
10
15
012345678910
VOLTAGE (V)
TIME (µs)
V
SY
= ±15V
V
IN
= ±10V
13502-045
Figure 49. Large Signal Transient Response, VSY = ±15 V
–4
–2
0
2
4
012345678910
VOLTAGE (V)
TIME (µs)
V
SY
= ±5V
V
IN
= ±3V
13502-046
Figure 50. Large Signal Transient Response, VSY = ±5 V
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 21 of 37
0
1
2
3
4
012345678910
VOLTAGE (V)
TIME (µs)
13502-047
V
SY
= 5V
V
IN
= 0.5V TO 3.5V
Figure 51. Large Signal Transient Response, VSY = 5 V
–3
–2
–1
0
1
2
3
01 2 3 4 5 6 7 8 9 10
VOLTAGE (V)
TIME (µs)
V
SY
= ±2. 5V
V
IN
= ±2V
13502-048
Figure 52. Large Signal Transient Response, VSY = ±2.5 V
–0.10
–0.05
0
0.05
0.10
012345678910
VOLTAGE (V)
TIME (µs)
VSY = ±15V
VIN = ±50mV p-p
13502-049
Figure 53. Small Signal Transient Response, VSY = ±15 V
–0.10
–0.05
0
0.05
0.10
012345678910
VOLTAGE (V)
TIME (µs)
VSY = ±5V
VIN = ±50mV p-p
13502-050
Figure 54. Small Signal Transient Response, VSY = ±5 V
0.15
0.20
0.25
0.30
0.35
01234567 8 9 10
VOLTAGE (V)
TIME (µs)
13502-051
VSY = 5V
VIN = 0.2V TO 0. 3V
Figure 55. Small Signal Transient Response, VSY = 5 V
–20
–10
0
10
20
–15
–10
–5
0
5
012345678910
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
13502-052
VSY = ±15V
Figure 56. Negative Overload Recovery, AV = −10, VSY = ±15 V
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 22 of 37
–6
–3
0
3
6
–3
–2
–1
0
1
012345678910
OUTPUT VOLTAGE (V)
INPUT V
O
LTAGE (V)
TIME (µs)
13502-053
V
SY
= ±5V
Figure 57. Negative Overload Recovery, AV = −10, VSY = ±5 V
–3
–2
–1
1
0
2
–2.0
–1.5
–1.0
0
–0.5
0.5
012345678910
OUTPUT VOLTAGE (V)
INPUT V
O
LTAGE (V)
TIME (µs)
13502-054
V
SY
= ±2.5V
Figure 58. Negative Overload Recovery, AV = −10, VSY = ±2.5 V
–5
5
15
25
35
–15
–10
–5
0
5
012345678910
OUTPUT VOLTAGE (V)
INPUT V
O
LTAGE (V)
TIME (µs)
13502-055
VSY = ±15V
Figure 59. Positive Overload Recovery, AV = −10, VSY = ±15 V
–3
0
3
9
6
12
–4
–3
–2
0
–1
1
012345678910
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
13502-056
V
SY
= ±5V
Figure 60. Positive Overload Recovery, AV = −10, VSY = ±5 V
–1
1
0
2
4
3
5
–2.5
–2.0
–1.5
0
–0.5
–1.0
0.5
012345678910
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
13502-057
V
SY
= ±2.5V
Figure 61. Positive Overload Recovery, AV = −10, VSY = ±2.5 V
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
–25
–20
–15
–10
-5
0
5
10
012345678910
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
V
SY
= ±15V
V
IN
= ±5V
13502-058
Figure 62. Positive Settling Time, AV = −10, VSY = ±15 V
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 23 of 37
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
–20
–16
–12
–8
–4
0
4
8
0 1 2345678910
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
VSY = ± 5V
VIN = ±4V
13502-059
Figure 63. Positive Settling Time, AV = −10, VSY = ±5 V
–0.01
0.01
0
0.02
0.04
0.03
0.05
–12
–10
–8
–2
–4
–6
0
012345678910
OUTPUT VOLTAGE (V)
INP UT VOLTAGE (V)
TIME (µs)
13502-060
V
SY
= 5V
V
IN
= –0.5V TO –4. 5V
Figure 64. Positive Settling Time, AV = −10, VSY = 5 V
–0.08
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
–25
–20
–15
–10
–5
0
5
10
01234567 8 9 10
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
V
SY
= ±15V
V
IN
= ±5V
13502-061
Figure 65. Negative Setting Time, AV = −10, VSY = ±15 V
–0.07
–0.06
–0.05
–0.04
–0.03
–0.02
–0.01
–20
–16
–12
–8
–4
0
4
8 0
012345678910
OUTPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TIME (µs)
V
SY
= ±5V
V
IN
= ±4V
13502-062
Figure 66. Negative Setting Time, AV = −10, VSY = ±5 V
–0.04
–0.02
–0.03
–0.01
0.01
0
0.02
–12
–10
–8
–2
–4
–6
0
01234567 8 9 10
OUTPUT VOLTAGE (V)
INP UT VOLTAGE (V)
TIME (µs)
13502-063
VSY = 5V
VIN = –0.5V TO –4.5V
Figure 67. Negative Setting Time, AV = −10, VSY = 5 V
VOLTAGE NOISE DENSITY (nV/√Hz)
13502-064
FREQUENCY (Hz)
V
SY
= ±15V
Figure 68. Voltage Noise Density, VSY = ±15 V
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 24 of 37
13502-065
CH1 200mV M1.00ms A CH1 –3.80MV
1
CH1 p-p = 776.0mV
VSY = ±15V
Figure 69. 0.1 Hz to 10 Hz Noise, VSY = ±15 V,
Gain = 1 Million
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0 ±2±4±6 ±8±10±12±14±16±18
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
–40°C
+25°C
+85°C
+125°C
13502-066
Figure 70. Supply Current (ISY) vs. Supply Voltage (VSY) for Various
Temperatures (ADA4622-2)
1.0
1.1
1.2
1.3
1.4
1.5
1.6
–40 –25 –10 5 20 35 50 65 80 95 110 125
SUPPLY CURRENT (mA)
TEMPERATURE (°C)
V
SY
= +5V
V
SY
= ±2.5V
V
SY
= ±5V
V
SY
= ±15V
13502-067
Figure 71. Supply Current (ISY) vs. Temperature for Various Supply Voltages
(ADA4622-2)
–140
–120
–100
–80
–60
–40
–20
0
100 1k 10k 100k
CHANNEL SEPARATION (dB)
FREQUENCY (Hz)
VSY = ±15V
VIN = 20V p-p
13502-068
Figure 72. Channel Separation vs. Frequency, VSY = ±15 V
0.0001
0.001
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10
THD + N (%)
AMPLITUDE (V rms)
V
SY
= ±15V
BW = 500kHz
BW = 80kHz
13502-069
Figure 73. THD + N vs. Amplitude, VSY = ±15 V
0.0001
0.001
0.01
0.1
1
10
100
0.01 0.1 1 10
THD + N (%)
AMPLITUDE (V rms)
V
SY
= ±5V
BW = 500kHz
BW = 80kHz
13502-070
0.001
Figure 74. THD + N vs. Amplitude, VSY = ±5 V
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 25 of 37
0.0001
0.001
0.01
0.1
1
10
100
0.001 0.01 0.1 110
THD + N (%)
AMPL IT UDE ( V rms)
VSY = 5V
BW = 500kHz
BW = 80kHz
13502-071
Figure 75. THD + N vs. Amplitude, VSY = 5 V
0.00001
0.0001
0.001
0.01
0.1
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY (Hz)
VSY = ± 15V
BW = 500kHz
BW = 80kHz
13502-072
Figure 76. THD + N vs. Frequency, VSY = ±15 V
0.00001
0.0001
0.001
0.01
0.1
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY (Hz)
VSY = ± 5V
BW = 500kHz
BW = 80kHz
13502-073
Figure 77. THD + N vs. Frequency, VSY = ±5 V
0.001
0.01
0.1
10 100 1k 10k 100k
THD + N ( %)
FREQUENCY (Hz)
VSY = 5V
BW = 500kHz
BW = 80kHz
13502-074
Figure 78. THD + N vs. Frequency, VSY = 5 V
0
10
20
30
40
50
60
70
–40 –25 –10 520 35 50 65 80 95 110 125
SHUT DO WN CURRENT (µ A)
TEMPERATURE (°C)
±15V
±5V
+5V
13502-277
Figure 79. Shutdown Current vs. Temperature
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 26 of 37
THEORY OF OPERATION
SLEW
ENHANCEMENT
CIRCUIT
ED1
+IN x
V+
OUT x
V–
–
IN x
ED2
R1
R3 R4
R8 R9 R10
R7
Q1 Q3
C1
Q2
Q4 Q5
RR
OUTPUT
STAGE
V
BIAS
R5 R6
IN OUT1 OUT2
J2J1
R2
ED3 ED4
ED5
ED6
I
MAGIC
CURRENT
CURRENT MIRROR
13502-075
Figure 80. Simplified Circuit Diagram
INPUT CHARACTERISTICS
The ADA4622-1/ADA4622-2/ADA4622-4 input stage consists
of N-channel JFETs that provide low offset, low noise, and high
impedance. The minimum input common-mode voltage
extends from −0.2 mV below V− to 1 V less than V+. Driving
the input closer to the positive rail causes loss of amplifier
bandwidth and increased common-mode voltage error. Figure 81
shows the rounding of the output due to the loss of bandwidth.
The input and output are superimposed.
13502-076
CH1 1.00V CH2 1.00V M2.00µs A CH1 3.00V
1
Figure 81. Bandwidth Limiting due to Headroom Requirements
The ADA4622-1/ADA4622-2/ADA4622-4 do not exhibit phase
reversal for input voltages up to V+. For input voltages greater
than V+, a 10 kΩ resistor in series with the noninverting input
prevents phase reversal at the expense of higher noise (see
Figure 82).
13502-077
CH1 1.00V CH2 1.00V M2.00µs
1
A CH1 3.84V
Figure 82. No Phase Reversal
Because the input stage uses N-channel JFETs, the input current
during normal operation is negative. However, the input bias
current changes direction as the input voltage approaches V+
due to internal junctions becoming forward-biased (see Figure 83).
–3
–2
–1
0
1
2
3
4
–5 –4 –3 –2 –1 0 1 2 3 4 5
INPUT BIAS CURRENT (pA)
COMMON-MODE VOLTAGE (V)
13502-078
Figure 83. Input Bias Current vs. Common-Mode Voltage with ±5 V Supply
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 27 of 37
The ADA4622-1/ADA4622-2/ADA4622-4 are designed for
12 nV/√Hz wideband input voltage noise density and maintain
low noise performance at low frequencies (see Figure 84). This
noise performance, along with the low input current as well as
low current noise, means that the ADA4622-1/ADA4622-2/
ADA4622-4 contribute negligible noise for applications with a
source resistance greater than 10 kΩ and at signal bandwidths
greater than 1 kHz.
1k
10k
100k
10 100 1k 10k 100k
RESISTANCE (Ω)
FREQUENCY (Hz)
13502-079
ADA4622-1/ADA4622-2/ADA4622-4 VOLTAGE
AND CURRENT NOISE
R
S
NOISE
TOTAL NOISE
Figure 84. Total Noise vs. Source Resistance and Frequency
Input Overvoltage Protection
The ADA4622-1/ADA4622-2/ADA4622-4 have internal
protective circuitry that allows voltages as high as 0.3 V beyond
the supplies applied at the input of either terminal without
causing damage. Use a current-limiting resistor in series with the
input of the ADA4622-1/ADA4622-2/ADA4622-4 if the input
voltage exceeds 0.3 V beyond the supply rails of the amplifiers. If
the overvoltage condition persists for more than a few seconds,
damage to the amplifiers can result.
For higher input voltages, determine the resistor value by
mA10
S
SY
IN
R
V
V
where:
VIN is the input voltage.
VSY is the voltage of either the V+ pin or the V− pin.
RS is the series resistor.
With a very low input bias current of ±1.5 nA maximum up to
125°C, higher resistor values can be used in series with the inputs
without introducing large offset errors. A 1 kΩ series resistor
allows the ADA4622-1/ADA4622-2/ADA4622-4 to withstand
10 V of continuous overvoltage and increases the noise by a
negligible amount. A 5 kΩ resistor protects the inputs from
voltages as high as 25 V beyond the supplies and adds less than
10 μV to the offset voltage of the amplifiers.
EMI Rejection Ratio
Figure 85 shows the EMI rejection ratio (EMIRR) vs. the
frequency for the ADA4622-1/ADA4622-2/ADA4622-4.
0
20
40
60
80
100
10M 100M 1G
EMIRR (dB)
FREQUENCY (Hz)
COMPETITOR 1
COMPETITOR 2
ADA4622-1/ADA4622-2/ADA4622-4
13502-080
Figure 85. EMIRR vs. Frequency
OUTPUT CHARACTERISTICS
The ADA4622-1/ADA4622-2/ADA4622-4 unique bipolar rail-
to-rail output stage swings within 10 mV of the supplies with no
external resistive load.
The approximate output saturation resistance of the ADA4622-1/
ADA4622-2/ADA4622-4 is 24 Ω, sourcing or sinking. Use the
output impedance to estimate the output saturation voltage when
driving heavier loads. As an example, when driving 5 mA, the
saturation voltage from either rail is approximately 120 mV.
If the ADA4622-1/ADA4622-2/ADA4622-4 output drives hard
against the output saturation voltage, it recovers within 1.2 μs of the
input, returning to the linear operating region of the amplifier
(see Figure 56 and Figure 59).
Capacitive Load Drive Capability
Direct capacitive loads interact with the effective output impedance
of the ADA4622-1/ADA4622-2/ADA4622-4 to form an
additional pole in the feedback loop of the amplifiers, which
causes excessive peaking on the pulse response or loss of
stability. The worst case condition is when the devices use a single
5 V supply in a unity-gain configuration. Figure 86 shows the
pulse response of the ADA4622-1/ADA4622-2/ADA4622-4
when driving 500 pF directly.
13502-081
CH1 50.0mV
BW
M2.00µs A CH1 108mV
1
Figure 86. Pulse Response with 500 pF Load Capacitance
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 28 of 37
SHUTDOWN OPERATION
Use the active low DISABLE input to put the ADA4622-1 into
shutdown mode. When the voltage on the DISABLE input is
less than 1.4 V above the negative supply voltage (V−), the
ADA4622-1 shuts down and consumes only 50 μA to 60 μA
(typical). When the voltage on the DISABLE input is more than
1.4 V above the negative supply voltage (V−), or if the DISABLE
input is left floating, the ADA4622-1 powers up. For best
performance, it is recommended that the input voltage level on
the DISABLE input be V− or that the input be left floating. The
ADA4622-1 is still a drop-in replacement for devices with
standard single channel op amp pinouts because the ADA4622-1
enables when the DISABLE input is left floating. Figure 87
shows a simplified circuit for the DISABLE input.
DISABLE
MIRROR I
OUT
13502-285
Figure 87. Simplified Circuit for the DISABLE Input
Figure 88 and Figure 89 show the start-up and shutdown
response when toggling the DISABLE input.
CH1 50mV CH2 5V M1.00µs A CH2 –11.5V
1
1
T 49.8%
∆: 1.12µs ∆: 5mV
@: 1.10µs @: –1mV
13502-286
Figure 88. Start-Up Response when Toggling the DISABLE Input
CH1 100mV CH2 5V M1.00µs A CH2 –11.5V
1
1
T 49.8%
∆: 1.98µs ∆: 2mV
@: –60ns @: 2mV
13502-287
Figure 89. Shutdown Response when Toggling the DISABLE Input
Figure 90 shows the DISABLE input current vs. the DISABLE
input voltage relative to the negative supply voltage (V−).
DISABLE INPUT CURRENT (µA)
0123
DISABLE INPUT VOLTAGE RELATIVE TO V– (V)
456
13502-288
Figure 90. DISABLE Input Current vs. DISABLE Input Voltage Relative to V−
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 29 of 37
APPLICATIONS INFORMATION
RECOMMENDED POWER SOLUTION
The ADA4622-1/ADA4622-2/ADA4622-4 can operate from a
±2.5 V to ±15 V dual supply or a 5 V to 30 V single supply. The
ADP7118 and the ADP7182 are recommended to generate the
clean positive and negative rails for the ADA4622-1/ADA4622-2/
ADA4622-4. Both low dropout (LDO) regulators are available in
fixed output voltage or adjustable output voltage versions. To
generate the input voltages for the LDOs, the ADP5070 dc-to-dc
switching regulator is recommended. Figure 91 shows the
recommended power solution configuration for the ADA4622-1/
ADA4622-2/ADA4622-4.
ADP5070
ADP7118
ADP7182
+12
V
+16
V
+15V
–15V
–16V
13502-082
Figure 91. Power Solution Configuration for the
ADA4622-1/ADA4622-2/ADA4622-4
Table 12. Recommended Power Management Devices
Product Description
ADP5070 DC-to-DC switching regulator with independent
positive and negative outputs
ADP7118 20 V, 200 mA, low noise, CMOS LDO regulator
ADP7182 −28 V, −200 mA, low noise, linear regulator
MAXIMUM POWER DISSIPATION
The maximum power the ADA4622-1/ADA4622-2/ADA4622-4
can safely dissipate is limited by the associated rise in junction
temperature. For plastic packages, the maximum safe junction
temperature is 150°C. If this maximum temperature is exceeded,
reduce the die temperature to restore proper circuit operation.
Leaving the device in the overheated condition for an extended
period of time can result in device burnout. To ensure proper
operation, it is important to observe the specifications shown in
the Absolute Maximum Ratings and Thermal Resistance sections.
SECOND-ORDER LOW-PASS FILTER
Figure 92 shows the ADA4622-1/ADA4622-2/ADA4622-4
configured as a second-order, Butterworth, low-pass filter. With
the values as shown, the corner frequency equals 200 kHz. The
following equations show the component selection:
R1 = R2 = User Selected (Typical Values: 10 kΩ to 100 kΩ)
R1f
C1
CUTOFF
2π
1.414
R1f
2C
CUTOFF
2π
0.707
ADA4622-1/
ADA4622-2/
ADA4622-4
C3
0.1µF
+5V
C4
0.1µF
V
OUT
V
IN
C1
28pF
–5V
C2
56pF
R1
20kΩR2
20kΩ
50pF
13502-083
Figure 92. Second-Order, Butterworth, Low-Pass Filter
Figure 93 shows a plot of the filter; greater than 35 dB of high
frequency rejection is achieved.
100
–50
–40
–30
–20
–10
0
10
20
30
40
50
1k 10k 100k
FREQUENCY (Hz)
1M 10M 100M
13502-084
AMPLITUDE (dB)
Figure 93. Frequency Response of the Filter
WIDEBAND PHOTODIODE PREAMPLIFIER
The ADA4622-1/ADA4622-2/ADA4622-4 are an excellent
choice for photodiode preamplifier applications. The low input
bias current minimizes the dc error at the output of the pre-
amplifier. In addition, the high gain bandwidth product and low
input capacitance maximizes the signal bandwidth of the
photodiode preamplifier. Figure 94 shows the ADA4622-1/
ADA4622-2/ADA4622-4 as a current to voltage (I to V)
converter with an electrical model of a photodiode.
–
+
V
OUT
V
B
C
D
C
M
C
M
R
SH
= 10
11
Ω
C
S
I
PHOTO
C
F
R
F
13502-085
ADA4622-1/
ADA4622-2/
ADA4622-4
Figure 94. Wideband Photodiode Preamplifier
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 30 of 37
The following basic transfer function describes the transimpedance
gain of the photodiode preamplifier:
FF
F
PHOTO
OUT RsC
RI
V
1
where:
IPHOTO is the output current of the photodiode.
The parallel combination of RF and CF sets the signal bandwidth
(see the I to V gain trace in Figure 96).
s refers to the s-plane.
Note that RF must be set so the maximum attainable output
voltage corresponds to the maximum diode output current,
IPHOTO, which allows use of the full output swing. The attainable
signal bandwidth with this photodiode preamplifier is a function
of RF, the gain bandwidth product (fGBP) of the amplifier, and
the total capacitance at the amplifier summing junction, including
CS and the amplifier input capacitance, CD and CM. RF and the
total capacitance produce a pole with loop frequency (fP).
S
F
PCR
f
2
1
With the additional pole from the amplifier open-loop response,
the two-pole system results in peaking and instability due to an
insufficient phase margin (see Figure 95).
log f
log f
G = 1
G = R2C1s
OPEN-LOOP GAIN
PHASE (°) |A| (dB)
–180°
–135°
–90°
–45°
0°
13502-086
f
P
f
X
f
GBP
Figure 95. Gain and Phase Plot of the Transimpedance Amplifier Design,
Without Compensation
OPEN-LOOP GAIN
f
fp
G = 1
f
fGBP
G = 1 + C
S
/C
F
fZ
fX
fN
I TO V GAIN
|A (s)|
–
135°
–90°
–45°
0°
45°
90°
G = R
F
C
S
(s)
13502-087
Figure 96. Gain and Phase Plot of the Transimpedance Amplifier Design with
Compensation
Adding CF creates a zero in the loop transmission that compensates
for the effect of the input pole, which stabilizes the photodiode
preamplifier design because of the increased phase margin. Adding
CF also sets the signal bandwidth (see Figure 96). The signal
bandwidth and the zero frequency are determined by
FF
ZCR
fπ2
1
where fZ is the zero frequency.
Setting the zero at the fX frequency maximizes the signal bandwidth
with a 45° phase margin. Because fX is the geometric mean of fP
and fGBP, it can be calculated by
GBP
PX fff
Combining these equations, the CF value that produces fX is
GBP
F
S
FfR
C
C
2
The frequency response in this case shows approximately 2 dB of
peaking and 15% overshoot. Doubling CF and halving the band-
width results in a flat frequency response with approximately 5%
transient overshoot.
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 31 of 37
The dominant sources of output noise in the wideband photodiode
preamp design are the input voltage noise of the amplifier, VNOISE,
and the resistor noise due to RF. The gray trace in Figure 96 shows
the noise gain over frequencies for the photodiode preamp.
Calculate the noise bandwidth at the fN frequency by
FF
S
GBP
NCCC
f
f)(
Figure 97 shows the ADA4622-1/ADA4622-2/ADA4622-4
configured as a transimpedance photodiode amplifier. The
amplifiers are used in conjunction with a photodiode detector
with an input capacitance of 5 pF. Figure 98 shows the transim-
pedance response of the ADA4622-1/ADA4622-2/ADA4622-4
when IPHOTO is 1 μA p-p. The amplifiers have a bandwidth of
2 MHz when they are maximized for a 45° phase margin with
CF = 2 pF. Note that with the PCB parasitics added to CF, the
peaking is only 0.5 dB, and the bandwidth is reduced slightly.
Increasing CF to 3 pF completely eliminates the peaking; however,
increasing CF to 3 pF reduces the bandwidth to 1 MHz.
Table 13 shows the noise sources and total output noise for the
photodiode preamp, where the preamp is configured to have a
45° phase margin for maximum bandwidth and fZ = fX = fN in
this case.
0.1µF
+5V
49.9kΩ
V
OUT
0.1µF
–5V
–
5
V
100Ω
2p
F
13502-088
ADA4622-1/
ADA4622-2
ADA4622-4
Figure 97. Transimpedance Photodiode Preamplifier
10 100
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
1k 10k 100k
FREQUENCY (Hz)
AMPLITUDE (dB)
1M 10M 100M
13502-089
2pF
3pF
Figure 98. Transimpedance Photodiode Preamplifier Frequency Response
Table 13. RMS Noise Contributions of the Photodiode Preamplifier
Contributor Expression RMS Noise (μV)1
RF
2
π
NF fR4kT 50.8
VNOISE
N
F
DFM
S
NOISE f
C
CCCC
V
2
)( 131.6
Root Sum Square (RSS) Total 22
NOISE
FVR 141
1 RMS noise with RF = 50 kΩ, CS = 5 pF, CF = 2 pF, CM = 3.7 pF, and CD = 0.4 pF.
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 32 of 37
PEAK DETECTOR
A peak detector captures the peak value of a signal and produces an
output equal to it. By taking advantage of the dc precision and
super low input bias current of the JFET input amplifiers, such as
the ADA4622-1/ADA4622-2/ADA4622-4, a highly accurate
peak detector can be built, as shown in Figure 99.
ADA4622-1/
ADA4622-2/
ADA4622-4
ADA4622-1/
ADA4622-2/
ADA4622-4
V
IN
+
–
V–
V
+
V–
V+
U1
3
2
4
8
1
5
6
4
8
7
C4
50pF C3
1µF
R6
1kΩ
R7
10kΩ
D2
1N448
D3
1N4148
+PEAK
D4
1N4148
U2
13502-090
Figure 99. Positive Peak Detector
In this application, D3 and D4 act as unidirectional current
switches that open when the output is kept constant in hold mode.
To detect a positive peak, U1 drives C3 through D3 and drives
D4 until C3 is charged to a voltage equal to the input peak value.
Feedback from the output of the U2 (positive peak) through R6
limits the output voltage of U1. After detecting the peak, the
output of U1 swings low but is clamped by D2. D3 reverses bias
and the common node of D3, D4, and R7 is held to a voltage
equal to positive peak by R7. The voltage across D4 is 0 V;
therefore, the leakage is small. The bias current of U2 is also
small. With almost no leakage, C3 has a long hold time.
The ADA4622-1/ADA4622-2/ADA4622-4, shown in Figure 99,
are a perfect fit for building a peak detector because U1 requires
dc precision and high output current during fast peaks, and U2
requires low input bias current (IB) to minimize capacitance
discharge between peaks. A low leakage and low dielectric
absorption capacitor, such as polystyrene or polypropylene, is
required for C3. Reversing the diode directions causes the
circuit to detect negative peaks.
MULTIPLEXING INPUTS
By using the ADA4622-1 DISABLE input, it is possible to multi-
plex two inputs to a single output by using the circuit shown in
Figure 100. If the gain configuration or filter configuration of
the two amplifiers is different, and a common single input to
both amplifiers is used, this configuration can control selectable
gain or selectable frequency response at the output.
V
+
V
+
–
ADA4622-1
ADA4622-1
V–
U1
3
2
4
7
6
8
VOUT
V
V
+
–
V–
U2
3
2
4
7
6
8
DISABLE
13502-298
Figure 100. Multiplexed Input Circuit
Figure 101 shows the output response when multiplexing two
input signals. The input to the first amplifier is a 4 V p-p,
200 kHz sine wave; the input to the second amplifier is an
8 V p-p, 100 kHz sine wave.
OUTPUT
V
LOGIC
TIME
V
O
LTAGE
13502-299
Figure 101. Multiplexed Output
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 33 of 37
FULL WAVE RECTIFIER
Figure 102 shows the circuit of a full wave rectifier using two
ADA4622-1 op amps in single-supply operation. The circuit is
composed of a voltage follower (U1) and a second stage amplifier
(U2) that combine the output of the first stage amplifier and the
inverted version of the input signal. U1 follows the input during
the positive half cycle and clamps the negative going input
signal to ground, producing a half wave signal at VHW. The
following equation defines the circuit transfer function:
VFW = (1+ R3/R2)VHW − (R3/R2) × VIN
where:
VFW is the full wave output from U1.
R3 and R2 are the feedback resistors shown in Figure 102.
VHW is the half wave output from U1.
VIN is the input voltage.
2V p-p
1kHz
0°
R1
30kΩ
V
FW
U1 U2
V
CC
5V
V
CC
5V
GND GND GND
R2
50kΩR3
50kΩ
13502-300
Figure 102. Full Wave Rectifier Circuit
During the input positive half cycle, U1 follows the input so that
VHW = VIN; therefore, VFW = VIN. During the negative half cycle,
U1 clamps the signal to ground so that VHW = 0 V; therefore,
VFW = −(R3/R2) × VIN = −VIN because R3/R2 = 1. Figure 103
shows the input and outputs waveforms from the circuit. The
input is a 2 V p-p, 1 kHz sine wave while the circuit is running
on a 5 V single supply.
INPUT
HALF
WAVE
FULL
WAVE
13502-301
TIME
V
O
LTAGE
Figure 103. Full Wave and Half Wave Rectifier Input and Output Waveforms
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 34 of 37
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-178-AA
10°
5°
0°
SEATING
PLANE
1.90
BSC
0.95 BSC
0.60
BSC
5
123
4
3.00
2.90
2.80
3.00
2.80
2.60
1.70
1.60
1.50
1.30
1.15
0.90
0
.15 MAX
0
.05 MIN
1.45 MAX
0.95 MIN
0.20 MAX
0.08 MIN
0.50 MAX
0.35 MIN
0.55
0.45
0.35
11-01-2010-A
Figure 104. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 105. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 35 of 37
8
1
5
4
0.30
0.25
0.20
PIN 1 INDEX
AREA
0.80
0.75
0.70
1.55
1.45
1.35
1.84
1.74
1.64
0.203 REF
0.05 MAX
0.02 NOM
0.50
BSC
EXPOSED
PAD
3.10
3.00 SQ
2.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEED-4
TOP VIEW BOTTOM VIEW
SIDE VIEW
PKG-003886
02-10-2017-A
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
Figure 106. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-8-13)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 107. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ADA4622-1/ADA4622-2/ADA4622-4 Data Sheet
Rev. D | Page 36 of 37
*COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGC-3
WITH EXCEPTION TO THE EXPOSED PAD.
1
0.65
BSC
16
5
8
9
12
13
4
4.10
4.00 SQ
3.90
0.50
0.40
0.30
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.35
0.30
0.25
*2.40
2.35 SQ
2.30
10-11-2017-C
BOTTOM VIEW
TOP VIEW
SIDE VIEW
EXPOSED
PAD
PKG-004024
SEATING
PLANE
PIN 1
INDICATOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 108. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-20)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
060606-A
14 8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
45°
Figure 109. 14-Lead Standard Small Outline Package [SOIC_N]
(R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADA4622-1ARJZ-R2 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A3J
ADA4622-1ARJZ-R7 −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A3J
ADA4622-1ARJZ-RL −40°C to +125°C 5-Lead Small Outline Transistor Package [SOT-23] RJ-5 A3J
ADA4622-1ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-1ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-1ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-1BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-1BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-1BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
Data Sheet ADA4622-1/ADA4622-2/ADA4622-4
Rev. D | Page 37 of 37
Model1 Temperature Range Package Description Package Option Marking Code
ADA4622-2ACPZ-R7 −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 A3D
ADA4622-2ACPZ-RL −40°C to +125°C 8-Lead Lead Frame Chip Scale Package [LFCSP] CP-8-13 A3D
ADA4622-2ARMZ −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A3D
ADA4622-2ARMZ-R7 −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A3D
ADA4622-2ARMZ-RL −40°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 A3D
ADA4622-2ARZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-2ARZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-2ARZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-2BRZ −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-2BRZ-R7 −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-2BRZ-RL −40°C to +125°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
ADA4622-4ACPZ-R2 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20
ADA4622-4ACPZ-R7 −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20
ADA4622-4ACPZ-RL −40°C to +125°C 16-Lead Lead Frame Chip Scale Package [LFCSP] CP-16-20
ADA4622-4ARZ −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4622-4ARZ-R7 −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
ADA4622-4ARZ-RL −40°C to +125°C 14-Lead Standard Small Outline Package [SOIC_N] R-14
1 Z = RoHS Compliant Part.
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D13502-0-4/18(D)
