LTC3816
1
3816f
Typical applicaTion
FeaTures DescripTion
Single-Phase Wide VIN
Range DC/DC Controller for
Intel IMVP-6/IMVP-6.5 CPUs
The LTC
®
3816 is a single-phase synchronous step-down
DC/DC switching regulator controller that drives N-channel
power MOSFETs in a constant-frequency voltage mode
architecture. The controller’s leading edge modulation to-
pology allows extremely low output voltages and supports
a phase-lockable switching frequency up to 550kHz. The
output voltage is programmed using a 7-bit VID code.
The LTC3816 features all of the IMVP-6/IMVP-6.5 require-
ments, including start-up to a preset boot voltage, differ-
ential remote output voltage sensing with programmable
active voltage positioning, IMON output current reporting,
power optimization during sleep state, and fast or slow
slew rate sleep state exit.
Fault protection features include input undervoltage
lockout, cycle-by-cycle current limit, output overvoltage
protection, and PWRGD and overtemperature flags.
High Efficiency, Synchronous IMVP-6/ IMVP-6.5 Step-Down Controller
applicaTions
n Supports 7-Bit IMVP-6/IMVP-6.5 VID Code and
Features
n Wide VIN Range: 4.5V to 36V Operation with
Optional Line Feedforward Compensation
n tON(MIN) < 35ns, Capable of Very Low Duty Cycle
n Temperature Compensated Inductor DCR or Sense
Resistor Output Current Monitoring
n Differential Remote Output Voltage Sensing with
Programmable Active Voltage Positioning
n Phase-Lockable Fixed Frequency: 150kHz to 550kHz
n Programmable UVLO, Preset VOUT at Boot-Up
n Programmable Slow Slew Rate Sleep State Exit
n Internal LDO for Single Supply Operation
n Overvoltage and Overcurrent Protection
n PWRGD and VRTT# Thermal Throttling Flags
n Power Optimization During Sleep and Light Load
n
38-Pin Thermally Enhanced eTSSOP and 5mm × 7mm
QFN Packages
n Embedded Computing
n Mobile Computers, Internet Devices
n Navigation Displays
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and RSENSE
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patents, including 5408150, 5055767, 5481178, 6580258.
+
PWRGD
CLKEN#
VRTT#
VRON
DPRSLPVR
MODE/SYNC
RFREQ
LFF
VID0-VID6
VRON
DPRSLPVR
MODE/SYNC
INTVCC
PWRGD
CLKEN#
VRTT#
TG
BG
BOOST
SW
BSOURCE
ISENP
ISENN
IMAX
RPTC
22pF
RPTC
470pF
10k
12k 22pF
10pF
2.2nF
CSLEW
SS ITCFB
PREIMON
ITC
VCC(SEN)
VSS(SEN)
COMP
VFB
SERVO
GND
IMON
VIN
1.9k
V3
3.3V
VCCP
1.1V
1.9k56Ω EXTVCC
LTC3816
INTVCC
47µF s2 + 10µF s2
330µF s3
+ 10µF s20
4.7µF
0.1µF
0.1µF
15nF
2.55k
+VCC(CORE)
NTC
0.33µH,
1.3mΩ
VIN
4.5V TO 36V
6.98k 8.25k
5.1k
14k
10k
21k 15nF
IMON
3816 TA01
LOAD CURRENT (A)
30
EFFICIENCY (%)
POWER LOSS (W)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 TA01b
0
3
9
10
2
1
8
5
7
6
4
0
0.1
VIN = 12V, fOSC = 400kHz
VCC(CORE) = 0.75V, VEXTVCC = 5V
FORCED CONTINUOUS MODE
VIN + VEXTVCC LOSS
EFFICIENCY
Efficiency and Power Loss
vs Load Current
LTC3816
2
3816f
absoluTe MaxiMuM raTings
Input Supply Voltage (VIN) ......................... –0.3V to 40V
Topside Driver Voltage (BOOST) ................ –0.3V to 46V
Switch Voltage (SW) ..................................... –5V to 40V
INTVCC, EXTVCC, (BOOST-SW) .................. –0.3V to 6V
ISENN, ITCFB, PREIMON, IMON, RPTC, VRON, VCC(SEN),
VFB, SS, VIDn, RFREQ, MODE/SYNC,
LFF, ISENP, IMAX .........................–0.3V to INTVCC + 0.3V
PWRGD, CLKEN# ........................................ –0.3V to 6V
(Notes 1, 8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC eTSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
ISENN
ITCFB
ITC
PREIMON
IMON
RPTC
VRON
VSS(SEN)
VCC(SEN)
SERVO
VFB
COMP
SS
DPRSLPVR
CSLEW
VID0
VID1
VID2
VID3
IMAX
ISENP
LFF
VRTT#
CLKEN#
PWRGD
SW
TG
BOOST
VIN
EXTVCC
INTVCC
BG
BSOURCE
MODE/SYNC
RFREQ
VID6
VID5
VID4
39
GND
TJMAX = 125°C, θJA = 29°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
13 14 15 16
TOP VIEW
39
GND
UHF PACKAGE
38-LEAD (5mm s 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1PREIMON
IMON
RPTC
VRON
VSS(SEN)
VCC(SEN)
SERVO
VFB
COMP
SS
DPRSLPVR
CSLEW
CLKEN#
PWRGD
SW
TG
BOOST
VIN
EXTVCC
INTVCC
BG
BSOURCE
MODE/SYNC
RFREQ
ITC
ITCFB
ISENN
IMAX
ISENP
LFF
VRTT#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
pin conFiguraTion
DPRSLPVR, VRTT# .................................. –0.3V to 3.3V
VSS(SEN), BSOURCE ................................. –0.3V to 0.3V
INTVCC RMS Output Current .................................50mA
Operating Junction Temperature Range
(Note 3) .................................................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
Lead Temperature (Soldering, 10sec)
eTSSOP .............................................................300°C
LTC3816
3
3816f
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3816EFE#PBF LTC3816EFE#TRPBF LTC3816FE 38-Lead Plastic eTSSOP –40°C to 125°C
LTC3816IFE#PBF LTC3816IFE#TRPBF LTC3816FE 38-Lead Plastic eTSSOP –40°C to 125°C
LTC3816EUHF#PBF LTC3816EUHF#TRPBF 3816 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3816IUHF#PBF LTC3816IUHF#TRPBF 3816 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating junction temperature ranges.
*The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Input and INTVCC Linear Regulator
VIN VIN Supply Voltage Range VINTVCC > VUVLO l4.5 36 V
IVIN VIN Supply Current
Normal Mode
Shutdown
VBOOST = VINTVCC, fOSC = 400kHz (Note 4)
VRON = 0V
11
27
100
mA
µA
INTVCC Internal VCC Voltage l4.9 5.2 5.5 V
VINTVCC(LINE) Line Regulation 7.5V < VIN < 36V ±1.0 %
VINTVCC(LOAD) Load Regulation Load = 0mA to 20mA –0.25 –1.0 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.25 4.50 4.75 V
VEXTVCC(HYS) EXTVCC Hysteresis 0.4 V
VEXTVCC(DROP) EXTVCC Voltage Drop Load = 20mA, VEXTVCC = 5V 40 100 mV
VUVLO INTVCC Undervoltage Reset INTVCC Ramping Positive 3.7 3.9 4.1 V
Undervoltage Hystersis 0.4 V
Switcher Control Loop
VCC(CORE) VCC(CORE) = (VCC(SEN) – VSS(SEN)) VCC(CORE) > 0.75V (Note 5)
0.5V ≤ VCC(CORE) ≤ 0.75V (Note 5)
0.3V ≤ VCC(CORE) < 0.5V (Note 5)
l
l
l
±0.75
±6
±10
%
mV
mV
∆VCC(CORE) VCC(CORE) Voltage Line Regulation VIN = 7.5V to 36V (Note 5) ±0.002 %/V
AEA Error Amplifier DC Gain No load 80 dB
fBW Error Amplifier Unity-Gain Bandwidth (Note 6) 20 MHz
ICOMP Error Amplifier Output Source Current
Error Amplifier Output Sink Current
VCOMP = 0V
VCOMP = 5V
5
–1.5 mA
mA
IVCC(SEN) VCC(SEN) Input Current VISENN = VCC(SEN), 0V ≤ VCC(SEN) ≤ 1.5V ±30 µA
IVSS(SEN) VSS(SEN) Input Current VSS(SEN) = 0V –60 µA
IVFB VFB Input Current 0V ≤ VFB ≤ 2V ±0.1 µA
IITCFB ITCFB Input Current 0V ≤ VITCFB ≤ 1.5V ±0.1 µA
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BSOURCE = EXTVCC = 0V, VRON = 5V, unless
otherwise noted. (Notes 2, 3)
LTC3816
4
3816f
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VBOOT Core Supply Start-Up Voltage VIMON = INTVCC (IMVP-6 Configuration)
VIMON < 1.1V (IMVP-6.5 Configuration)
1.2
1.1
V
V
VOVF Overvoltage Fault Threshold VIMON = INTVCC (IMVP-6 Configuration)
VIMON < 1.1V (IMVP-6.5 Configuration)
l
l
1.65
1.53
1.7
1.55
V
V
ISS SS Pull-Up Current VSS = 0V –1 µA
ICSLEW CSLEW Pull-Up Current VCSLEW = 0V
IMVP-6 and VDPRSLPVR = INTVCC
IMVP-6.5 or VDPRSLPVR = 0V
–10
–40
µA
µA
IRPTC RPTC Source Current RPTC = 0V –90 –100 –110 µA
VRPTC RPTC Thermal Shutdown Threshold 0.47 V
IMAX IMAX Source Current VIMAX = 0V, 1× Current Limit Duration
VIMAX = 0V, 2× Current Limit Duration
l–9 –10
–20
–11 µA
µA
tIMAX2×2× Current Limit Duration
2× Current Limit Period
35 45
630
µs
µs
VILIM Current Comparator Offset VIMAX = 1.0V, VILIM = VISENP – VIMAX ±3 mV
VIREV Reverse-Current Comparator Offset VISENN = 1.0V, VIREV = VISENP – VISENN ±2 mV
IISENP ISENP Input Current 0V ≤ VISENP ≤ 1.5V ±1 µA
IISENN ISENN Input Current 0V ≤ VISENN ≤ 1.5V ±20 µA
VIMON IMVP-6/IMVP-6.5 Selection Threshold 2.4 V
IVRON Regulator On Source Current VRON = 0V –1 µA
VRON Regulator On Threshold
Regulator Power-Down Threshold
Rising Edge
Falling Edge
1.18 1.2
0.65
1.22 V
V
Oscillator and Drivers
fOSC Oscillator Frequency RFREQ Floats
VRFREQ = 0V
VRFREQ = 2.5V
375
180
530
400
210
580
425
240
640
kHz
kHz
kHz
fSYNC Minimum Synchronization Input Frequency
Maximum Synchronization Input Frequency
550
150 kHz
kHz
VSYNC MODE/SYNC Synchronization Threshold 1.6 V
IRFREQ RFREQ Source Current VRFREQ = 0V –9 –10 –11 µA
VMODE MODE/SYNC Force Continuous Threshold VIMON = INTVCC (IMVP-6 Configuration)
VIMON < 1.1V (IMVP-6.5 Configuration)
1.6
0.5
V
V
DCMAX Maximum TG Duty Cycle MODE/SYNC = 0, RFREQ Floats 90 %
tON(MIN) TG Minimum Pulse Width (Note 6) 35 ns
tDEAD Driver Dead-Time 30 ns
TG RUP TG Driver Pull-Up On-Resistance TG High, IOUT = –100mA (Note 7) 2.6 Ω
TG RDOWN TG Driver Pull-Down On-Resistance TG Low, IOUT = 100mA (Note 7) 1.2 Ω
BG RUP BG Driver Pull-Up On-Resistance BG High, IOUT = –100mA (Note 7) 2.6 Ω
BG RDOWN BG Driver Pull-Down On-Resistance BG Low, IOUT = 100mA (Note 7) 0.9 Ω
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BSOURCE = EXTVCC = 0V, VRON = 5V, unless
otherwise noted. (Notes 2, 3)
LTC3816
5
3816f
The l denotes the specifications which apply over the full operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, BSOURCE = EXTVCC = 0V, VRON = 5V, unless
otherwise noted. (Notes 2, 3)
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VID, DPRSLPVR, LFF Parameters
VIL(VID) VID Input Low Threshold 0.3 V
VIH(VID) VID Input High Threshold 0.7 V
IVID VID Input Leakage Current 0V ≤ VVID ≤ 5V ±1 µA
VDPRSLPVR DPRSLPVR Input Threshold VIMON = INTVCC (IMVP-6 Configuration) 1.6 V
ILFF LFF Pull-Up Current VLFF = 0V –1 µA
VLFF LFF Input Threshold 1 V
PWRGD, CLKEN#, VRTT#
VPWRGD Positive Power Good Threshold
Negative Power Good Threshold
With Respect to VID VCC(CORE) 150
–240
175
–270
200
–300
mV
mV
ILEAK PWRGD, CLKEN# Leakage Current
VRTT# Leakage Current
VPWRGD = VCLKEN# = 5V
VVRTT# = 3.3V
10
100
µA
µA
VOL PWRGD, CLKEN# Output Low Voltage
VRTT# Output Low Voltage
IOUT = 2mA
IOUT = 20mA
0.1
0.075
0.3
0.18
V
V
tPWRGD PWRGD Glitch Filter Power Good to Power Bad 750 µs
tCLKEN# CLKEN# Falling Edge Delay Rising VBOOT Edge to CLKEN#
Falling Edge
l50 75 100 µs
tCLK(PWRGD) CLKEN# to PWRGD Rising Edge Delay l5 10 20 ms
tVR(PWRGD) VRON to PWRGD Falling Edge Delay VRON Falling Edge 100 ns
Note 1: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. Exposure to any
Absolute Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Note 3: The LTC3816 is tested under pulse load conditions such that
TJ ≈ TA.
The LTC3816E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. LTC3816I specifications are
guaranteed over the full –40°C to 125°C operating junction temperature
range. Note that the maximum ambient temperature consistent with
these specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance
and other environmental factors. TJ is calculated from the ambient
temperature, TA, and power dissipation, PD, according to the following
formula,
LTC3816EFE: TJ = TA + (PD • 29°C/W)
LTC3816EUHF: TJ = TA + (PD • 34°C/W)
Note 4: The dynamic input supply current is a function of the power
MOSFET gate charging (QG • fOSC). See Applications Information for
more information.
Note 5: The LTC3816 is measured in a feedback loop that adjusts
VCC(SEN) – VSS(SEN) to achieve a specified COMP pin voltage. The AITC
amplifier is configured as an inverter with gain = –1.
Note 6: Guaranteed by design, not subject to test.
Note 7: On-resistance limit is guaranteed by design and correlation
with statistical process controls.
Note 8: The LTC3816 includes overtemperature protection that is
intended to protect the device during momentary overload conditions.
The maximum rated junction temperature will be exceeded when this
protection is active. Continuous operation above the specified absolute
maximum operating junction temperature may impair device reliability
or permanently damage the device.
LTC3816
6
3816f
Typical perForMance characTerisTics
Efficiency vs VIN with VEXTVCC = 5V
VCC(CORE) vs Temperature
Load Regulation with
AVP Slope = –3mV/A
Efficiency vs Load Current Efficiency vs VCC(CORE) Efficiency vs VIN with VEXTVCC = 0V
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 G01
0
0.1
VIN = 12V, fOSC = 400kHz
VCC(CORE) = 0.75V, VEXTVCC = 0V
LAST PAGE CIRCUIT
PULSE-SKIPPING
MODE
FORCED CONTINUOUS
MODE
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 G02
0
0.1
VIN = 12V, fOSC = 400kHz, VEXTVCC = 0V
FORCED CONTINOUS MODE
LAST PAGE CIRCUIT
VCC(CORE) = 0.50V
VCC(CORE) = 0.75V
VCC(CORE) = 1.00V
VCC(CORE) = 1.20V
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 G03
0
0.1
VCC(CORE) = 0.75V, fOSC = 400kHz
VEXTVCC = 0V
FORCED CONTINOUS MODE
LAST PAGE CIRCUIT
VIN = 5V
VIN = 12V
VIN = 24V
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 G04
0
0.1
VCC(CORE) = 0.75V, fOSC = 400kHz
VEXTVCC = 5V
FORCED CONTINOUS MODE
LAST PAGE CIRCUIT
VIN = 12V
VIN = 24V
Efficiency vs fOSC with
VEXTVCC = 0V
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 G05
0
0.1
VIN = 12V, VCC(CORE) = 0.75V
VEXTVCC = 0V
FORCED CONTINOUS MODE
LAST PAGE CIRCUIT
fOSC = 210kHz
fOSC = 400kHz
fOSC = 580kHz
Efficiency vs fOSC with
VEXTVCC = 5V
LOAD CURRENT (A)
30
EFFICIENCY (%)
90
100
20
10
80
50
70
60
40
0.01 1 10
3816 G06
0
0.1
VIN = 12V, VCC(CORE) = 0.75V
VEXTVCC = 5V
FORCED CONTINOUS MODE
LAST PAGE CIRCUIT
fOSC = 210kHz
fOSC = 400kHz
fOSC = 580kHz
TEMPERATURE (°C)
–50
0.745
VCC(CORE) (V)
0.746
0.748
0.749
0.750
0.755
0.752
050 75
3816 G07
0.747
0.753
0.754
0.751
–25 25 100 125
LOAD CURRENT (A)
0
–80
∆VCC(CORE) (mV)
–70
–50
–40
–30
16
10
3816 G08
–60
8
420 24
12 28
–20
–10
0
VCC(CORE) = 0.5V
VCC(CORE) = 1.2V
VIN = 12V, fOSC = 400kHz
VEXTVCC = 0V
AVP SLOPE = –3mV/A
FORCED CONTINOUS MODE
LAST PAGE CIRCUIT
LTC3816
7
3816f
Load Regulation vs Temperature
Typical perForMance characTerisTics
VIMON vs Temperature
Load Step in Forced Continuous
Mode
Narrow TG Pulse Width with Low
VCC(CORE) Ripple
Pulse-Skipping Mode at No Load
with Low VCC(CORE) Ripple
Pulse-Skipping Mode
at 0.2A Load
Line Regulation
TEMPERATURE (°C)
–50
–100
∆VCC(CORE) (mV)
–90
–70
–60
–50
0
–30
050 75
3816 G09
–80
–20
–10
–40
–25 25 100 125
VIN = 12V, fOSC = 400kHz
VEXTVCC = 0V, AVP = –3mV/A
L = VISHAY IHLP5050CE01 0.33µH
PTC CONFIGURATION (FIGURE 12)
RLPTC = VISHAY TFPT1206L1002FV
RVDCRP = 23.2k, CVDCRP = 10nF
NTC CONFIGURATION,
LAST PAGE CIRCUIT
NO TEMPERATURE COMPENSATION
LAST PAGE CIRCUIT, REPLACE NTC
WITH 10k RESISTOR
IDEAL VALUE
5A LOAD
10A LOAD
20A LOAD
VIN (V)
0
VCC(CORE) (V)
0.7515
12
3816 G10
0.7500
0.7490
4 8 16
0.7485
0.7480
0.7520
0.7510
0.7505
0.7495
20 24 28
fOSC = 400kHz, VEXTVCC = 0V
FORCED CONTINUOUS MODE
NO LOAD
LAST PAGE CIRCUIT
TEMPERATURE (°C)
–50
0
VIMON (V)
0.1
0.3
0.4
0.5
1.1
1.0
0.7
050 75
3816 G11
0.2
0.8
0.9
0.6
–25 25 100 125
VIN = 12V, fOSC = 400kHz
VEXTVCC = 0V, AVP = –3mV/A
RPREIMON = 5.1k, RIMON = 21k
PTC CONFIGURATION (FIGURE 12)
RLPTC = VISHAY TFPT1206L1002FV
RVDCRP = 23.2k, CVDCRP = 10nF
NTC CONFIGURATION,
LAST PAGE CIRCUIT
NO TEMPERATURE COMPENSATION
LAST PAGE CIRCUIT, REPLACE NTC
WITH 10k RESISTOR
IDEAL VALUE
5A LOAD
L = VISHAY IHLP5050CE01 0.33µH
10A LOAD
20A LOAD
VCC(CORE)
50mV/DIV
LOAD
CURRENT
20A/DIV
20µs/DIV 3816 G12
VIN = 12V
VCC(CORE) = 0.75V
fOSC = 400kHz
FORCED CONTINUOUS MODE
AVP SLOPE = –3mV/A
VCC(CORE)
20mV/DIV
VTG-VSW
2V/DIV
VBG
5V/DIV
ZOOM IN
VTG-VSW
1V/DIV
20ns/DIV
∆t = 24.6ns
20µs/DIV 3816 G13
VIN = 28V
VCC(CORE) = 0.5V (ILOAD = 0.5A)
fOSC = 400kHz
FORCED CONTINUOUS MODE
VCC(CORE)
20mV/DIV
VTG-VSW
2V/DIV
VBG
5V/DIV
100µs/DIV 3816 G14
VIN = 12V
VCC(CORE) = 0.75V, NO LOAD
fOSC = 400kHz
PULSE-SKIPPING MODE
VCC(CORE)
20mV/DIV
VTG-VSW
2V/DIV
VBG
5V/DIV
5µs/DIV 3816 G15
VIN = 12V
VCC(CORE) = 0.75V (ILOAD = 0.2A)
fOSC = 400kHz
PULSE-SKIPPING MODE
LTC3816
8
3816f
Typical perForMance characTerisTics
Momentary Overcurrent,
45µs IMAX Pulse
Start-Up to VBOOT VBOOT to PWRGD Delay VRON Shutdown
VCC(CORE)
200mV/DIV
CLKEN#
5V/DIV
PWRGD
5V/DIV
VRON
5V/DIV
100µs/DIV 3816 G16
VIN = 12V
IMVP6 CONFIGURATION
CSS = 470pF
VID = 0.75V
NO LOAD
VCC(CORE)
200mV/DIV
CLKEN#
5V/DIV
PWRGD
5V/DIV
VRON
5V/DIV
2ms/DIV 3816 G17
VIN = 12V
IMVP6 CONFIGURATION
CSS = 470pF
VID = 0.75V
NO LOAD
VCC(CORE)
200mV/DIV
CLKEN#
5V/DIV
PWRGD
5V/DIV
VRON
5V/DIV
10µs/DIV 3816 G18
VIN = 12V
VID = 0.75V
NO LOAD
Momentary Overcurrent,
90µs IMAX Pulse
VCC(CORE)
100mV/DIV
20µs ILOAD
10A/DIV
IL
10A/DIV
VRIMAX
20mV/DIV
10µs/DIV 3816 G19
VIN = 12V
VCC(CORE) = 1V
RIMAX = 1.5k
RSENSE = 1mΩ
FORCED CONTINUOUS MODE
VCC(CORE)
100mV/DIV
60µs ILOAD
10A/DIV
IL
10A/DIV
VRIMAX
20mV/DIV
20µs/DIV 3816 G20
VIN = 12V
VCC(CORE) = 1V
RIMAX = 1.5k
RSENSE = 1mΩ
FORCED CONTINUOUS MODE
2x Overcurrent
VCC(CORE)
100mV/DIV
20µs ILOAD
20A/DIV
IL
20A/DIV
VRIMAX
20mV/DIV
10µs/DIV 3816 G21
VIN = 12V
VCC(CORE) = 1V
RIMAX = 1.5k
RSENSE = 1mΩ
FORCED CONTINUOUS MODE
Current Comparator Offset
vs Common Mode Range
Duty Cycle vs VCOMP with Line
Feedforward
VISENN (V)
0
VISENP – VIMAX (mV)
–0.5
0
0.5
0.75 1.25
3816 G22
–1.0
–1.5
–2.0 0.25 0.5 1
1.0
1.5
2.0
1.5
VIN = 12V
VIMAX – VISENN = 20mV
Current Comparator Offset
vs Temperature
VCOMP (V)
1.0
0
DUTY CYCLE (%)
10
30
40
50
100
70
1.4 1.8 2.0
3816 G24
20
80
90
60
1.2 1.6 2.2 2.4
VIN = 5V
VIN = 12V
VIN = 24V
VIN = 36V
fOSC = 400kHz
LFF = FLOAT
TEMPERATURE (°C)
–50
VISENP – VIMAX (mV)
1.5
25
3816 G23
0
–1.0
–25 0 50
–1.5
–2.0
2.0
1.0
0.5
–0.5
75 100 125
VIN = 12V
VISENN = 1V
VIMAX – VISENN = 20mV
LTC3816
9
3816f
Typical perForMance characTerisTics
Duty Cycle vs VCOMP without Line
Feedforward VRPTC vs TemperaturefOSC vs Temperature
VCOMP (V)
1.0
0
DUTY CYCLE (%)
10
30
40
50
100
70
1.4 1.8 2.0
3816 G25
20
80
90
60
1.2 1.6 2.2 2.4
VIN = 12V
fOSC = 400kHz
LFF = 0V
TEMPERATURE (°C)
–50
fOSC (kHz)
500
600
700
25 75
3816 G26
400
300
–25 0 50 100 125
200
100
VRFREQ = 2.5V
VRFREQ = 0V
RFREQ FLOATS
TEMPERATURE (°C)
–50
VRPTC POSITIVE THRESHOLD (mV)
VRPTC NEGATIVE THRESHOLD (mV)
470
475
480
25 75
3816 G27
465
460
–25 0 50 100 125
455
450
110
115
120
105
100
95
90
VRPTC POSITIVE THRESHOLD
VRPTC NEGATIVE THRESHOLD
INTVCC Line Regulation INTVCC Dropout vs TemperatureINTVCC Load Regulation
TEMPERATURE (°C)
–50
IRFREQ, IIMAX (µA)
IRPTC (µA)
10.50
11.00
11.50
10.75
11.25
25 75
3816 G28
10.25
10.00
–25 0 50 100 125
9.75
9.50
95.0
100.0
105.0
IRPTC
97.5
102.5
92.5
90.0
87.5
85.0
IRFREQ, IIMAX
TEMPERATURE (°C)
–50
0.5
VRON THRESHOLD (V)
0.6
0.8
0.9
1.0
50
1.4
3816 G29
0.7
0
–25 75 100
25 125
1.1
1.2
1.3 VRON RAMPS HIGH,
REGULATOR ON THRESHOLD
VRON RAMPS LOW,
REGULATOR OFF THRESHOLD
VRON RAMPS HIGH,
POWER-UP THRESHOLD
VRON RAMPS LOW,
POWER-DOWN THRESHOLD
TEMPERATURE (°C)
–50
3.8
3.9
4.1
25 75
3816 G30
3.7
3.6
–25 0 50 100 125
3.5
3.4
4.0
INTVCC UVLO (V)
VEXTVCC = 0V
VIN RAMPS HIGH
VIN RAMPS LOW
IIMAX, IRFREQ and IRPTC
vs Temperature INTVCC UVLO vs TemperatureVRON vs Temperature
VIN (V)
0
VINTVCC (V)
4.8
5.0
5.2
30
3816 G31
4.6
4.4
10 20
5 35
15 25 40
4.2
4.0
5.4 VEXTVCC = 0V
ILOAD (mA)
0
∆INTVCC WITH VIN = 12V (mV)
∆INTVCC WITH VIN = 5V (mV)
–20
–10
40
3816 G32
–30
–40 10 20 30 50
0
–600
–300
–900
–1200
0
VEXTVCC = 0V
fOSC = 400kHz
VIN = 12V
VIN = 5V
TEMPERATURE (°C)
–50 –25
–1.0
INTVCC DROPOUT VOLTAGE (V)
–0.6
0
050 75
3816 G33
–0.8
–0.2
–0.4
25 100 125
VEXTVCC = 0V
fOSC = 400kHz
LOAD CURRENT = 20mA
∆INTVCC = –1%
LTC3816
10
3816f
Typical perForMance characTerisTics
EXTVCC Switchover Voltage
vs Temperature IVIN
EXTVCC Voltage Drop
vs Temperature
TEMPERATURE (°C)
–50
3.9
EXTVCC SWITCHOVER VOLTAGE (V)
4.0
4.2
4.3
4.4
50
4.8
3816 G34
4.1
0
–25 75 100
25 125
4.5
4.6
4.7
EXTVCC RAMPS HIGH
EXTVCC RAMPS LOW
TEMPERATURE (°C)
–50
VEXTVCC – VINTVCC (mV)
80
100
120
25 75
3816 G35
60
40
–25 0 50 100 125
20
0
VEXTVCC = 5V
fOSC = 400kHz
ILOAD = 50mA
ILOAD = 20mA
NO LOAD
VIN (V)
0
IVIN (mA)
IVIN (SHUTDOWN) (µA)
13
14
15
15 25 40
3816 G36
12
11
10
30
40
50
20
10
0
5 10 20 30 35
VEXTVCC = 0V
fOSC = 400kHz
IVIN (SHUTDOWN)
IVIN
IVIN (Shutdown) vs Temperature IVIN and IEXTVCC vs Temperature
TEMPERATURE (°C)
–50
IVIN (µA)
40
50
60
25 75
3816 G37
30
20
–25 0 50 100 125
10
0
VEXTVCC = VRON = 0V
VIN = 5V
VIN = 12V
VIN = 40V
TEMPERATURE (°C)
–50
12
13
15
25 75
3816 G38
11
10
–25 0 50 100 125
9
8
14
IVIN, IEXTVCC (mA)
VIN = 12V
fOSC = 400kHz
VEXTVCC = 0V, IVIN
VEXTVCC = 5V, IEXTVCC
VCC(SEN) and ISENN Input Current
vs Common Mode Range VSS(SEN) Input Current
VCC(SEN) (V)
0
–10
IVCC(SEN), IISENN (µA)
–5
0
5
10
20
0.25 0.50 0.75 1.00
3816 G39
1.25 1.50
15
VIN = 12V
VISENN = VCC(SEN)
VITC = VITCFB
VSS(SEN) = 0V
IVCC(SEN)
IISENN
VSS(SEN) (V)
–0.3
–50
IVSS(SEN) (µA)
–40
–30
–20
–10
0
–0.2 –0.1 0 0.1
3816 G40
0.2 0.3
VIN = 12V
VISENN = VCC(SEN)
VITC = VITCFB
VCC(CORE) = 0.3V
VCC(CORE) = 0.9V
VCC(CORE) = 1.5V
LTC3816
11
3816f
pin FuncTions
(eTSSOP/QFN)
ISENN (Pin 1/Pin 36): Current Sense Negative Input. Con-
nect this pin to the negative terminal of the current sense
resistor or the negative terminal of the inductor DCR
lowpass filter.
ITCFB (Pin 2/Pin 37): Inductor DCR Temperature Compen-
sation Amplifer Feedback Input. To derive the temperature
compensated voltage dropped across the inductor DCR,
connect a resistor from the SW node to this pin. An NTC
network, in parallel with a capacitor, forms the feedback
path of this amplifier. For applications that use a discrete
resistor for current sensing, replace the NTC network
with a resistor.
ITC (Pin 3/Pin 38): Inductor DCR Temperature Compen-
sation Amplifer Output. The IMON circuitry and the error
amplifier obtain the temperature compensated DCR voltage
through this amplifier.
PREIMON (Pin 4/Pin 1): IMON Current Output Setting.
PREIMON is servoed to the ISENN potential. A resistor from
PREIMON to ITC sets the IMON
output current. For the IMVP-6
configuration, connect this pin to INTVCC.
IMON
(Pin 5/Pin 2): IMVP-6/IMVP-6.5 Configuration Selec-
tion and Output Current Monitor. Connect this pin to INTVCC
to select the IMVP-6 configuration. At start-up, the switcher
VOUT is ramped to 1.2V (VBOOT). In deeper sleep mode,
the controller enables the slow VOUT slew rate. Connect a
resistor to VSS(SEN) to select the IMVP-6.5 configuration.
In this case, VBOOT equals 1.1V, slow slew rate is disabled
and the IMON current source is proportional to the load. In
the IMVP-6.5 configuration, this pin is internally clamped
to 1.1V with respect to the VSS(SEN) pin.
RPTC (Pin 6/Pin 3):
Nonlinear PTC Thermistor Input.
Connect to a nonlinear PTC thermistor for MOSFET or
inductor temperature sensing. This pin is pulled up by a
100µA current source. If the potential at RPTC is higher
than 0.47V, thermal flag VRTT# is pulled low. RPTC is
sensitive to noise pickup. Avoid coupling high frequency
switching signals to this pin. If required, bypass this
pin with a capacitor to GND.
VRON (Pin 7/Pin 4): Voltage Regulator Enable Input. The
VRON pin power-up threshold is 1.2V. When forced below
0.65V, a power-down sequence is initiated where the
VCC(CORE) output is ramped down near 0V before the IC
is put into a low current shutdown mode. The VRON pin
has an internal 1µA pull-up current.
VSS(SEN) (Pin 8/Pin 5): Processor VCC(CORE) Negative
Terminal Voltage Sense. Negative input of the differential
sense amplifier. Connect to the processor VSS(SEN) pin.
VCC(SEN) (Pin 9/Pin 6): Processor VCC(CORE) Positive
Terminal Voltage Sense. Positive input of the differential
sense amplifier. Connect to the processor VCC(SEN) pin.
SERVO (Pin 10/Pin 7): Error Amplifier AC Input. The
controller servos the switcher output voltage to the VID
DAC voltage through the error amplifier.
VFB (Pin 11/Pin 8): Error Amplifier Negative Input Pin.
VFB is servoed to 1.3V.
COMP (Pin 12/Pin 9): Error Amplifier Output. The COMP
pin is connected directly to the error amplifier output and
the input of the line feedforward circuit. Use an RC network
between the COMP pin and the VFB pin to compensate
the feedback loop for stability and optimum transient
response.
SS (Pin 13/Pin 10): Soft-Start Input. The SS pin has an
internal 1µA current source pull-up. A capacitor connected
to this pin controls the output voltage start-up. SS is
forced low if VRON or PWRGD is low, or if an overvoltage
or overcurrent fault occurs. If the potential at SS is less
than 0.3V, the IMAX sourcing current is reduced to 2.5µA
and the current limit threshold is reduced to 25% of its
nominal value.
DPRSLPVR (Pin 14/Pin 11): Deeper Sleep Mode. For the
IMVP-6 configuration, 25µs after DPRSLPVR is asserted
high, the controller enables the VOUT slow slew rate tran-
sition. To disable slow slew rate mode, force DPRSLPVR
low. Upon power-up, the DPRSLPVR input is ignored until
PWRGD is asserted.
LTC3816
12
3816f
pin FuncTions
(eTSSOP/QFN)
CSLEW (Pin 15/Pin 12): VID DAC Slew Rate Control.
CSLEW is internally pulled up by a current source. Add a
capacitor to program the VID DAC transition slew rate. If
slow slew rate is selected, a 100pF capacitor connected
to CSLEW results in a VID DAC slew rate of 1.25mV/µs.
When slow slew rate is disabled, a 100pF capacitor results
in a VID DAC slew rate of 5mV/µs. Avoid coupling high
frequency switching signals to this pin. For the IMVP-6.5
configuration, the slow slew rate function is disabled.
VID0-VID6 (Pins 16-22/Pins 13-19): VID DAC Voltage
Control Logic Inputs. See Table 1.
RFREQ (Pin 23/Pin 20): Frequency Setting. The voltage
on the RFREQ pin determines the free-running operating
frequency. The RFREQ pin has an internal 10µA current
source pull-up allowing the switching frequency to be
programmed by a single external resistor to GND. Alter-
natively, this pin can be driven with a DC voltage source
to control the frequency of the internal oscillator. Floating
this pin or shorting this pin to INTVCC allows the controller
to run at a fixed 400kHz frequency.
MODE/SYNC (Pin 24/Pin 21): Mode Select/Synchroniza-
tion Input. This pin is pulled up by an internal 1µA current
source. Floating this pin or shorting it to INTVCC enables
pulse-skipping mode. Shorting this pin to ground con-
figures forced continuous mode. During frequency syn-
chronization, the phase-locked loop forces the controller
to operate in continuous mode with the falling top gate
signal synchronized to the falling edge of the MODE/SYNC
input pulse. During start-up, the controller is forced to run
in pulse-skipping mode.
BSOURCE (Pin 25/Pin 22): Bottom MOSFET Source. Con-
nect this pin to the source of the bottom power MOSFET.
Do not short BSOURCE to the LTC3816 exposed pad
directly.
BG (Pin 26/Pin 23): Bottom Gate Drive. The BG pin drives
the gate of the bottom N-channel synchronous switch
MOSFET.
INTVCC (Pin 27/Pin 24): Output of the Internal Linear
Low Dropout Regulator. The driver and control circuits
are powered from this voltage source. The INTVCC pin
must be decoupled to GND with a minimum 4.7µF low
ESR ceramic capacitor (X5R or better).
EXTVCC (Pin 28/Pin 25): External Power Input to an Inter-
nal Switch Connected to INTVCC. This switch closes and
supplies the IC power, bypassing the internal low dropout
regulator, whenever EXTVCC is higher than 4.5V. Do not
exceed 6V on this pin.
VIN (Pin 29/Pin 26): Main Supply Pin. A bypass capacitor
should be connected from this pin to the GND pin.
BOOST (Pin 30/Pin 27): Top Gate Driver Supply. The BOOST
pin should be decoupled to the SW node with a 0.1µF low
ESR (X5R or better) ceramic capacitor. An external Schottky
diode from INTVCC to BOOST creates a complete floating
charge-pumped supply from BOOST to SW.
TG (Pin 31/Pin 28):
Top Gate Drive. The TG pin drives
the top N-channel MOSFET with a voltage swing equal to
INTVCC superimposed on the switch node voltage.
LTC3816
13
3816f
pin FuncTions
(eTSSOP/QFN)
SW (Pin 32/Pin 29): Switching Node. Connect SW to the
source of the upper power MOSFET and to the negative
terminal of the BOOST pin decoupling capacitor.
PWRGD (Pin 33/Pin 30): Open-Drain Power Good Out-
put/Power Bad Latchoff Input. PWRGD is an open-drain
output pin and can be connected to other open-drain
outputs to implement wire-ORing. PWRGD is externally
pulled high 10ms after the output regulates. After start-up,
if a fault condition causes PWRGD to go low, or PWRGD
is externally pulled low, the regulator output voltage is
actively ramped to 0V and PWRGD remains latched low
until either the power is cycled or VRON toggles. PWRGD
has a 750µs de-glitch delay and is masked for 100µs after
the VID code changes. In deeper sleep mode, the PWRGD
comparators are disabled and not allowed to de-assert
the PWRGD pin.
CLKEN# (Pin 34/Pin 31): Open-Drain Clock Enable Indica-
tor. 75µs after VCC(CORE) reaches the VBOOT voltage, CLKEN#
pulls low to enable the processor phase-locked loop.
VRTT# (Pin 35/Pin 32): Open-Drain Output for Voltage
Regulator Thermal Throttling. The VRTT# pin pulls low if
the RPTC voltage exceeds 0.47V or if the control IC junc-
tion temperature exceeds 150°C.
LFF (Pin 36/Pin 33): Line Feedforward. This pin has a
1µA pull-up current source to INTVCC. Floating this pin
or connecting it to INTVCC enables the line feedforward
compensation. Connect this pin to GND to disable the line
feedforward compensation.
ISENP (Pin 37/Pin 34): Current Sense Positive Input. Con-
nect this pin to the positive terminal of the current sense
resistor or to the output of the inductor DCR lowpass
filter.
IMAX (Pin 38/Pin 35): Current Comparator Threshold Set-
ting. The IMAX pin has an internal 10µA pull-up current
source, allowing the current limit comparator threshold to
be programmed by a single external resistor. The control-
ler allows a momentary 45µs overcurrent event to occur
within a period of 630µs. See Current Sense and Current
Limit in Applications Information.
GND (Exposed Pad Pin 39/Exposed Pad Pin 39): Ground.
The soft-start and slew rate control capacitors as well as
the frequency setting and thermal shutdown resistors
should return to this exposed pad ground pin. This GND
pin should also be connected to the negative terminals of
the local voltage regulator output capacitors through vias
to the PCB ground plane.
LTC3816
14
3816f
FuncTional DiagraM
1.65V/1.53V
IMVP-6
2.4V
1.3V
SERVO
DAC – VAVP
+
–
+
–+
–
+
–
+
–
+
–
+
–
+
+
–
+
–
+
–
+
–
OVP
DAC
+ 25mV
DAC + 0.175V
PWM
+
–
ILIM 10µA
100µA
1µA
DAC
INTVCC
INTVCC
4.7V
INTVCC
INTVCC
INTVCC
DA OUT
INTVCC
BSOURCE
OVF
+
–
+
–
NPG PPG
+
–
IREV
AITC
VAVP+
–
LOGIC
LFF
SAW
EN CLK
PWRGD POWER
DOWN
VIN
DELAY
AND
LATCH
ISENP
RPTC
VIN
EXTVCC
LFFDPRSLPVRVRTT#
56Ω
1.1V
ISENN
ITCFB
PREIMON
IMON
VSS(SEN)
VCC(SEN)
VFB
CCRC
COMP
OC FAULT
OV FAULT
GND
ITC
IMAX RIMAX CIDCR
RAVPDCRN
BG
SW
0.47V
TSD
TG CB
QT
QB
DB
DNTC
PTC
COUT
VOUT
L
BOOST
1x
DAMP
CINTVCC
CVDCR
CIMON
IMON
RIDCR
RSER
RPREIMON
RIMON
RPAR
LDO
+
CIN
VIN
+
EA
DAC – 0.270V
1µA
1.2V
ON
SS
VRON
RFREQ
MODE/SYNC
CSLEW
INTVCC
10µA/40µA
BANDGAP
CHIP TSD
CSS
RFREQ
INTVCC
CC1 CFF
R1
1µA
10µA
1µA
VID0-VID6
CSLEW
0.5V/1.6V
CLKEN#
EN CLK
1.9k
3.3V
PWRGD
PWRGD
1.9k
3.3V
Figure 1. Functional Diagram
LTC3816
15
3816f
operaTion
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC(CORE)
0 0 0 0 0 0 0 1.5000
0 0 0 0 0 0 1 1.4875
0 0 0 0 0 1 0 1.4750
0 0 0 0 0 1 1 1.4625
0 0 0 0 1 0 0 1.4500
0 0 0 0 1 0 1 1.4375
0 0 0 0 1 1 0 1.4250
0 0 0 0 1 1 1 1.4125
0 0 0 1 0 0 0 1.4000
0 0 0 1 0 0 1 1.3875
0 0 0 1 0 1 0 1.3750
0 0 0 1 0 1 1 1.3625
0 0 0 1 1 0 0 1.3500
0 0 0 1 1 0 1 1.3375
0 0 0 1 1 1 0 1.3250
0 0 0 1 1 1 1 1.3125
0 0 1 0 0 0 0 1.3000
0 0 1 0 0 0 1 1.2875
0 0 1 0 0 1 0 1.2750
0 0 1 0 0 1 1 1.2625
0 0 1 0 1 0 0 1.2500
0 0 1 0 1 0 1 1.2375
0 0 1 0 1 1 0 1.2250
0 0 1 0 1 1 1 1.2125
0 0 1 1 0 0 0 1.2000
0 0 1 1 0 0 1 1.1875
0 0 1 1 0 1 0 1.1750
0 0 1 1 0 1 1 1.1625
0 0 1 1 1 0 0 1.1500
0 0 1 1 1 0 1 1.1375
0 0 1 1 1 1 0 1.1250
0 0 1 1 1 1 1 1.1125
0 1 0 0 0 0 0 1.1000
0 1 0 0 0 0 1 1.0875
0 1 0 0 0 1 0 1.0750
0 1 0 0 0 1 1 1.0625
0 1 0 0 1 0 0 1.0500
0 1 0 0 1 0 1 1.0375
0 1 0 0 1 1 0 1.0250
0 1 0 0 1 1 1 1.0125
0 1 0 1 0 0 0 1.0000
0 1 0 1 0 0 1 0.9875
0 1 0 1 0 1 0 0.9750
0 1 0 1 0 1 1 0.9625
0 1 0 1 1 0 0 0.9500
0 1 0 1 1 0 1 0.9375
0 1 0 1 1 1 0 0.9250
0 1 0 1 1 1 1 0.9125
0 1 1 0 0 0 0 0.9000
0 1 1 0 0 0 1 0.8875
0 1 1 0 0 1 0 0.8750
0 1 1 0 0 1 1 0.8625
0 1 1 0 1 0 0 0.8500
0 1 1 0 1 0 1 0.8375
0 1 1 0 1 1 0 0.8250
0 1 1 0 1 1 1 0.8125
0 1 1 1 0 0 0 0.8000
0 1 1 1 0 0 1 0.7875
0 1 1 1 0 1 0 0.7750
0 1 1 1 0 1 1 0.7625
0 1 1 1 1 0 0 0.7500
0 1 1 1 1 0 1 0.7375
0 1 1 1 1 1 0 0.7250
0 1 1 1 1 1 1 0.7125
VID6 VID5 VID4 VID3 VID2 VID1 VID0 VCC(CORE)
1 0 0 0 0 0 0 0.7000
1 0 0 0 0 0 1 0.6875
1 0 0 0 0 1 0 0.6750
1 0 0 0 0 1 1 0.6625
1 0 0 0 1 0 0 0.6500
1 0 0 0 1 0 1 0.6375
1 0 0 0 1 1 0 0.6250
1 0 0 0 1 1 1 0.6125
1 0 0 1 0 0 0 0.6000
1 0 0 1 0 0 1 0.5875
1 0 0 1 0 1 0 0.5750
1 0 0 1 0 1 1 0.5625
1 0 0 1 1 0 0 0.5500
1 0 0 1 1 0 1 0.5375
1 0 0 1 1 1 0 0.5250
1 0 0 1 1 1 1 0.5125
1 0 1 0 0 0 0 0.5000
1 0 1 0 0 0 1 0.4875
1 0 1 0 0 1 0 0.4750
1 0 1 0 0 1 1 0.4625
1 0 1 0 1 0 0 0.4500
1 0 1 0 1 0 1 0.4375
1 0 1 0 1 1 0 0.4250
1 0 1 0 1 1 1 0.4125
1 0 1 1 0 0 0 0.4000
1 0 1 1 0 0 1 0.3875
1 0 1 1 0 1 0 0.3750
1 0 1 1 0 1 1 0.3625
1 0 1 1 1 0 0 0.3500
1 0 1 1 1 0 1 0.3375
1 0 1 1 1 1 0 0.3250
1 0 1 1 1 1 1 0.3125
1 1 0 0 0 0 0 0.3000
1 1 0 0 0 0 1 0.2875
1 1 0 0 0 1 0 0.2750
1 1 0 0 0 1 1 0.2625
1 1 0 0 1 0 0 0.2500
1 1 0 0 1 0 1 0.2375
1 1 0 0 1 1 0 0.2250
1 1 0 0 1 1 1 0.2125
1 1 0 1 0 0 0 0.2000
1 1 0 1 0 0 1 0.1875
1 1 0 1 0 1 0 0.1750
1 1 0 1 0 1 1 0.1625
1 1 0 1 1 0 0 0.1500
1 1 0 1 1 0 1 0.1375
1 1 0 1 1 1 0 0.1250
1 1 0 1 1 1 1 0.1125
1 1 1 0 0 0 0 0.1000
1 1 1 0 0 0 1 0.0875
1 1 1 0 0 1 0 0.0750
1 1 1 0 0 1 1 0.0625
1 1 1 0 1 0 0 0.0500
1 1 1 0 1 0 1 0.0375
1 1 1 0 1 1 0 0.0250
1 1 1 0 1 1 1 0.0125
1 1 1 1 0 0 0 0.0000
1 1 1 1 0 0 1 0.0000
1 1 1 1 0 1 0 0.0000
1 1 1 1 0 1 1 0.0000
1 1 1 1 1 0 0 0.0000
1 1 1 1 1 0 1 0.0000
1 1 1 1 1 1 0 0.0000
1 1 1 1 1 1 1 0.0000
Table 1. IMVP-6/IMVP-6.5 VID Output Voltage Programming
(Refer to Funtional Diagram)
LTC3816
16
3816f
Figure 2. LTC3816 Power-Up and Power-Down Timing Diagram
VRON
VID
DPRSLPVR
INTVCC
45mV
VCC(CORE)
VBOOT
tCLKEN#
IMVP-6
SLOW SLEW RATE
NORMAL
SLEW RATE
3816 F02
tCLK(PWRGD)
CLKEN#
PWRGD
The LTC3816 is a constant frequency, voltage mode DC/DC
step-down controller that complies with the Intel IMVP-6/
IMVP-6.5 specifications. The 7-bit VID code programs the
switcher output voltage as specified in Table 1. Figure 2
shows the timing diagram. Upon start-up, the switcher
output soft-start ramps to the VBOOT voltage. 75µs after
reaching the VBOOT power good threshold, which is about
45mV below VBOOT
, the controller forces the CLKEN# pin
low and the VID code is loaded. Next, the output is servoed
to its VID DAC potential. 10ms after regulation, PWRGD
pulls high to indicate that the switcher is regulating and
has completed its start-up phase.
The LTC3816 uses two external synchronous N-channel
MOSFETs. A floating topside driver and a simple external
charge pump provide full gate drive to the upper MOSFET.
The controller uses a leading edge modulation architec-
ture to allow extremely low duty cycles and fast load
step response. In a typical LTC3816 switching cycle, the
PWM comparator turns on the top MOSFET to charge the
output capacitor. An internal clock resets the top MOSFET
and turns on the bottom MOSFET to reduce the output
charging current. This switching cycle repeats itself at an
internally fixed frequency, or in synchronization with an
external oscillator.
The top gate duty cycle is controlled by the voltage feed-
back loop which includes an internal differential amplifier
that senses the differential output voltage between the
VCC(SEN) and VSS(SEN) pins. The AITC amplifier monitors
the inductor current and computes the load dependent
output droop required to implement the active voltage
positioning features in IMVP-6/IMVP-6.5. The IC servos
the differential output voltage to the VID DAC voltage
minus the small load dependent AVP droop.
The LTC3816 feedback loop is capable of dynamically
changing the regulator output to different VID DAC voltages.
Upon receiving a new VID code, the LTC3816 regulates to
its new potential with a programmable slew rate which is
selected to prevent the converter from generating audible
noise. The switcher output load current can be monitored
by measuring the IMON pin potential. The LTC3816 forces
the IMON pin voltage to be proportional to the average
load current with a gain configured by the RPREIMON and
RIMON resistors.
The LTC3816 includes an onboard current limit circuit that
senses the inductor current through an external sense
resistor or the inductor DCR. The peak inductor current
can be controlled by selecting the current limit RIMAX
resistance. The LTC3816 current limit architecture allows
momentary overcurrent events for a predefined duration
(see the Current Sense and Current Limit sections). Upon
current limit, the top gate is shut off, the SS external
capacitor is discharged to limit the top gate duty cycle,
and the switcher output voltage is reduced until the load
fault is removed.
operaTion
(Refer to Funtional Diagram)
LTC3816
17
3816f
applicaTions inForMaTion
LDO, INTVCC/EXTVCC POWER SUPPLY
The LTC3816 is designed to operate with a wide range of
VIN input voltages. The IC includes a 5.2V LDO to power
the driver and control circuits. The LDO output, INTVCC
should be bypassed with a minimum 4.7µF low ESR
ceramic capacitor. The INTVCC regulator can supply up to
50mA of total LTC3816 quiescent current, IQ(TOT), which
consists of the static supply current, IQ, and the current
required to charge the gate capacitance, QG(TOT), of the
top and bottom power MOSFETs.
IQ(TOT) = IQ + QG(TOT) • fOSC
PDISS = VIN • (IQ + QG(TOT) • fOSC)
TJ = TA + PDISS • θJA
The value of QG(TOT) can be obtained from the MOSFET
data sheets. For high VIN and high frequency operation,
care must be taken to ensure that the maximum junction
temperature TJMAX of the IC is never exceeded.
When the EXTVCC pin is left open or tied to a voltage less
than 4.5V, the 5.2V LDO powers INTVCC. If EXTVCC is taken
above 4.5V, the LDO is turned off and an internal switch
connects INTVCC to EXTVCC. Do not apply greater than 6V
to the EXTVCC pin, and ensure that EXTVCC < VIN + 0.3V
unless EXTVCC is shorted to the VIN supply. Using the
EXTVCC pin allows INTVCC to be powered from an external
source reducing LDO losses and improving the regulator
efficiency, especially at high VIN. When the EXTVCC pin is
used, the chip power dissipation reduces to:
PDISS = VEXTVCC • (IQ + QG(TOT) • fOSC)
If the VIN supply is low enough for the INTVCC LDO to enter
dropout, the output voltage of the LDO becomes:
VINTVCC(DROPOUT) = VIN – VDROPOUT
The LDO dropout voltage is a function of the total quies-
cent current IQ(TOT), VIN voltage and junction temperature.
The temperature coefficient of the LDO dropout voltage
is approximately 6400ppm/°C. To enable proper opera-
tion, make sure that the LDO output voltage meets the
INTVCC undervoltage and minimum MOSFET gate driver
requirements. If VIN is connected to a fixed 5V supply, it is
advisable to short EXTVCC to VIN. In this case, the INTVCC
output voltage becomes:
VINTVCC(EXTVCC) = VEXTVCC – IQ(TOT) • REXTVCC
where REXTVCC is the internal EXTVCC switch on-resistance.
It has a typical value of 2Ω at 25°C and has a temperature
coefficient of approximately 4000ppm/°C.
UNDERVOLTAGE LOCKOUT AND SHUTDOWN
A precision undervoltage lockout (UVLO) comparator
monitors the INTVCC voltage and enables soft-start opera-
tion once INTVCC is above 3.9V. For power supplies that
start-up slowly, the gate drivers could begin switching
when VIN is well below its steady-state value. The high
inrush current through the input power cable could cause
the VIN supply to dip below the UVLO threshold and result
in hiccup operation at start-up. This problem can be eas-
ily overcome by adding a VIN UVLO function as shown in
Figure 3. Connect an external resistive divider from VIN to
VRON. Set the resistive divider according to the following
equation:
V V V R
R R
UVLO IN UVLO ON
ON ON
= = +
1 2 1
1 2
.( )
where VIN(UVLO) is the desired VIN UVLO threshold. The
resistances are normally chosen so that the error caused
by the internal 1µA pull-up current has a negligible effect
on the UVLO threshold. Be careful not to allow the resistive
divider output voltage to exceed the 6V maximum rating
of the VRON pin.
If the external resistive divider is not used, upon power-
up, the VRON pin is pulled up by an internal 1µA pull-up
current. The LTC3816 can be put into a low power shut-
Figure 3. VIN UVLO Circuit
+
–
SHUTDOWN
RON2
VIN
VRON
1µA
LTC3816
ON
RON1 1.2V
3816 F03
LTC3816
18
3816f
applicaTions inForMaTion
down mode by pulling the VRON pin below 0.65V. In the
shutdown mode, the internal circuitry and the INTVCC
regulator are off and the supply current drops well below
100µA. When the VRON pin voltage is between 0.65V and
1.2V, the INTVCC regulator and internal circuitry power up
but the driver outputs remain low.
TOPSIDE MOSFET DRIVER SUPPLY
An external bootstrap capacitor, CB, connected from the
BOOST pin to the SW pin supplies the topside gate driver
as shown in Figure 1. Capacitor CB is charged though the
external diode, DB, from INTVCC when the SW pin is low.
When the topside MOSFET is turned on, the top driver
places the CB voltage across the gate source of the top
MOSFET. This enhances the MOSFET and turns on the
top switch. The switch node voltage, SW, rises to VIN and
the BOOST pin follows. With the topside MOSFET on, the
boost voltage is above the input supply:
VBOOST = VIN + VINTVCC
The value of the boost capacitor, CB, needs to be at least
100 times that of the total input capacitance of the topside
MOSFET. The reverse breakdown of the external Schottky
diode, DB, must be greater than VIN(MAX).
IMVP-6/IMVP-6.5 SELECTION AND VBOOT VOLTAGE
The LTC3816 can be configured to meet either IMVP-6
or IMVP-6.5 requirements. To select IMVP-6 operation,
short both IMON and PREIMON to INTVCC. At start-up, when
VRON is asserted, the switcher output ramps to VBOOT =
1.2V regardless of the VID code. To configure IMVP-6.5
operation, connect a resistor from IMON to VSS(SEN) and
another resistor from PREIMON to ITC. The IMON and
PREIMON resistance set the IMON gain (see the IMON sec-
tion). The VBOOT voltage for IMVP-6.5 is 1.1V.
SOFT-START OPERATION
The start-up of VOUT is controlled by the LTC3816’s SS
pin. When the voltage at the SS pin is less than 1.3V, the
LTC3816 regulates the VFB voltage to the SS pin voltage
instead of 1.3V. This allows the user to program the soft-
start of the regulator output with a capacitor from the SS
pin to GND. An internal 1µA current source charges this
capacitor, creating a voltage ramp on the SS pin. As the
SS pin voltage rises from 0V to 1.3V, the output voltage,
VOUT
, rises smoothly from 0V to its VBOOT value. Once
the soft-start interval is over, the internal current source
continues charging the SS capacitor until the SS poten-
tial is internally clamped at about 2.7V. For the IMVP-6
configuration, a 1000pF SS capacitor generates roughly
a 1.6ms start-up time. With the IMVP-6.5 configuration,
the start-up time is about 1.5ms.
During severe overload conditions, the LTC3816 discharges
the SS capacitor to lower the switcher output voltage. If the
potential at SS is forced below 0.3V, the controller reduces
its IMAX sourcing current from 10µA to 2.5µA and cuts the
short-circuit current to about 25% of its nominal value.
CURRENT SENSE AND CURRENT LIMIT
The LTC3816 features an onboard cycle-by-cycle user-
programmable current limit circuit that controls the peak
inductor current. The IMAX pin has an internal 10µA pull-
up current source, allowing the maximum load current
ILOAD(MAX) to be programmed by a single external resistor
RIMAX connected between the IMAX and ISENN pins.
II R
R
I I I
L PEAK IMAX IMAX
SENSE
LOAD MAX LIMIT L
( )
( ) (
•
=
< = PPEAK L IMAX IMAX
SENSE
L
I I R
R
I
)–•–
∆ ∆
2 2
=
where IL(PEAK) is the peak inductor current, IIMAX is the IMAX
pin pull-up current, RSENSE is the current sense resistor
value and ∆IL is the inductor ripple current.
∆If L VV
V
LOSC OUT OUT
IN
=
11
•–
Note that the output ripple current varies with the switch-
ing frequency, inductor value and duty cycle. Hence, the
current limit value should be checked on the application
board to ensure that ILOAD(MAX) < ILIMIT under all operating
conditions and temperature variations.
For current sensing using a low value sense resistor, the
sense resistor parasitic inductance must be considered to
LTC3816
19
3816f
applicaTions inForMaTion
achieve accurate current sensing. Figure 4 shows a real
current sensing resistor, RSENSE, which can be modeled
with an ideal resistance, RSEN, in series with its parasitic
ESL. As shown in Figure 4, the voltage across the sense
resistor includes the voltage across the parasitic induc-
tor which is a strong function of inductor ripple current
and the switching frequency. This effectively reduces the
current limit threshold, typically by more than 30%. The
voltage across the sense resistor can be extracted from
a lowpass filter placed close to the controller input sense
pins as shown in Figure 4. The voltage across the sensing
capacitor, CISR, is:
V I R
sESL
R
sR C
CISR L SEN SEN
ISR ISR
=
+
+
••
1
1
In the frequency domain, the second term in the above
equation must be equal to 1 to ensure that the voltage
across the filter capacitor is independent of operating
frequency. To meet this requirement, the value of the RC
filter should fulfill the following condition:
R C ESL
R
ISR ISR SEN
•=
The ESL value can be obtained from the manufacturer ’s
data sheet or estimated with an oscilloscope, as shown in
the Figure 4 waveform, using the following equation:
ESL V V
It t
ESL ON ESL OFF
LON OFF
=+
+
( ) ( )
∆1 1
where tON is the TG on time and tOFF is the TG off time.
For high efficiency applications, the inductor DCR provides
a method of sensing the inductor current without incurring
additional power loss from a sense resistor. The DCR of
the inductor represents the small amount of resistance
in the copper winding, which can be less than 1mΩ for
today ’s low value, high current inductors. Figure 5 shows
a simplified inductor model, which can be modeled with an
ideal inductor, L, in series with its parasitic DCR. The DCR
value can be obtained from the inductor manufacturer ’s
data sheet. Similar to the sense resistor application circuit,
the voltage across the inductor DCR can be extracted from
a lowpass filter and the current limit threshold is given by
the following equation:
II R
R
I I I
L PEAK IMAX IMAX
DCR
LOAD MAX LIMIT L PE
( )
( ) (
•
=
< = AAK L IMAX IMAX
DCR
L
IDCR IDCR
I I R
R
I
if R C L
R
)–•–
•
∆ ∆
2 2
=
=
DDCR
+
QBD
L
QT
VIN
ESL
COUT
VOUT
IL
SENSE RESISTOR
RSEN
RISR
VISR
RIMAX
CISR
TG
BG
BSOURCE
ISENP
ISENN
IMAX
LTC3816
SW
VESL(OFF)
VESL(ON)
3816 F04
VISR = VRSEN + VESL
VRSEN = IL • RSEN
Figure 4. Current Limit Sensing Using
a Low Value Sense Resistor
+
QBD
QT
VIN
L
COUT
3916 F05
VOUT
IL
INDUCTOR
DCR
RIDCR
RIMAX
CIDCR
TG
BG
BSOURCE
ISENP
ISENN
IMAX
LTC3816
SW
Figure 5. Current Limit Sensing Using Inductor DCR
LTC3816
20
3816f
applicaTions inForMaTion
Note that the value of RDCR must account for its temperature
coefficient, which is approximately 0.39%/°C.
The current limit architecture of the LTC3816 allows short
durations of instantaneous overload. Upon power-up, the
current limit threshold is set to 1×, equal to ILIMIT
. The
load is limited to ILIMIT until the switcher output reaches
its VBOOT potential. Beyond this point, during the VID DAC
slewing interval, the IMAX sourcing current automatically
switches from 10µA to 20µA and the current limit threshold
increases to 2× to enable the output capacitor voltage to
track the DAC transition. If the controller detects that there
is an overload condition when the DAC is not slewing, the
current limit threshold increases to 2× for a duration of
45µs. If the overload interval is shorter than 45µs, the IC
allows another overcurrent event within the next 630µs,
as shown in Figure 6a. However, if an overload occurs
within the 630µs following the second event, the controller
current limits, as shown in Figure 6b.
If the overload condition persists for more than 45µs,
the LTC3816 allows the 2× current limit to continue for
CURRENT LIMITED
20µA
10µA
ILOAD
2s
45µs
<45µs
<630µs
1s
IIMAX
45µs 45µs
<45µs <45µs
3816 F06a
>630µs
Figure 6a. Permissible Overload
CURRENT LIMITED
20µA
10µA
ILOAD
2s
45µs
<45µs
<630µs <630µs
1s
IIMAX
45µs
<45µs <45µs
3816 F06b
Figure 6b. Repeated Overload Triggers Current Limit
another cycle. After 90µs, the IMAX current returns to 10µA,
and the output load is limited to 1× for the next 630µs as
shown in Figure 6c. Figure 6d shows the condition when
a repetitive overload event triggers current limit.
Figure 6e shows that at any instant, if the load current
is above 1× for more than 90µs, or higher than 2×, the
controller enters current limit. Under this condition, the TG
duty cycle is reduced and the SS capacitor is discharged
CURRENT LIMITED
20µA
10µA
ILOAD
2s
90µs
1s
IIMAX
<45µs
3816 F06c
45µs < t < 90µs
45µs
>630µs
Figure 6c. Allowable Longer Overload Condition
CURRENT LIMITED
20µA
10µA
ILOAD
2s
90µs
1s
IIMAX
<45µs
3816 F06d
45µs < t < 90µs
<630µs
Figure 6d. Allowable Longer Overload Condition,
Followed by Repeated Overload Triggers Current Limit
CURRENT LIMITED
20µA
10µA
ILOAD
2s
90µs
>90µs
1s
IIMAX
45µs
<45µs
3816 F06e
>630µs
Figure 6e. Long Overload or Excessive Loading
Triggers Current Limit Condition
LTC3816
21
3816f
applicaTions inForMaTion
to lower the regulator output voltage. This current limit
condition persists until the fault condition disappears or
the controller detects a low output voltage fault and forces
the switcher output to latch off. Once the output voltage
is lower than the power good threshold, the controller
limits the maximum load to 1× to reduce the short-circuit
current.
ACTIVE VOLTAGE POSITIONING (AVP)
In a conventional buck converter, the feedback control
regulates the output voltage to the same level for the
entire load range as shown in Figure 7a. The peak-to-peak
output voltage spikes resulting from the load step must
be smaller than the voltage tolerance window.
To reduce the regulator output voltage peak-to-peak
perturbation resulting from a load transient, the LTC3816
modulates the output voltage based on the output loading
current. The built-in AVP circuit lowers the output voltage
proportional to the load current as shown in Figure 7b.
Figure 7c shows the transient response with the AVP
function. The AVP voltage droop reduces the peak-to-peak
output voltage perturbation. As a result, the AVP topology
requires fewer capacitors at the regulator output to achieve
the same voltage tolerance window.
The AVP circuit obtains the load current information from
the sense resistor or the inductor DCR as shown in Figure 8.
The voltage drop across the sense resistor is extracted
Figure 7a. Transient Waveform Without AVP. The Transient
Peak-to-Peak Spike ≈ 130mV. The AITC Amplifier is
Configured as a Unity-Gain Amplifier
Figure 7b. AVP DC Transfer Curve
Figure 7c. Transient Waveform with AVP Slope = –3mV/A, Using
The Same Inductor and Output Capacitor as Figure 7a. The
Transient Peak-to-Peak Perturbation is Reduced to About 85mV
VOUT
50mV/DIV
ILOAD
10A/DIV
VSW
20V/DIV
VIN = 12V
VOUT = 1V
ILOAD = 0A TO 20A
20µs/DIV 3816 F07a
ILOAD (A)
0
0.88
VOUT (V)
% FROM IDEAL NO-LOAD VALUE
0.91
0.94
0.97
1.00
1.03
–12
–9
–6
–3
0
3
510 15 20
3816 F07b
25 30
PROGRAMMABLE
AVP SLOPE
VOUT
50mV/DIV
ILOAD
10A/DIV
VSW
20V/DIV
VIN = 12V
VOUT = 1V
ILOAD = 0A TO 20A
20µs/DIV 3816 F07c
by the AITC amplifier and summed with the differential
amplifier output voltage. The resulting output is servoed
to the VID DAC voltage. At higher load current, the volt-
age drop across the sense resistor increases, resulting
in a lower switcher output voltage. Typically, the system
requirement defines the amount of AVP gain ensuring
that the output voltage remains within the regulator sup-
ply tolerance band over the full range of load conditions.
Figure 8 includes the components required to compensate
for the sense resistor parasitic inductance. The AVP DC
transfer function is:
VOUT = VDAC – AAVP(SR) • IL = VDAC – AG(SR) • IL • RSEN
LTC3816
22
3816f
applicaTions inForMaTion
where AAVP(SR) is the AVP gain with sense resistor con-
figuration and AG(SR) is the sense resistor gain:
A A R and A R
Rtt
R
AVP SR G SR SEN G SR VSR
AVPSR
VS
( ) ( ) ( )
•= =
RR VSR SEN
CESL
R
•=
Figure 9 shows the AVP configuration with current sense
implemented using the inductor DCR. The AVP DC transfer
function is:
VOUT = VDAC – AAVP(DCR) • IL = VDAC – AG(DCR) • IL • RDCR
where:
A A R and A R
R
AVP DCR G DCR DCR G DCR VDCR
AVPDCR
( ) ( ) ( )
•= =
RR C L
R
VDCR VDCR DCR
•=
TEMPERATURE COMPENSATED ACTIVE VOLTAGE
POSITIONING (AVP) WITH INDUCTOR DCR
The inductor DCR AVP configuration improves the regula-
tor efficiency by eliminating the power losses associated
with a sense resistor. However, without proper temperature
compensation, the positive temperature coefficient of the
inductor DCR, 0.39%/°C, may compromise the output volt-
age accuracy. As the temperature of the inductor rises, its
DCR value increases, resulting in a greater VOUT droop rate
(higher AVP gain). To compensate for the DCR temperature
shift, replace the resistor RVDCR in Figure 9 with an NTC
resistor placed as close as possible to the inductor. Ideally,
the NTC resistor should have the same temperature as the
inductor. As temperature increases, the NTC resistance
drops, resulting in a reduction in the AITC amplifier voltage
gain. This compensates for the increase in DCR resistance
and maintains the AVP gain. The NTC resistor, however, is
highly nonlinear and must be linearized. Figure 10 shows
+
QBD
QT
VIN
ESLL
COUT
3916 F08
VOUT
IL
SENSE RESISTOR
RSEN
CVSR
RAVPSR
TG
BG
BSOURCE
ITCFB
ISENN
ITC
LTC3816
SW
+
–RVSR
AITC
+
QBD
QT
VIN
L
COUT
3916 F09
VOUT
IL
INDUCTOR
DCR
CVDCR
RAVPDCR
TG
BG
BSOURCE
ITCFB
ISENN
ITC
LTC3816
SW
RVDCR
+
–
AITC
Figure 8. AVP Configuration with a Sense Resistor
Figure 9. AVP Configuration with Inductor DCR Current Sense
+
QBD
QT
VIN
L
COUT
3916 F10
VOUT
IL
INDUCTOR
DCR
NTC
CVDCRN
RAVPDCRN
TG
BG
BSOURCE
ITCFB
ISENN
ITC
LTC3816
SW
RPAR
RSER
+
–
AITC
Figure 10. AVP with Inductor DCR Current Sense
and NTC Temperature Compensation
LTC3816
23
3816f
applicaTions inForMaTion
the NTC compensation network. To determine the compo-
nent values, first, select the NTC with room temperature
resistance approximately equal to RVDCR that has the
smallest temperature coefficient (β constant in the NTC
data sheet. Using an NTC with a higher β constant gen-
erates a less optimal temperature compensation). Next,
calculate the resistances RPAR and RSER from the following
equations where the NTC resistances at different tempera-
tures is obtained from the manufacturer’s data sheet.
R R at C
R R R at C
PAR NTC
SER PAR NTC
= °
≈ °
( )
( )
|| –
25
10
30 RR R at C
R R at C
PAR NTC
PAR NTC
||
– ||
75
25
°
( )
( )
°
( ))
( )
Note that the above equations optimize temperature
compensation at hot. At extreme cold temperature, the
temperature compensation is less effective.
With the NTC resistor network, the temperature compen-
sated AVP transfer function becomes:
VOUT = VDAC – AAVP(DCRN) • IL = VDAC – AG(DCRN) • IL • RDCR
where AAVP(DCRN) and AG(DCRN) are the AVP and DCR gain
using the inductor DCR current sense with NTC temperature
compensation configuration.
A A R and A R
R
AVP DCRN G DCRN DCR G DCRN NTCNET
A
( ) ( ) ( )
•= =
VVPDCRN
VDCRN NTCNET DCR
NTCNET SER PAR
CL
R R
R R R R
=
= +
•
|| NNTC
( )
Figure 11a shows the room temperature AVP DC transfer
curves obtained using inductor DCR current sense with and
without NTC temperature compensation. There is only a
slight difference in the transfer curve at heavy load. Figure
11b shows the AVP transfer curve obtained at 125°C, it
shows the improvement in AVP accuracy with the NTC
resistor network.
Figure 12 shows another easy way to compensate for the
inductor DCR temperature coefficient. In this configura-
tion, a linear PTC resistor is connected from the SW node
to the ITCFB pin. The PTC thermistor ’s temperature coef-
ficient of 0.411%/°C compensates for the change in DCR
ILOAD (A)
0
VOUT (V)
0.97
0.98
0.99
15 25
3816 F11a
0.96
0.95
0.94 5 10 20
1.00
1.01
1.02
30
IDEAL + 1.5%
IDEAL
IDEAL – 1.5%
WITH NTC
WITHOUT NTC
TA = 25°C
Figure 11a. AVP Transfer Curve Using Vishay
IHLP-5050CE-01 0.33µH (DCR = 1.3mΩ) Inductor
DCR Current Sense with AG(DCRN) = 1 at TA = 25°C
ILOAD (A)
0
VOUT (V)
0.97
0.98
0.99
15 25
3816 F11b
0.96
0.95
0.94 5 10 20
1.00
1.01
1.02
30
IDEAL + 1.5%
IDEAL
IDEAL – 1.5%
WITH NTC
WITHOUT NTC
TA = 125°C
Figure 11b. Same Setup as Figure 11a. Improvement
in AVP Accuracy with NTC Temperature Compensation
Network at TA = 125°C
+
QBD
QT
VIN
L
COUT
3916 F12
VOUT
IL
INDUCTOR
DCR
LPTC
CVDCRP
LPTC: VISHAY TPFT1206 SERIES, 4110ppm/°C
TG
BG
BSOURCE
ITCFB
ISENN
ITC
LTC3816
SW
RVDCRP
+
–
AITC
Figure 12. AVP Using Inductor DCR Current Sense
with Linear PTC Temperature Compensation
LTC3816
24
3816f
applicaTions inForMaTion
resistance (0.39%/°C) and produces a near perfect AVP
slope across temperature.
VOUT = VDAC – AAVP(DCRP) • IL = VDAC – AG(DCRP) • IL • RDCR
where:
A A R and A R
R
AVP DCRP G DCRP DCR G DCRP VDCRP
LP
( ) ( ) ( )
•= =
TTC
VDCRP VDCRP DCR
CL
R R
=•
IMON
To facilitate CPU monitoring of load current in an IMVP-6.5
application, the LTC3816 forces the IMON pin voltage to
be proportional to the average load current. As shown in
Figure 13, the AITC and the unity-gain amplifiers force
the voltage across the resistor RPREIMON to be equal to
the voltage drop across the sense resistor. A current is
supplied to RIMON that is three times greater than the cur-
rent in RPREIMON. The voltage across the RIMON resistor
is equal to:
V I R R
R
R
R
IMON L SEN VSR
AVPSR
IMON
PREIMON
=
( )
3• • •
To prevent the ground difference between the CPU and
the regulator from affecting the IMON voltage accuracy,
the negative terminal of the resistor RIMON should be
connected directly to the CPU VSS(SEN) pin. Depending
on the output load requirements, the IMON voltage gain
can be programmed by changing the ratio of the RIMON
and RPREIMON resistances. A capacitor should be added
in parallel with the resistor RIMON to remove the switching
ripple. The value of the capacitor CIMON is determined by
the following equation:
Ct
R
IMON IMON
IMON
=
where tIMON is the IMON time constant and must be larger
than 300µs.
In the IMVP-6.5 configuration, the IMON pin potential is
internally clamped to 1.1V with respect to the VSS(SEN) pin
voltage. Forcing the PREIMON pin to INTVCC configures the
LTC3816 as an IMVP-6 regulator.
FEEDBACK CONTROL
The LTC3816 feedback loop consists of the line feed-
forward circuit, the modulator, the external inductor, the
output capacitor, the AITC and differential amplifier, and
the feedback amplifier with its compensation network. All
of these components affect loop behavior and need to be
accounted for in the loop compensation.
Line Feedforward and Modulator
The modulator consists of the PWM generator, the output
MOSFET drivers and the external MOSFETs themselves.
The modulator gain varies linearly with the input voltage.
The line feedforward circuit compensates for this change in
gain and provides a constant gain from the error amplifier
output to the SW node regardless of input voltage. From
a feedback loop point of view, the combination of the line
feedforward circuit and the modulator looks like a linear
voltage transfer function from COMP to the SW node and
has a gain roughly equal to:
AMOD ≈ 25V/V ≈ 28dB
It has a fairly benign AC behavior at typical loop compen-
sation frequencies with significant phase shift appearing
at half the switching frequency.
+
QBD
L
QT
VIN
ESL
COUT
VOUT
IL
SENSE RESISTOR
RSEN
RAVPSR
TG
BG
BSOURCE
ITC
ITCFB
ISENN
PREIMON
IMON
IMON
3816 F13
VSS(SEN)
INTVCC
LTC3816
SW
RVSR
CVSR
RPREIMON
RIMON CIMON
1X
+
–
AITC
Figure 13. IMON Configuration
LTC3816
25
3816f
applicaTions inForMaTion
LC Filter
The external inductor and output capacitor combination
causes a second order LC roll-off at the output with 180°
of phase shift. At higher frequencies, the reactance of the
output capacitor approaches its ESR, and the roll-off due to
the capacitor stops, leaving –20dB/decade and 90° of phase
shift. Beyond the ESR zero, the ceramic capacitor creates a
high frequency pole. The LC filter transfer function, poles
and zero locations are given by the following equations:
AV
V
sR C
s L C SR C
LC OUT
SW
ESR BULK
L OUT L OUT
= ≈ +
+ +
( )
1
1
1
2
•
•
11
1
2
+
=
sR C C
C
fL C
ESR BULK CER
OUT
LC DOUBLE POLE
L OU
•
( _ ) πTT
ESR ZERO ESR BULK
CER POLE
ESR
fR C
f
RC
( )
( )
• •
•
=
=
1
2
1
2
π
πBBULK CER
OUT
C
C
•
where:
RL includes DCR, sense resistance, PCB trace resistance
and the turn-on resistance of the power MOSFET.
LL includes the inductor inductance, PCB trace induc-
tance and sense resistor ESL.
COUT = CBULK + CCER
AITC and Differential Amplifiers
With the sense resistor configuration, the AITC and the
differential amplifiers add a double zero and a pole in the
vicinity of the feedback loop crossover frequency, fC, and
multiple poles at higher frequencies. The simplified low
frequency transfer function from the regulator output node
to the SERVO pin, as shown in Figure 14a, is given by the
following equation:
V
V
sA s B
sR C
SERVO
OUT
SR SR
ESR BULK
≈+ +
+
1
1
2
( ) ( )
•
where:
A(SR) = RESR • CBULK + AG(SR) • RSEN • COUT
B(SR) = AG(SR) • RSEN • RESR • CBULK • CCER
Similarly, for the DCR configuration with NTC compen-
sation, the simplified low frequency transfer function is
given by:
V
V
sA s B
sR C
SERVO
OUT
DCR DCR
ESR BULK
≈+ +
+
1
1
2
( ) ( )
•
where:
A(DCR) = RESR • CBULK + AG(DCR) • RDCR • COUT
B(DCR) = AG(DCRN) • RDCR • RESR • CBULK • CCER
Note that with either the sense resistor or the DCR current
sense configuration, the AVP circuitry introduces a pole at
the same location as the LC lowpass filter ESR zero. This
cancels the increase in gain and phase caused by the ESR
zero. Fortunately, the zero in the AVP transfer function is
typically within the closed-loop bandwidth and provides a
beneficial phase boost at the crossover frequency.
Error Amplifier
The error amplifier provides most of the low frequency
loop gain and servos the switcher output voltage to the
VID DAC potential minus the AVP droop. After selecting
the inductor, the output capacitor and the AVP component
values, the control loop is compensated by tailoring the
frequency response of the error amplifier. A typical LTC3816
application uses Type 3 compensation to frequency com-
pensate the feedback loop. Figure 14a and Figure 14b
show the LTC3816 error amplifier Type 3 configuration.
The transfer function of this amplifier is given by the fol-
lowing equation:
V
V
sR C sR C
sR C C
COMP
SERVO
C C FF
C C
=+
( )
+
( )
+
( )
+
–• •1 1 1
1 1
1ssR C C
C C
CC C
C C
•1
1
+
The error amplifier component values can be obtained
using the following guidelines.
LTC3816
26
3816f
applicaTions inForMaTion
+
L
VIN
ESL
CBULK
VOUT
IL
SENSE RESISTOR
RSEN
RAVPSR
TG
BG
BSOURCE
SERVO COMP
LTC3816
VFB
1.3V
R1
CFF
ITC
ITCFB
ISENN
VSS(SEN)
VCC(SEN) 3816 F14a
SW SW
RESR
RC
RVSR
CVSR
+
–
AITC
CCER
+
–
EA
CC
CC1
+
–
DAMP
Figure 14a. LTC3816 Frequency Compensation with Sense Resistor Configuration
+
VIN
L
CBULK
VOUT
IL
INDUCTOR
NTC
DCR
RAVPDCRN
TG
BG
BSOURCE
SERVO COMP
LTC3816
VFB
1.3V
R1
CFF
ITC
ITCFB
ISENN
VSS(SEN)
VCC(SEN) 3816 F14b
SW SW
RESR
RC
RPAR
CVDCRN RSER
+
–
AITC
CCER
+
–
EA
CC
CC1
+
–
DAMP
Figure 14b. LTC3816 Frequency Compensation with DCR Configuration
LTC3816
27
3816f
applicaTions inForMaTion
1. Select fC = feedback crossover frequency =
f
N
OSC
where N is between 5 and 10.
2. At the feedback loop crossover frequency, fC, the loop
gain is unity, therefore the error amplifier gain is:
V
VA A V
V
COMP
SERVO MOD LC SERVO
OUT
=1
• •
3. Place the error amplifier zero near the LC filter double-
pole frequency:
fR C L C
EA ZERO C C L OUT
( ) • •
= ≈
1
2
1
2
ππ
4. The feedforward zero is positioned to give the required
phase boost at the crossover frequency:
fR C
FF ZERO FF
( ) • •
=1
2 1π
5. Place the error amplifier pole at 5fC to suppress the
switching noise.
f
RC C
C C
f
EA POLE
CC C
C C
C( )
••
=
+
=
1
2
5
1
1
π
Compensating the switching power supply voltage feed-
back loop is a complex task. The frequency compensation
equations shown in this data sheet were obtained using
some approximations to simplify the calculations. The
compensation values shown in this data sheet are typi-
cal values, optimized for the power components shown
in the circuit. Though similar power components should
suffice, substantially changing even one major power
component or circuit layout may degrade performance
significantly. To verify the calculated component values,
all new circuit designs should be prototyped and tested
for stability.
LINE FEEDFORWARD (LFF)
The LTC3816 incorporates a line feedforward function to
compensate for changes in the line voltage and to simplify
the frequency compensation. On the other hand, with
the line feedforward enabled, the feedback loop has high
modulator gain and is more sensitive to noise pickup.
If the input supply voltage is low (e.g., around 5V) and
well regulated, it is better to disable the LFF function by
shorting the LFF pin to GND. Without LFF , the modulator
gain AMOD(WOLFF) is reduced and the control loop is less
sensitive to noise injection.
AMOD(WOLFF) ≈ 0.85 • VIN
If line feedforward is disabled, the control loop needs to
be recompensated in order to account for the reduction
in modulator gain.
DPRSLPVR AND VID DAC SLEW RATE CONTROL
The LTC3816 allows the user to program the VID DAC
voltage transition slew rate by adding a capacitor at the
CSLEW pin. In the IMVP-6.5 mode, CSLEW is internally
pulled up by a 40µA current source. Upon a code transition
command, CSLEW is ramped up by the internal current
source. When the capacitor, CSLEW
, potential reaches 1V,
the VID DAC output voltage jumps by 1 LSB (12.5mV) and
the controller resets the CSLEW capacitor. This operation
repeats until the DAC reaches its target value. The DAC
voltage slew rate is given by the following equation:
dV
dt mV I
C
DAC CSLEW
SLEW
=12 5. •
where ICSLEW = 40µA.
When the IMVP-6 configuration is selected, the LTC3816
allows two different slew rates as shown in Figure 15.
To configure the normal slew rate, short the pin DPRSLPVR
to ground. To configure for a slower slew rate, force the
DPRSLPVR pin potential above 1.6V. 25µs after the control-
ler detects a low-to-high transition at the DPRSLPVR pin,
LTC3816
28
3816f
applicaTions inForMaTion
Figure 15. Programmable VID Slew Rate
VOUT
100mV/DIV
VID5
1V/DIV
DPRSLPVR
5V/DIV
VIN = 12V
VOUT = 0.75V TO 1.15V
CSLEW = 47pF
IMVP-6 CONFIGURATION
0.1ms/DIV
3816 F15
the controller reduces the ICSLEW pull-up current from 40µA
to 10µA (deeper sleep mode). This effectively reduces the
VID DAC slew rate to 1/4 of its original value. If IMVP-6.5
is selected, the slow slew rate function is disabled.
PULSE-SKIPPING AND FORCED CONTINUOUS MODE
OPERATION
The LTC3816 can operate in one of two modes select-
able with the MODE/SYNC pin: pulse-skipping mode
or forced continuous mode. Shorting the MODE/SYNC
pin to INTVCC selects pulse-skipping mode. Pulse-skip-
ping mode is selected when high efficiency at very light
loads is desired. In this mode, when the inductor current
reverses, the bottom MOSFET turns off to minimize the
efficiency loss due to reverse current flow. This reduces
the conduction loss and slightly improves the efficiency.
As the load reduces, the top gate duty cycle shrinks to
maintain regulation. The LTC3816 is capable of operating
at extremely low duty cycles; hence, TG will continue to
run at a constant switching frequency until the top gate
on-time is less than 40ns to 50ns. When the load decreases
beyond this point, the LTC3816 TG begins to skip cycles
to maintain regulation. The driver switching frequency
drops, which further improves efficiency by minimizing
gate charge losses.
Forcing the MODE/SYNC pin low enables forced continuous
mode operation. In forced continuous mode, the bottom
MOSFET is always on when the top MOSFET is off, allowing
the inductor current to reverse at low currents. This mode
is less efficient due to conduction and switching losses,
but has the advantage of better transient response at low
currents, constant frequency operation, and the ability to
maintain regulation when sinking current.
During soft-start, the LTC3816 forces the controller to
operate in pulse-skipping mode until the switcher output
voltage reaches its VBOOT power good threshold. During
VID code transitions, however, the controller always oper-
ates in forced continuous mode to allow the switcher to
sink current.
OPERATING FREQUENCY/FREQUENCY
SYNCHRONIzATION
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires a larger inductance and/or capacitance to
maintain low output voltage ripple. For converters with
high step-down VIN-to-VOUT ratios, another consideration
is the minimum on-time of the converter.
tV
V f
ON MIN OUT
IN MAX OSC
( ) ( ) •
=
If the MODE/SYNC pin is not driven by an external clock,
the RFREQ pin voltage configures the LTC3816 free-run-
ning switching frequency. Floating or shorting the RFREQ
pin to INTVCC allows the controller to run at the nominal
400kHz frequency. Connecting the RFREQ pin to GND
selects 210kHz. Tying RFREQ to a potential between 2.5V
and 3.5V selects 580kHz. The RFREQ pin has an internal
LTC3816
29
3816f
applicaTions inForMaTion
VRFREQ (V)
0
100
fOSC (kHz)
200
300
400
500
0.6 1.2 1.8 2.4
3816 F16
600
700
0.3 0.9 1.5 2.1
SYNCHRONIZATION
FREE
RUNNING
Figure 16. VCO Transfer Curve
10µA current source pull-up. Placing a resistor between
RFREQ and GND creates a potential given by the follow-
ing equation:
VRFREQ = IRFREQ • RRFREQ
where IRFREQ = 10µA and allows the oscillator free-running
frequency to be programmed between 210kHz to 580kHz
as shown in Figure 16.
An internal phase-locked loop (PLL) allows the LTC3816
to synchronize the internal oscillator to an external clock.
When there is a clocking signal at the MODE/SYNC pin, the
LTC3816 phase detector adjusts the internal PLL VCO input,
synchronizing the switching frequency to the external clock
frequency, and aligning the TG falling edge to the external
clock’s falling edge. During synchronization, the oscillator
frequency range widens to 120kHz to 650kHz.
For rapid frequency lock-in, the VCO input voltage can be
pre-biased to the desired operating frequency before the
external clock is applied. A resistor connected between
the RFREQ pin and GND can pre-bias the VCO’s input
voltage to the desired potential. Once pre-biased, the PLL
loop only needs to make slight changes to the VCO input
voltage in order to synchronize. The ability to pre-bias the
loop filter allows the PLL to lock-in rapidly.
CLKEN#, OVF AND PWRGD
CLKEN# is an open-drain output used to enable the CPU’s
PLL. Upon power-up, this open-drain pull-down is disabled,
and CLKEN# is pulled high by an external resistor. During
the soft-start ramp, when the switcher output is 45mV
from the VBOOT voltage, the controller completes its soft-
start cycle and 75µs later, CLKEN# pulls low to enable the
processor PLL as shown in Figure 2.
At any instant, if the switcher output voltage rises above
the OVF threshold, the PWRGD pulls low, the regulator
output voltage is actively ramped to 0V and PWRGD
remains latched low until either the power is cycled or
VRON toggles. In the IMVP-6 configuration, the maximum
OVF threshold is 1.7V. In the IMVP-6.5 configuration, the
maximum threshold reduces to 1.55V.
The PWRGD pin is an open-drain output that indicates the
regulator output voltage has stabilized. At start-up, once
the switcher output has settled to its VID potential for more
than 10ms, this open-drain releases and is pulled high by
the external pull-up resistor. It pulls low again if the switcher
output voltage remains outside of the +175mV/–270mV
window around its nominal VID set point for more than
750µs. Once pulled low, the PWRGD state is latched and
the control logic initiates a shutdown sequence. After the
LTC3816
30
3816f
applicaTions inForMaTion
Figure 17. Murata Nonlinear PTC PRF18 Series Typical
Resistance-Temperature Characteristics. Extracted From
Murata PTC PRF18**471QB1RB Data Sheet
TEMPERATURE (°C)
1
RESISTANCE CHANGE (R/R25)
10
100
1000
–20 60 100 140 160
0
20 40 80 1200
3816 F17
BG
BF
BE
BD
BC
BB
BA
AR
AS
output voltage is ramped down, the controller continues
to hold the regulator output and PWRGD low until the
VRON pin toggles or the input supply resets.
During a VID transition, the power good comparators
are masked for 100µs. In deeper sleep mode (25µs after
DPRSLPVR pin transitions high), the power good com-
parators are disabled and PWRGD stays high unless the
switcher output voltage rises above its overvoltage fault
threshold OVF or the controller detects that the regulator
output voltage is 370mV lower than its nominal value.
The LTC3816 PWRGD pin can be configured for wire-OR
operation. Shorting PWRGD to ground externally triggers
a latchoff function. The regulator forces the output to a
zero voltage condition and stays in this state until either
the VRON pin or the input supply resets.
VRTT# AND THERMAL SHUTDOWN
The LTC3816 includes a thermal monitoring circuit that
senses the potential at the RPTC pin. An internal 100µA
pull-up current source connects to an external nonlinear
PTC thermistor through this pin. At room temperature, the
low resistance PTC creates a low voltage at the RPTC pin.
At high temperatures, the PTC resistance increases expo-
nentially. If the resulting RPTC voltage is higher than 0.47V,
it trips the thermal monitor comparator, causing the open-
drain pin VRTT# to pull low signaling an overtemperature
event. The controller continues its normal operation with
no disruption to the output voltage. To reset this thermal
comparator, the voltage at the RPTC pin must drop below
0.1V. To accurately reflect the system temperature, the
nonlinear PTC thermistor should be mounted as close as
thermally possible to the hottest device, e.g., the inductor
or the MOSFET. To prevent the switching noise from af-
fecting the thermal sensing circuit, add a small capacitor
near the RPTC pin.
Figure 17 shows the Murata PTC PRF18 series typical re-
sistance-temperature characteristics. At room temperature,
all parts have about 470Ω nominal resistance. At higher
temperatures, the resistance increases exponentially. An
overtemperature event is detected by the LTC3816 when
the PTC thermistor ’s resistance exceeds 4.7k. By selecting
the appropriate thermistor from the series, this thermal
monitoring threshold can be set anywhere from 65°C to
145°C with 10°C resolution.
The LTC3816 includes a second thermal protection feature.
If the LTC3816 die temperature is higher than 150°C, the
controller pulls down the VRTT# pin. Under this condition
the CPU should initiate its thermal management opera-
tion. To untrip the VRTT# flag, the die temperature must
be dropped below 130°C. If the LTC3816 die temperature
exceeds 165°C, the driver is disabled and the controller is
latched in a thermal shutdown state until the power supply
is cycled or the VRON input toggles.
LTC3816
31
3816f
Figure 18. MOSFET Miller Capacitance
+
–VDS
VIN
3816 F18
VGS
MILLER EFFECT
QIN
A B
CMILLER = (QB – QA)/VDS
VGS
VGS(MIL)
V
+
–
applicaTions inForMaTion
POWER MOSFET AND SCHOTTKY DIODE SELECTION
The LTC3816 requires two external N-channel power
MOSFETs: One for the top (main) switch and one (or more)
for the bottom (synchronous) switch.
The peak-to-peak MOSFET gate drive levels are set by the
5.2V INTVCC supply, requiring the use of logic-level thresh-
old MOSFETs in most applications. Pay close attention to
the BVDSS specification for the MOSFETs as well; many
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs includes the
input capacitance, the on-resistance RDS(ON), the input
voltage and the maximum output current. MOSFET input
capacitance is a combination of several components
but can be derived from the typical gate-charge
curve
included on most data sheets as shown in Figure 18. The
curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the
gate-to-drain capacitances. The flat portion of the curve
is the result of the Miller multiplication effect of the drain-
to-gate capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gate-
to-source capacitance.
The Miller charge (the increase in coulombs on the hori-
zontal axis from A to B while the curve is flat) is specified
for a given VDS drain voltage, but can be adjusted for
different VDS voltages by multiplying the ratio of the ap-
plication VDS to the curve specified VDS values. A way to
estimate the CMILLER term is to take the change in gate
charge from points A and B on a manufacturers data sheet
and divide by the stated VDS voltage specified. CMILLER is
the most important selection criteria for determining the
transition loss term in the top MOSFET but is not directly
specified on MOSFET data sheets. CRSS and COSS are
specified sometimes but definitions of these parameters
are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given
by:
Main Switch Duty Cycle =
Synchronous Swi
V
V
OUT
IN
ttch Duty Cycle = V V
V
IN OUT
IN
–
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
PV
VI R
VI
MAIN OUT
IN LOAD MAX DS ON
IN
L
=
( )
+
( )
+
( )
( )
2
2
1δ( )
OOAD MAX
DR MILLER
INTVCC GS MIL GS
R C
V V V
( )
( )
•
–
2
1 1
( )( )
+
(( )
( )
–
MIL OSC
SYNC IN OUT
IN LOAD MAX
f
PV V
VI
( )
=
( )
22 1+
( )
δRDS ON( )
where δ is the temperature dependency of RDS(ON) and
RDR is the effective top driver resistance (approximately
2.6Ω). VGS(MIL) is the MOSFET VGS at the Miller effect
transition. CMILLER is the calculated capacitance using
the gate-charge curve from the MOSFET data sheet as
described above. The term (1 + δ) is generally given for
a MOSFET in the form of a normalized RDS(ON) versus
temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs.
LTC3816
32
3816f
applicaTions inForMaTion
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at the highest input voltage. The number,
type and on-resistance of all MOSFETs selected take into
account the voltage step-down ratio as well as the actual
position (main or synchronous) in which the MOSFET is
used. A much smaller, lower input capacitance MOSFET
should be used for the top MOSFET in applications where
VIN >> VOUT
. The top MOSFET ’s on-resistance is normally
less important for overall efficiency than its input capaci-
tance at operating frequencies above 300kHz. MOSFET
manufacturers have designed special purpose devices that
provide reasonably low on-resistance with significantly
reduced input capacitance for the main switch in switching
regulators. The synchronous MOSFET losses are greatest
at high input voltages when the top switch duty cycle is
low or during a short circuit when the synchronous switch
is on close to 100% of the period.
The Schottky diode, D, shown in Figure 1 conducts during
the dead-time between the conduction of the two large
power MOSFETs. This prevents the body diode of the bot-
tom MOSFET from turning on, storing charge during the
dead time and requiring a reverse-recovery period which
could cost as much as several percent in efficiency. Due
to the relatively small average current, a 2A to 8A Schottky
is generally acceptable while offering a good compromise
between series resistance and capacitance. Larger diodes
result in additional transition loss due to their larger junc-
tion capacitance.
CIN SELECTION
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
I I V V V
V
RMS MAX LOAD MAX
OUT IN OUT
IN
( ) ( )
–
≈
( )
This equation has a maximum RMS current at VIN = 2VOUT
,
where IRMS(MAX) = ILOAD(MAX)/2. This simple worst-case
condition is commonly used for design because even
significant deviations do not offer much relief. A typical
LTC3816 application operates at low duty cycle, hence,
the maximum input supply ripple current occurs at
VIN = VIN(MIN), and typically IRMS(MAX) < ILOAD(MAX)/2.5.
Note that capacitor manufacturers’ ripple current ratings
are often based on only 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose
a capacitor rated at a higher temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. Sanyo OS-CON SVP,
SVPD series or aluminum electrolytic capacitors from
Panasonic WA series in parallel with a couple of high
performance ceramic capacitors should be used as the
input supply bypass. Ceramic capacitors placed next to
the top MOSFET drain helps to reduce the input supply
voltage ripple.
COUT SELECTION
The output capacitor choice is primarily determined by the
voltage tolerance specifications due to large load current
transients encountered in typical LTC3816 applications.
The capacitance must be sufficient to absorb the change
in inductor current when a high current to low current
transition occurs. The opposite load current transition is
generally determined by the control loop compensation
components, so make sure not to overcompensate and
slow down the response. The minimum capacitance to
assure the inductor ’s energy is adequately absorbed is:
C C L I
V V
BULK CER LOAD
OUT OUT LOAD
+ =
( )
( )
∆
∆
2
2( )
where CBULK is the amount of bulk capacitance and CCER
is the total amount of ceramic capacitance. To minimize
the output voltage overshoot during a load step, set:
∆VOUT(LOAD) = ∆VOUT(AVP)
LTC3816
33
3816f
applicaTions inForMaTion
The resistive component of the bulk capacitor ESR must
be small enough that under a load release, ESR multiplied
by the change in load current must meet the following
criteria:
∆VOUT(LOAD) > ∆ILOAD • RESR
The ceramic capacitors at the regulator output help to
absorb some of the change in the load current and reduce
the ESR voltage step predicted by the above equation. High
performance ceramic capacitors also help to lower the
regulator output voltage perturbation caused by the high
slew rate change in the inductor current flowing through
the bulk capacitor parasitic ESL.
The total amount of output capacitance required is also
restricted by the steady-state output voltage ripple. The
output ripple, ∆VOUT
, in continuous mode is determined
by:
∆ ∆V I R f C C
OUT L ESR OSC BULK CER
≈ + +
( )
1
8 • •
where fOSC = operating frequency and ∆IL = ripple current
in the inductor. The output ripple is highest at maximum
input voltage since ∆IL increases with input voltage. The
first term in the ripple voltage equation relates to the
ripple current into the ESR of the output capacitor, which
dominates the output ripple voltage. The second term
guarantees that the output capacitance does not signifi-
cantly discharge during the operating frequency period
due to ripple current.
Note that the IMVP-6 or IMVP-6.5 application specifies
extremely low output voltage deviations. Therefore, the
output capacitor selection should be carefully considered.
The regulator should be located in close proximity to the
CPU. The bulk capacitor needs to be as close as possible
to the power supply pins of the processor to minimize the
parasitic inductance between the decoupling capacitor and
the load. In addition, multiple high performance ceramic
capacitors are normally placed in the processor socket
cavity to compensate for the PCB parasitic resistance
and inductance.
The Sanyo OS-CON semiconductor electrolyte capacitor
is one possible choice for high performance through-hole
capacitors. In surface mount applications, multiple paral-
lel capacitors are required to meet the ESR or transient
current handling requirements. Aluminum electrolytic
and dry tantalum capacitors are both available in surface
mount configurations. New special polymer surface mount
capacitors offer very low ESR but have much lower ca-
pacitive density per unit volume. In the case of tantalum,
it is critical that the capacitors are surge tested for use in
switching power supplies. Several excellent output capaci-
tor choices are the Sanyo POSCAP TPF, TPL and TPLF, or
the Panasonic SP series. Consult the manufacturer for
other specific recommendations.
INDUCTOR SELECTION
The inductor in a typical LTC3816 circuit is chosen primarily
for its saturation current and inductance value. The induc-
tor DC rated current should be larger than the expected
peak current which is equal to:
I I I
L PEAK LOAD MAX
L MAX
( ) ( )
( )
= + ∆
2
In addition, the selected inductor must be able to withstand
2 × ILOAD(MAX) for a short duration without saturation (see
the Current Limit section).
The inductor value sets the ripple current, which is com-
monly chosen at around 20% to 30% of the anticipated
full load current. Higher inductance reduces ripple cur-
rent, core losses in the inductor, ESR losses in the output
capacitors and output voltage ripple. But, under rapid
loading conditions, higher inductance results in higher
peak-to-peak transient deviations. A lower value inductor
reduces the number of output capacitors and requires a
smaller PCB footprint for the LC filter. Highest efficiency
operation is obtained at low frequency with small ripple
current. However, achieving this requires a large induc-
tor and higher output ripple under transient conditions.
There is a trade-off between component size, efficiency
LTC3816
34
3816f
applicaTions inForMaTion
QBDCOUT
3816 F19
L
QT
VIN VBAT
12V
VOUT
TG
BG
BSOURCE
LTC3816
SW +
Figure 19. Automotive Application Protection
and operating frequency. Given a specified limit for ripple
current, the inductor value can be obtained using the fol-
lowing equation:
LV
f I
V
V
OUT
OSC L MAX
OUT
IN MAX
=
•–
( ) ( )
∆1
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite cores. Ferrite
designs have very low core loss and are thus preferred
at high switching frequencies. Ferrite core materials
saturate hard, which means that inductance collapses
abruptly when the peak design current is exceeded. This
results in an abrupt increase in inductor ripple current and
consequent output voltage ripple. Do not allow the core to
saturate! A variety of inductors designed for high current,
low voltage applications are available from manufacturers
such as Vishay, Sumida, Pulse, Wurth Elektronik, Vitec
and Toko.
AUTOMOTIVE CONSIDERATIONS
Before you connect an LTC3816 converter to an automo-
tive cigarette lighter supply, be advised: you are plugging
into the supply from hell. The main battery line in an
automobile is the source of a number of nasty potential
transients, including load dump, reverse battery and
double battery.
Load dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alterna-
tor can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse battery is
just what it says, while double battery is a consequence of
tow truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 19 is the most straightforward
approach to protect a DC/DC converter from the ravages
of an automotive battery line. The series diode prevents
current from flowing during reverse battery, while the
transient suppressor clamps the input voltage during
load dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the IC has a maximum input voltage of 40V on
the SW pins, most applications will be limited to 30V by
the MOSFET BVDSS.
CHECKING TRANSIENT RESPONSE
For all new LTC3816 PCB circuits, transient tests need to
be performed to verify the proper feedback loop operation.
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to ∆VAVP
. ∆ILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem.
Measuring transient response presents challenges in two
respects: obtaining an accurate measurement and generat-
ing a suitable transient to use to test the circuit. Output
measurements should be taken with a scope probe directly
across the output capacitor. Proper high frequency probing
techniques should be used. In particular, don’t use the 6"
ground lead that comes with the probe! Use an adapter that
fits on the tip of the probe and has a short ground clip to
ensure that inductance in the ground path doesn’t cause
a bigger spike than the transient signal being measured.
LTC3816
35
3816f
PULSE
GENERATOR
0V TO 10V
100Hz, 1% TO 5%
DUTY CYCLE
LTC3816
50Ω
10k
3816 F20
LOCATE CLOSE TO THE OUTPUT
RLOAD
RENESAS RJK0305DPB
OR EQUIVALENT
VOUT
Figure 20. Transient Load Generator PC Board
applicaTions inForMaTion
Conveniently, the typical probe tip ground clip is spaced
just right to span the leads of a typical output capacitor. In
general, it is best to take this measurement with the 20MHz
bandwidth limit on the oscilloscope turned on to limit high
frequency noise. Note that microprocessor manufacturers
typically specify ripple ≤20MHz, as energy above 20MHz
is generally radiated and not conducted and will not affect
the load even if it appears at the output capacitor.
Now that we know how to measure the signal, we need to
have something to measure. The ideal situation is to use
the actual load for the test, and switch it on and off while
watching the output. If this isn’t convenient, a current
step generator is needed. This generator needs to be able
to turn on and off in nanoseconds to simulate a typical
switching logic load, so stray inductance and long clip
leads between the LTC3816 and the transient generator
must be minimized.
Figure 20 shows an example of a simple transient gen-
erator. Be sure to use a noninductive resistor as the load
element—many power resistors use an inductive spiral
pattern and are not suitable for use here. A simple solution
is to take ten 1/4W film resistors and wire them in parallel
to get the desired value. This gives a noninductive resis-
tive load which can dissipate 2.5W continuously or 50W
if pulsed with a 5% duty cycle, enough for most LTC3816
circuits. Solder the MOSFET and the resistor(s) as close
to the output of the LTC3816 circuit as possible and set
up the signal generator to pulse at a 100Hz rate with a 5%
duty cycle. This pulses the LTC3816 with 500µs transients
10ms apart, adequate for viewing the entire transient
recovery time for both positive and negative transitions
while keeping the load resistor cool.
A DESIGN EXAMPLE
As a design example, consider an IMVP-6.5 application
with inductor DCR current sense (see the last page
schematic) and the following requirements: assume VIN
= 12V (nominal), VIN = 24V (maximum), VOUT = 0.75V,
VOUT (minimum) = 0.725V, ILOAD(MAX) = 27A, ILOAD(MIN)
= 1.5A, AVP = –3mV/A, fOSC = 400kHz, VIMON = 1.0V.
For the input and output conditions given above, the
steady-state minimum on-time for this application at
VIN = 24V is approximately:
tV
V f
V
V kH
ON MIN
OUT MIN
IN MAX OSC
( )
( )
( ) •
.
•
= = 0 725
24 400 zz ns=75 5.
This is much longer than the LTC3816 minimum on-time.
To program the 400kHz operation, float the RFREQ pin.
The inductance value is chosen first based on a 20% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage:
LV
f I
V
V
V
OUT
OUT L MAX
OUT
IN MAX
=
=
•–
.
( ) ( )
∆1
0 75
4000 0 2 27 10 75
24 0 33
kHz A
V
VµH
•.• –..
=
A commonly available 0.33µH inductor is chosen. This
results in 5.5A of ripple current. The peak inductor cur-
rent is the maximum DC load current plus one-half the
ripple current, or:
I A A A
L PEAK( ) • . .= + =27 1
25 5 29 75
LTC3816
36
3816f
applicaTions inForMaTion
For this example, a Vishay IHLP-5050CE-01 0.33µH induc-
tor is chosen. According to the inductor data sheet, it has
a maximum DC current rating of 36.5A and a saturation
current of 62A. At room temperature, the typical DCR is
1.3mΩ and the maximum DCR is 1.5mΩ. At 125°C, the
DCR increases to approximately 2.085mΩ. The RIMAX
resistor value can be calculated.
R I IR
I
A
IMAX LIMIT LDCR
IMAX MIN
= +
=
∆
2
29 75 2
( )
. • .0085
96 89
m
µA k
Ω=.
Choose 1% resistor RIMAX = 6.98k to ensure that the
regulator can supply the maximum load current under
the worst-case conditions.
If this large DCR variation is a problem, replace this induc-
tor with another inductor with a smaller DCR variation or
use an NTC temperature compensation circuit as shown in
Figure 21. Please refer to the Temperature Compensated
Active Voltage Positioning with Inductor DCR section.
Note that Figure 21 uses a resistive divider and requires
different component values for optimal temperature
compensation.
To derive the voltage drop across the inductor DCR (typically
1.3mΩ), place a 0.1µF capacitor across the current sense
input pins, ISENP and ISENN. The current sense filter resistor
value RIDCR can be calculated from the equation:
RL
R C
µH
m µF k
IDCR DCR IDCR
= = =
•
.
. • . .
0 33
1 3 0 1 2 538
Ω
Select RIDCR = 2.55k.
For the AVP section (refer to Figure 10), first select a 10k
NTC thermistor. In this example, the Murata NCP18XH103
is chosen. Next, select:
RPAR = RNTC at 25°C = 10k
The RSER resistor value can be obtained from the follow-
ing equation:
R R R
SER PAR PAR
≈
( )
( )
10
3|| – ||R at 0°C R at 75°
NTC NTC CC
( )
( )
°
( )
( )
– ||R R at C
PAR NTC 25
From the NTC data sheet:
RNTC at 0°C = 27.2k
RNTC at 75°C = 1.925k
QB
RS
VOUT
COUT
D
3816 F21
L DCR
INDUCTOR
NTC
QT
IL
VIN
TG
BG
BSOURCE
ISENP
ISENN
IMAX
LTC3816
SW
+
RSER
CIDCR
RIMAX
RPAR
Figure 21. Inductor DCR Current Sense Using
NTC Temperature Compensation
LTC3816
37
3816f
applicaTions inForMaTion
Therefore RSER is calculated to be 13.99k and standard
value RSER = 14k is used. Next, the resistor RAVPDCRN value
is obtained from the AVP slope requirement:
A mV A R R R
RR
AVP
SER PAR NTC
AVPDCRN DCR== = +
( )
⇒
3 / || •
RR k k k
mV A m k
AVPDCRN =+
( )
=
14 10 10
31 3 8 233
||
/• . .Ω
Select the standard value 8.25k. The capacitor value CVDCRN
is given by the following equation:
CL
R R R R
µH
k
VDCRN
SER PAR NTC DCR
=+
( )
=+
|| •
.0 33
14 10kk k m nF
|| • . .
10 1 3 13 36
( )
=
Ω
Use the standard value CVDCRN = 15nF.
To program the IMON voltage, first select the resistor
RPREIMON such that IPREIMON bias current is around 10µA
to 20µA:
RI R
I
R
R
PREIMON
LOAD MAX DCR
PREIMON
NTCNET
AVPDCR
=( ) ••
NN
A m
µA
k k k
k
k
=+
( )
=
27 1 3
15
14 10 10
8 25
5 389
• . •||
.
.
Ω
Select a standard value RPREIMON = 5.1k. Once the resistor
RPREIMON value is chosen, the RIMON resistor value can
be obtained from the following equation:
RV R
I R
R
IMON IMON PREIMON
LOAD MAX DCR
AVPDCR
=
( )
•
• • •
( )
3
NN
NTCNET
R
V k
A m
k
k k
=
( )
+
1 0 5 1
3 27 1 3
8 25
14 10
. • .
• • . •.
||
Ω110
21 03
k
k
( )
=.
Select RIMON = 21k. The value of CIMON is selected to
satisfy the desired IMON time constant:
Ct
R
µs
knF
IMON IMON
IMON
= = =
300
21 14 28.
Select CIMON = 15nF.
The power MOSFETs chosen for this application are the
Renesas RJK0305DPB (top) and 2 × RJK0330DPB (bot-
tom). The upper MOSFET, which is optimized for low
switching losses, has a typical RDS(ON) of 10mΩ at VGS
= 4.5V, a total gate charge of 8nC, and a minimum BVDSS
of 30V. The bottom MOSFET which is optimized for low
on-resistance, has a typical RDS(ON) of 2.8mΩ at VGS =
4.5V, a total gate charge of 27nC, and a minimum BVDSS
of 30V.
From the RJK0305DPB upper MOSFET data sheet, the
Miller capacitance is calculated to be:
CQ
V
nC
VpF
MILLER G
DS
≈ = =
∆
∆
2
12 167
Assuming a top MOSFET junction temperature of 75°C,
δ = 0.25 and the power dissipation in this MOSFET is:
PV
VI R t
VI
MAIN OUT
IN LOAD MAX DS ON
IN
=
( )
+
( )
+
( )
( ) ( )
2
2
1δ
LLOAD MAX
DR MILLER
INTVCC GS MIL G
R C
V V V
( )
( )
•
–
2
1 1
( )( )
+
SS MIL OSC
MAIN
f
PV
VA
( )
..
( )
=
( )
+
0 75
12 27 1 0 25
2
(( )
+
( ) ( )( )
+
10
12 27
22 6 167
1
5 2 3
1
3
2
m
VApF
V V V
Ω
Ω. •
. –
( )
= + ≈
400
0 57 0 266 0 836
kHz
P W W W
MAIN . . .
LTC3816
38
3816f
applicaTions inForMaTion
For the synchronous MOSFETs, assume that the two
bottom MOSFETs share the inductor current equally. The
power dissipation for one MOSFET is:
PV V
VI R
P
SYNC IN OUT
IN LOAD MAX DS ON
SYNC
=
( )
+
( )
–
( ) ( )
21δ
==
( )
+
( )
=
12 0 75
12 13 5 1 0 25 2 8
0 598
2
V V
VA m
W
– . . . .
.
Ω
The total power dissipation of the bottom MOSFETs is
2 × 0.598W = 1.196W.
For this application, the maximum input RMS current
happens when VIN = VIN(MIN) and can be determined from
the formula:
I I V V V
V
RMS MAX LOAD MAX
OUT IN MIN OUT
IN MIN
( ) ( )
( )
( )
–
≈
( )
II A V V V
VA
RMS MAX( )
. – . .≈
( )
≈27 0 75 5 0 75
59 64
The minimum RMS current rating of the input capacitor
must exceed 9.64A. To meet this ripple current requirement
with VIN(MAX) = 24V, select two Sanyo OS-CON 25SVP56
capacitors or higher voltage rating capacitor as the input
supply bulk capacitance. In addition, place a couple of
high performance ceramic capacitors in parallel with the
bulk capacitors.
The output capacitor value is determined by:
C C L I
V V
BULK CER LOAD
OUT OUT LOAD
+ =
( )
( )
∆
∆
2
2( )
Most regulator designs allow a slight transient overshoot
for a short duration. If this is limited to 40mV, we have:
∆V AVP I I
mV
AA
OUT AVP LOAD MAX LOAD MIN( ) ( ) ( )
• –
•
=
( )
=3 27 –– . .
( ) ( )
1 5 76 5A mV
V V V
OUT LOAD OUT AVP OVERSHO
( )
=
= +∆ ∆ ∆ OOT
BULK CER
mV mV mV
C C µH A
= + =
+ =
76 5 40 116 5
0 33 27 1 5
. .
. – . AA
V mV µF
( )
( )( )
=
2
2 0 75 116 5 1228
. .
The ESR of the output capacitor is determined by the load
transient requirement. If the output voltage jump due to
the capacitor ESR is limited to ∆VOUT(AVP):
RV
I
mV
A A m
ESR
OUT AVP
LOAD
< =
( )
=
∆
∆Ω
( )
– . .
75
27 1 5 2 94
The above requirements are easily satisfied by three
Sanyo POSCAP 2TPF330M6 330µF (ESR = 6mΩ) bulk
capacitors in parallel, twenty 10µF and some 1µF high
performance ceramic capacitors in the processor socket
cavity. With three bulk capacitors in parallel, the effective
ESR is 2mΩ, and the maximum steady-state output ripple
voltage is given by:
∆ ∆V I R f C C
A
OUT L ESR OSC BULK CER
≈ + +
( )
=
1
8
5 5
• •
.22 1
8 400 3 330 20 10
11 1 4
mkHz µF µF
mV
Ω+ +
( )
= +
• • • •
. 44 12 44mV mV=.
LTC3816
39
3816f
Figure 22. Sense Resistor and Inductor DCR
Kelvin Current Sensing
applicaTions inForMaTion
As can be seen from the above equation, the biggest portion
of the output ripple comes from the ESR of the capacitor.
This is why low ESR capacitors are so important in low
voltage, high current applications.
PC BOARD LAYOUT CHECKLIST
When laying out the printed circuit board, start with the
power devices. Be sure to orient the power circuitry so
that a clean flow of the power path is achieved. Conductor
widths should be maximized and lengths minimized. After
you are satisfied with the power path, the control circuitry
should be laid out. It is much easier to find routes for the
relatively small traces in the control circuits than it is to
find circuitous routes for high current paths. After the
layout, the following checklist should be used to ensure
proper operation of the LTC3816.
1. Keep the GND and BSOURCE traces separate. The signal
ground consists of the LTC3816 GND pin and the (–)
terminal of VOUT
. The power ground consists of the
BSOURCE pin, the Schottky diode anode, the source
of the bottom side MOSFET, and the (–) terminal of the
input capacitor. Also, try to connect the (–) terminal
of the output capacitor as close as possible to the (–)
terminals of the input capacitor. Place the LDO ceramic
capacitor CINTVCC next to the IC, between INTVCC and
GND. The negative terminals of CIN, COUT and CINTVCC
should be as close as possible to one another.
2. The high di/dt loop formed by the top MOSFET, the
bottom MOSFET and the CIN capacitor should have
short leads and PC trace lengths to minimize high
frequency noise and voltage stress from inductive
ringing.
3. Connect the drain of the topside MOSFET directly to the
(+) plate of CIN, and connect the source of the bottom
side MOSFET directly to the (–) terminal of CIN. This
capacitor provides the AC current to the MOSFETs.
4. The charge pump capacitor, CB, should also be next
to the IC between BOOST and SW.
5. Place the small-signal components away from high
frequency switching nodes (BOOST, SW, TG and
BG).
6. The AITC amplifier external components should be
placed close to the LTC3816. Only the NTC or PTC
thermistor should be placed near the inductor.
7. Are the VCC(SEN) and VSS(SEN), ISENP and ISENN leads
routed together with minimum PC trace spacing? The
filter capacitor between VCC(SEN) and VSS(SEN) and the
filter capacitor between ISENP and ISENN should be as
close as possible to the LTC3816. Ensure accurate
current sensing with Kelvin connections as shown in
Figure 22.
8. To prevent IMON current from affecting the output
voltage kelvin sense accuracy, the IMON resistor and
VSS(SEN) should be connected to the CPU VSS(SEN) pin
using separate PCB traces.
9. Since the IC ground will normally return to the ground
planes on the PCB through an array of vias, be sure
to avoid having any high di/dt power path currents
flowing under the IC.
10. Any external small-signal components that are con-
nected to ground should be located as close as pos-
sible to the IC, with local connections to GND or the
ground plane using vias.
ISENP
LTC3816
INDUCTOR
OUTPUT CAPACITOR
SENSE
RESISTOR
ISENN
CISR
RISR
CISR
RISR
INDUCTOR
3816 F22
OUTPUT CAPACITOR
SW
ISENP
LTC3816
ISENN
LTC3816
40
3816f
Typical applicaTions
An IMVP-6 Converter Using Current Sense Resistor with –5.7mV/A AVP Slope
+
+
GND
INTVCC SGND
LTC3816
ISENN ISENP LFF
1.1V
VRTT# VRTT#
3.3V
IMAX
ITC
33pF
4.75k 3.32k
124Ω
1000pF
CLKEN# CLKEN#
PWRGD
PREIMON
IMON
RPTC
VRON
VSS(SEN)
VCC(SEN)
SERVO
VFB
SS
VID0 VID1 VID2 VID3 VID4 VID5 VID6
VID0 VID1 VID2 VID3 VID4 VID5 VID6
COMP
VRON
DPRSLPVR
CSLEW
DPRSLPVR
4.5V TO 25V VIN
CIN
PTC
0.1µF
1µF
1
8
5
4
2, 3
6, 7 LRSEN
CBULK
330µF
s2
CCER
10µF
s6
VCC(CORE)
ILOAD(MAX)
4A
VSS(CORE)
DB
4.7µF
CBULK: SANYO POSCAP 2TPF330M6
L: VISHAY IHLP2525CZ-06 (1µH, DCR = 8.44mΩ)
PTC: MURATA PRF18BC471QB1RB
RSEN: PANASONIC ERJM1WTF4M0U
fSYNC
INTVCC Si4816BDY
SW
TG
BOOST
VIN
INTVCC
BG
BSOURCE
EXTVCC
RFREQ
MODE/SYNC
56Ω
2.37k
1.9k 1.9k
100Ω
3816 TA02
100Ω
ITCFB
10pF
1500pF
22pF470pF
22pF
1000pF
10k
20k
LOAD CURRENT (A)
0.01
40
EFFICIENCY (%)
50
60
70
80
0.1 1
3816 TA02b
30
20
10
0
90
100 VCC(CORE) = 1V
fOSC = 400kHz
VEXTVCC = 0V
CONTINUOUS MODE
PULSE-SKIPPING MODE
VIN = 5V
VIN = 12V
VCC(CORE)
20mV/DIV
ILOAD
2A/DIV
20µs/DIV 3816 TA02b
Efficiency Transient Waveform
LTC3816
41
3816f
Typical applicaTions
A Dual Channel IMVP-6 Converter Using Sense Resistor with –2.1mV/A AVP Slope
2.43k
ISENN
ISENP
LFF
VRTT# VRTT#
3.3V
IMAX 1000pF 1000pF
CCER
0.1µF 0.1µF
5V 5V
DBDB
PTC
– +
PTC
L L
RSENSE RSENSE
CBULK
VCC_CORE
ILOAD(MAX) = 54A
CBULK: 4 s SANYO 2TPF330M6 (330µF)
CCER: 32 s 10µF + 2 s 1µF
CIN: 3 s SANYO OS-CON 35SVPD47M + 2 s 10µF
DB: CMDSH-4E
L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)
PTC: MURATA PRF18BC471QB1RB
QT: RENESAS RJK0305DPB
QB: 2 s RENESAS RJK0330DPB
RSENSE: PANASONIC ERJM1WTF1M0U (1mΩ)
CVIN
VIN
4.5V TO 24V
4.7µF 4.7µF
400kHz
SQUARE WAVE
QTQT
QBQB
3k
511Ω 511Ω
3k
56Ω
100Ω100Ω
1.1V 3.3V
22pF
ITCFB
ITC
PREIMON
CLKEN# CLKEN#
SW
TG
BOOST
VIN
EXTVCC
INTVCC
MODE/SYNC
BSOURCE
VID6
VID5
VID4
RFREQ
BG
1.9k
1.9k
PWRGD
LT3816
GND GND
3816 TA04
PWRGD
+
+
10pF
10k
22pF 6800pF
22pF470pF
12k
10.2k
1000pF
RPTC
VRON
VRON
INTVCC IMON
CSLEW
VID0
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VID1
VID2
VID3
DPRSLPVR
SS
SERVO
VFB
COMP
VSS(SEN)
VCC(SEN)
ISENN
ISENP
LFF
VRTT#
IMAX
CLKEN#
SW
TG
BOOST
VIN
EXTVCC
INTVCC
MODE/SYNC
BSOURCE
VID6
VID5
VID4
RFREQ
BG
PWRGD
ITCFB
ITC
PREIMON
RPTC
VRON
IMON
CSLEW
VID0
VID1
VID2
VID3
DPRSLPVR
SS
22pF
12k
10k
22pF
10.2k2.43k 1000pF
INTVCC
10pF
22pF
6800pF
470pF
SERVO
VFB
COMP
VSS(SEN)
VCC(SEN)
LT3816
GND
LTC3816
42
3816f
package DescripTion
FE Package
38-Lead Plastic eTSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev B)
Exposed Pad Variation AA
4.75
(.187) REF
FE38 (AA) eTSSOP REV B 0510
0.09 – 0.20
(.0035 – .0079)
0o – 8o
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
LTC3816
43
3816f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
5.00 p 0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF
5.15 ± 0.10
7.00 p 0.10
0.75 p 0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 p 0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ± 0.10
0.40 p0.10
0.70 p 0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ± 0.05
4.10 p 0.05
5.50 p 0.05 5.15 ± 0.05
6.10 p 0.05
7.50 p 0.05
0.25 p 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
LTC3816
44
3816f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2010
LT 0710 • PRINTED IN USA
relaTeD parTs
Typical applicaTion
An IMVP-6.5 Converter Using Temperature Compensated Inductor DCR Sensing with –3mV/A AVP Slope
ISENN
ISENP
LFF
VRTT# VRTT# 1.1V
3.3V
IMAX 0.1µF
CCER VCC(CORE)
ILOAD(MAX) = 27A
0.1µF
5V
DB
L
NTC
PTC
CBULK
CBULK: 3 s SANYO 2TPF330M6 (330µF)
CCER: 20 s 10µF + 2 s 1µF
CIN: 2 s SANYO OS-CON 35SVPD47M + 2 s 10µF
DB: CMDSH-4E
L: IHLP-5050CE-01 (0.33µH, DCR = 1.3mΩ)
NTC: MURATA NCP18XH103
PTC: MURATA PRF18BC471QB1RB
QB: 2 s RENESAS RJK0330DPB
QT: RENESAS RJK0305DPB
100Ω
100Ω
CVIN
VIN
4.5V TO 24V
4.7µF
QT
QB
6.98k
2.55k
56Ω
8.25k
14k
21k
IMON
15nF
15nF
ITCFB
ITC
PREIMON
CLKEN# CLKEN#
SW
TG
BOOST
VIN
EXTVCC
INTVCC
MODE/SYNC
BSOURCE
VID6
VID5
VID4
RFREQ
BG
1.9k
PWRGD
LT3816
GND
PWRGD 1.9k
+
+
5.1k
1000pF
10pF
10k
22pF 2.2nF
22pF470pF
12k
10k
RPTC
VRON
VRON
IMON
CSLEW
VID0
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID1
VID2
VID3
DPRSLPVR
SS
SERVO
VFB
COMP
VSS(SEN)
VCC(SEN)
PART NUMBER DESCRIPTION COMMENTS
LTC3732 3-Phase, 5-Bit VID, 600kHz Synchronous Buck Switching Regulator Controller VRM9.0 and VRM9.1, VID = 1.1V to 1.85V
LTC3733 3-Phase, 5-Bit VID, 600kHz Synchronous Buck Switching Regulator Controller AMD Opteron (VID = 0.8V to 1.55V)
LTC3734 Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs 6-Bit IMVP-4 VID: 0.7V ≤ VOUT ≤ 1.708V, ILOAD ≤ 25A,
Lossless Voltage Positioning
LTC3735 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs 6-Bit IMVP-IV, VID Code: VOUT = 0.7V to 1.708V
LTC3738 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning VID = 1.1V to 1.85V
LTC3819 2-Phase, High Efficiency, Step-Down Controller for AMD CPUs 4V ≤ VIN ≤ 36V, VID =1.025V to 1.4125V
LTC3850 Dual 2-Phase Synchronous Controller Dual 180° Phase Controllers, 4V ≤ VIN ≤ 28V,
97% Duty Cycle
LTC3851A No RSENSE™ Wide Input Range Step-Down Controller 4V ≤ VIN ≤ 38V, Very Low Dropout with Tracking
LTC3853 Triple Output, Multiphase Synchronous Step-Down Controller Triple Phase Version of LTC3850 in a 40-Lead
6mm × 6mm QFN Package
