CY7C43682AV-15AI - Cypress Semiconductor Corp.

CY7C43642AV

CY7C43662AV/CY7C43682AV

3.3V 1K/4K/16K x36 x2 Bidirecti onal

Synchronous FIFO

PRELIMINARY

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-06020 Rev. ** Revised March 26, 2001

3662AV

Features

• 3.3V high-speed, low-power, bidirectional, First-In First-

Out (FIFO) memories

• 1K x36 x2 (CY7C43642AV)

• 4K x36 x2 (CY7C43662AV)

• 16K x36 x2 (CY7C43682AV)

• 0.25-micron CMOS for optimum speed/power

• High-speed 133-MHz operation (7.5-ns read/write cycle

times)

• Low power

—ICC = 60 mA

—ISB = 10 mA

• Fully asynchronous and simultaneous read and write

operation permitted

• Mailbox bypass register for each FIFO

• Paralle l Programm able Alm ost Full and Almos t Empty

flags

• Retransmit function

• Standard or FWFT user selectable mode

• 120-pin TQFP packaging

• Easily expandable in width and depth

Logic Block Diagram

Port A

Control

Logic Port B

Control

Logic

Mail1

Input

Write

Pointer Read

Pointer

Status

Flag Logic

Programmable

Flag Offset Timing

Mode

Status

Flag Logic

Write

Pointer Read

Pointer

1K/4K/16K

x36

Dual Ported

Memory

1K/4K/16K

x36

Dual Ported

Memory

Mail2

Output

Input

FIFO1,

Mail1

Reset

Logic

FIFO2,

Mail2

Reset

Logic

CLKA

CSA

W/RA

ENA

MBA

RT2

MRST1

FFA/IRA

AFA

FS0

FS1

A0–35

EFA/ORA

AEA

MBF2

MRST2

FFB/IRB

AFB

FWFT/STAN

B0–35

CLKB

CSB

W/RB

ENB

MBB

RT1

EFB/ORB

AEB

MBF1

Output

Registers

(FIFO1)

(FIFo2)

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 2 of 31

CY7C43642AV

CY7C43662AV

CY7C43682AV

TQFP

Top Vi e w

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

MBF2

GND

FS0

MRST1

MBA

AEA

AFA

EFA/ORA

FFA/IRA

CSA

W/RA

ENA

CLKA

GND

W/RB

CLKB

ENB

CSB

GND

FFB/IRB

EFB/ORB

AFB

AEB

MBF1

MBB

MRST2

FS1

B26

GND

B24

B25

RT1

B27

B28

B29

B30

B31

GND

B32

B33

B34

B35

B14

GND

B12

B13

B15

VCC

B16

B17

GND

B18

B19

B20

B21

B22

B23

GND

A27

A23

A24

A25

A26

A28

GND

A30

A31

VCC

A32

A33

A34

A35

A14

A12

RT2

A13

A15

A16

A17

GND

A18

A19

A20

A21

VCC

A22

FWFT/STAN

A29

Pin Configuration

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 3 of 31

Functional Description

The CY7C436X2AV is a monolithic, high-speed, low-power,

CMOS Bidirectional Synchronous FIFO memory which sup-

ports clock frequencies up to 133 MHz and has read access

times as fast as 6 ns. Two independent 1K/4K/16K x 36 dual-

port SRAM FIFOs on board each chip buffer data in opposite

directions.

The CY7C436X2AV is a synchronous (clocked) FIFO, mean-

ing eac h port emp loys a sy nchronous interface . All data trans-

fers thro ugh a port a re gated to the LOW -to-HIGH tr ansition of

a port clock by enable signals. The clocks for each port are

independent of one another and can be asynchronous or co-

incident. The enables for each port are arranged to provide a

simple bidirectional interface between microprocessors and/or

buses w ith sy nc hron ous cont rol.

Comm unicatio n betwee n each port may bypa ss the FIF Os via

two mailbox registers. The mailbox registers’ width matches

the selected Port B bus width. Each mailbox register h as a flag

(MBF1 and MBF2) to signal when new mail has been stored.

Master Reset initializes the read and write pointers to the first

location of the memory array, and selects parallel flag pro-

gramming, or one of the three possible default flag offset set-

tings, 8, 16, or 64. Each FIFO has its own indep endent Master

Reset pin, MRST1 and MRST 2.

The CY7C436X2AV have two modes of operation: In the CY

Standard M ode , the first word w ritt en to an em pty FIFO is de-

posited in to th e m em ory array. A read o per atio n i s re qui red to

access that word (along with all other words residing in mem-

ory). In the First-Word Fall-Through Mode (FWFT), the first

word (36-b it wide) written to an empty FIFO app ears autom at-

ically on the outputs, no read operation required (nevertheless,

accessing subsequent words does necessitate a formal read

request). The state of the FWFT/ STA N pi n duri ng FI FO ope r-

ation determines the mode in use.

Each FIFO has a combined Empty/Output Ready flag (EFA/

ORA and EFB/ORB) and a combined Full/Input Ready flag

(FFA/IRA and FFB/IRB). The EF and FF functions are selected

in the CY Standard Mode. EF indicates whether the memory

is full or not . FF in dic ate s wheth er the FIFO i s full . T he IR an d

OR functions are selected in the First- Word Fall-Through

Mode. IR indicates whether or not the FIFO has available

memory locations. OR shows whether the FIFO has data avail-

able for reading or not. It marks the presence of valid data on

the outputs.

Each FIFO has a programmabl e Almost Emp ty flag (AEA and

AEB) and a programmable Almost Full flag (AFA and AFB).

AEA and AEB indicate when a selec ted number of words writ-

ten to FIFO memory achieve a predetermined “almost empty

state.” AFA and AFB indicate when a selected number of

words writt en to the memory ach ieve a predetermine d “almost

full stat e.”[1]

FFA/IRA, FFB/IRB, AF A, and AFB are synchronized to the port

clock tha t writes data into its array . EF A /ORA, EFB/ORB, AEA,

and AEB are synchronized to the port clock that reads data

from its arra y. Prog rammabl e offset for AEA, AEB, AFA, and

AFB are loaded in parallel using Port A. Three default offset

settings are also provided. The AEA and AEB threshold can

be set at 8, 16, or 64 locations from the empty boundary and

AFA and AFB threshold can be set at 8, 16, or 64 locations

from the full boundary. All these choices are made using the

FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider

data paths.

The CY7C436X2AV FIFOs are characterized for operation

from 0°C to 70°C commercial, and from –40°C to 8 5°C in dus -

trial. In put ESD protection i s gre ater th an 20 01V, and l atc h-u p

is prevented by the use of guard rings.

Selection Guide

CY7C43642/

62/82AV

−7

CY7C43642/

62/82AV

−10

CY7C43642/

62/82AV

−15

Maximu m Frequency (MHz) 133 100 66.7

Maximum Access Time (ns) 6 8 10

Minimum Cycle Time (ns) 7.5 10 15

Minimum Data or Enable Set-Up (ns) 345

Minimum Data or Enable Hold (ns) 000

Maximum Flag Delay (ns) 6 8 10

Active Power Supply

Current (ICC1) (mA) Commercial 60 60 60

Industrial 60

CY7C43642AV CY7C43662AV CY7C43682AV

Density 1K x 36 x2 4K x 36 x2 16K x 36 x2

Package 120 TQFP 120 TQFP 120 TQFP

Note:

1. When FIFO is operated at the almost empty/full boundary , there may be an uncertainty of up to 2 clock cycles for flag deassertion, but the flag will always be

asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to “Designing

with CY7C436xx Synchronous FIFOs” application note for more details on flag uncertainties.

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 4 of 31

Pin Definitions

Signal Name Description I/O Function

A0–35 Port A Data I/O 36-bit bidirectional data port for side A.

AEA Port A Almost

Empty Flag O Program mable Almo st Empty fla g synchro nized to CLKA. It i s LOW when the number

of words in FIFO2 is less than or equal to the value in the Almost Empty A offset register ,

X2.[1]

AEB Port B Almost

Empty Flag O Program mable Almo st Empty fla g synchro nized to CLKB. It i s LOW when the number

of words in FIFO1 is less than or equal to the value in the Almost Empty B offset register ,

X1.[1].

AFA Port A Almost

Full Flag O Programmable Almost Ful l flag s ynchr onize d to CLKA. It is LO W when the numbe r of

empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset

AFB Port B Almost

Full Flag O Programmable Almost Ful l flag s ynchr onize d to CLKB. It is LO W when the numbe r of

empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset

B0–35 Port B Data I/O 36-bit bidirectional data port for side B.

FWFT/STAN First-Word Fall-

Through / CY

Standard Select

I During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects

First -W ord Fall -Through mode . Once the tim ing mode ha s been sel ected, the le vel on

FWFT/STAN must be static throughout device operation.

CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can

be asynchronous or coincident to CLKB. FFA/IRA, EFA/O RA, AFA, and AEA are all

synchronized to the LOW-to-HIGH transition of CLKA.

CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can

be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all

synchronized to the LOW-to-HIGH transition of CLKB.

CSA Port A Chip

Select ICSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on

Port A. The A0–35 outpu ts are in the hig h-im pe da nce state when CSA is HIGH.

CSB Port B Chip

Select ICSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on

Port B. The B0–35 outpu ts are in the hig h-im pe da nce state when CSB is HIGH.

EFA/ORA Port A Empty/

Output Ready

Flag

O This is a dual-function pin. In the CY Standard Mode, the EF A function is selected. EF A

indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA

function is selected. ORA indicates the presence of valid data on A0–35 out puts avai l-

able for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.

EFB/ORB Port B Empty/

Output Ready

Flag

O This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB

indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB

function is selected. ORB indicates the presence of valid data on B0–35 out puts avai l-

able for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.

ENA Port A Enable I ENA must be HIGH to enable a LO W-to-H IGH transiti on of CLKA to read or w rite data

on Port A.

ENB Port B Enable I ENB must be HIGH to enable a LO W-to-H IGH transiti on of CLKB to read or w rite data

on Port B.

FFA/IRA Port A Full/Input

Ready Flag O This is a du al-function pin . In the CY Standard Mode, the FF A function is selected. FF A

indicates whether or not the F IFO1 memory is full. In the FWFT mode, the IRA function

is selected. IRA indicates whether or not there is space available for writing to the FIFO1

memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.

FFB/IRB Port B Full/Input

Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB

indicates whether or not the F IFO2 memory is full. In the FWFT mode, the IRB function

is selected. IRB indicates whether or not there is space available for writing to the FIFO2

memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 5 of 31

FS1 Flag Offset

Select 1 I The LOW-to-HIGH transition of a FIFO’s reset input latches the values of FS0 and FS1.

If either FS0 or FS1 is HIGH when a reset input goes HIGH, one of the three preset

values (8, 16, or 64) is selected as the offset for the FIFO’s Almost Full and Almost

Empty fla gs. If both FIFOs reset simultaneously and both FS0 and FS1 are LOW when

MRST1 and MRST2 go HIGH, the first four writes program the Almost Empty and

Almost Full offsets for both FIFOs.

FS0 Flag Offset

Select 0 I

MBA Port A Mailbox

Select I A HIGH level on MBA ch ooses a mail box regis ter for a Port A re ad or wr ite ope ration.

When the A0–35 outputs are activ e, a H IGH lev el on M BA s ele cts da ta fro m t he M ai l2

MBB Port B Mailbox

Select I A HIGH level on MBB ch ooses a mail box regis ter for a Port B re ad or wr ite ope ration.

When the B0–35 outputs are activ e, a H IGH lev el on M BB s ele cts da ta fro m t he M ai l1

MBF1 Mail1 Register

Flag OMBF1 is set LOW by a LOW -to-HIGH t rans iti on of CL KA that writ es data to the Ma il1

HIGH by a LOW -to -HIGH transi tion o f CL KB when a Port B read is s elect ed and MBB

is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.

MBF2 Mail2 Register

Flag OMBF2 is set LOW by a LOW -to-HIGH t rans iti on of CL KB that writ es data to the Ma il2

HIGH by a LOW -to -HIGH transi tion o f CL KA when a Port A read is s elect ed and MBA

is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

MRST1 FIFO1 Master

Reset I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes. A LOW pulse on MRST1

selects the programming method (serial or parallel) and one of three programmable

flag default offsets for FIFO1. Four LOW-to-HIGH transitions of CLKA and four LOW-

to-HIGH transitions of CLKB must occur while MRST1 is LOW.

MRST2 FIFO2 Master

Reset I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

memory and sets the Port A output register to all zeroes. A LOW pulse on MRST2

selects one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH

transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while

MRST2 is LO W.

RT1 Retransmit

FIFO1 I A LOW strobe on this pin will retransmit the data on FIFO1. This is achieved by bringing

the read pointer back to location zero. The user will still need to perform read operations

to retransmit the data. Retransmit function applies to CY standard mode only.

RT2 Retransmit

FIFO2 I A LOW strobe on this pin will retransmit the data on FIFO2. This is achieved by bringing

the read pointer back to location zero. The user will still need to perform read operations

to retransmit the data. Retransmit function applies to CY standard mode only.

W/RA Port A Write/

Read Select I A HIGH se le cts a w ri te o pe r ati on a nd a LO W se lec ts a re ad o pe r atio n o n Po rt A fo r a

LOW -to-HIG H tra nsiti on o f CLKA. The A0–35 outputs a r e i n th e h igh -im ped an ce state

when W/RA is HIGH.

W/RB Port B Write/

Read Select I A LOW sel ec ts a writ e op era tio n an d a H IG H se lec ts a re ad operatio n o n Po rt B fo r a

LOW -to-HIG H tra nsiti on o f CLKB. The B0–35 outputs a r e i n th e h igh -im ped an ce state

when W/RB is LOW.

Pin Definitions (continued)

Signal Name Description I/O Function

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 6 of 31

Maximum Ratings[2]

(Above w hi ch the usef ul l ife m ay be im pai red. For us er g uid e-

lines, not tes ted .)

Storage Temperature ......................................∠65°C to +1 50°C

Ambient Temperature with

Power Applied...................................................∠55°C to +125°C

Supply Vo ltage to Ground Potential................∠0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z Stat e[3] .........................................∠0.5V to VCC+0.5V

DC Input Voltage[3]......................................∠0.5V to VCC+0.5V

Output Current into Outputs (LOW).............................20 mA

Static Discharge Voltage...........................................>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current......................................................>200mA

Operating Range

Range Ambient

Temperature VCC[4]

Commercial 0°C to +70°C 3.3V ± 10%

Industrial ∠40°C to +85°C 3.3V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions

CY7C43642/62/82AV

UnitMin. Max.

VOH Output HIGH Voltage VCC = 3.0 V,

IOH = ∠2.0 mA 2.4 V

VOL Output LOW Voltage VCC = 3.0 V,

IOL = 8.0 mA 0.5 V

VIH Input HIGH Voltage 2.0 VCC V

VIL Input LOW Voltage ∠0.5 0.8 V

IIX Input Leakage Current VCC = Max. ∠10 +10 µA

IOZL

IOZH Output OFF, High Z

Current VSS < VO< VCC ∠10 +10 µA

ICC1[5] Active Power Supply

Current Com’l60 mA

Ind 60 mA

ISB[6] Average Standby

Current Com’l10 mA

Ind 10 mA

Capacitance[7]

Parameter Description Test Conditions Max. Unit

CIN Input Capa cit anc e TA = 25°C, f = 1 MHz,

VCC = 3.3V 4pF

COUT Output Capacitance 8pF

Notes:

2. Stresses beyond those listed under “Abso l ute Ma x imu m R a tin g s ” may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

3. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

4. Operating VCC Rang e for -7 speed is 3.3V ± 5%.

5. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs

are unloaded.

6. All inputs = VCC – 0.2V, except CLKA and CLKB (which are at frequency = 0 MHz). All outputs are unloaded.

7. Tested initially and after any design or process changes that may affect these parameters

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 7 of 31

AC Test Loads and Waveforms (-10 & -15)

AC Test Loads and Waveforms (-7)

Switching Characteristics Over the Operating Range

Parameter Description

CY7C43642/

62/82AV

-7

CY7C43642/

62/82AV

-10

CY7C43642/

62/82AV

-15

UnitMin. Max. Min. Max. Min. Max.

fSClock Frequency, CLKA or CLKB 133 100 67 MHz

tCLK Clock Cycle Time, CLKA or CLKB 7.5 10 15 ns

tCLKH Pulse Duration, CLKA or CLKB HIGH 3.5 4 6 ns

tCLKL Pulse Duration, CLKA or CLKB LOW 3.5 4 6 ns

tDS Set-Up Time, A0–35 before CLKA↑ and B0–35 before

CLKB↑3 4 5 ns

tENS Set-Up T ime, CSA, W/RA, ENA, and MBA before CLKA↑;

CSB, W/RB, ENB, and MBB before CLKB↑3 4 5 ns

tRSTS Set-Up Ti me, MRST1, MRST2, RT 1 or RT2 LOW before

CLKA↑ or CLKB↑[8] 2.5 4 5 ns

tFSS Set-Up Time, FS0 and FS1 before MRST1 and MRST2

HIGH 5 7 7.5 ns

tFWS Set-Up Time, FWFT before CLKA↑0 0 0 ns

tDH Hold Time, A0–35 after CLKA↑ and B0–35 after CLKB↑0 0 0 ns

tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑;

CSB, W/RB, ENB, and MBB after CLKB↑0 0 0 ns

tRSTH Hold Time, MRST1, MRST2, RT1 or RT2 LOW after

CLKA↑ or CLKB↑[8] 1 2 2 ns

tFSH Hol d Time, FS 0 and FS1 a fter MRST1 and MRST2 HIGH 1 1 2 ns

tSPH Hold Time, FS1 HIGH after MRST1 and MRST2 HIGH 1 1 2 ns

tSKEW1[10] Skew Time between CLKA↑ and CLKB↑ for EFA/ORA,

EFB/ORB, FFA/IRA, and FFB/IRB 5 5 7.5 ns

Notes:

8. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

9. CL = 5 pF for tDIS.

10. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB

cycle.

3.0V

3.3V

OUTPUT

R2=680

Ω

=30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤

3ns

≤

3ns

ALL INPUT PULSES

R1=330

Ω

[9]

3.0V

GND

90%

10%

90%

10%

≤3ns ≤3ns

ALL INPUT PULSES

I/O

50Ω

Z0=50Ω

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 8 of 31

tSKEW2[10] Skew Time between CLKA↑ and CLKB↑ for AEA, AEB,

AFA, AFB 7 8 12 ns

tAAccess Time, CLKA↑ to A0–35 and CL KB↑ to B0–35 1618310 ns

tWFF Propagation Del ay Time, CLKA↑ to FF A/IRA an d CLKB↑

to FFB/IRB 1618210 ns

tREF Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑

to EFB/ORB 1618210 ns

tPAE Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to

AEB 1618110 ns

tPAF Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to

AFB 1618110 ns

tPMF Propagatio n Delay T i me, CLKA↑ to M BF1 LOW or MBF2

HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH 0608012 ns

tPMR Propagatio n Del ay Time, CLKA↑ to B0–35[11] a nd C L KB↑

to A0–35[12] 1 7 2 11 312 ns

tMDV Propaga tion Delay T im e, MBA to A0–35 Valid and M BB to

B0–35 Valid 1629311 ns

tRSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB

LOW, AFA HIGH, FFA/IRA LOW , EFB /ORB LOW and

MBF1 HIG H and MRS2 or PRS2 LOW to AEA LOW , AFB

HIGH, FFB/IRB LOW, EFA /ORA LOW and MBF2 HIGH

1 6 1 10 115 ns

tEN Enable Time, CSA or W/RA LOW to A0–35 Active and CSB

LOW and W/RB HIGH to B0–35 Active 1628210 ns

tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High-

Impedanc e and CSB HIGH or W/RB LOW to B0–35 at

High-Impedance

151618ns

tRTR Retransmit Recovery Time 90 90 90 ns

Notes:

11. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.

12. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.

Switching Characteristics Over the Operating Range (continued)

Parameter Description

CY7C43642/

62/82AV

-7

CY7C43642/

62/82AV

-10

CY7C43642/

62/82AV

-15

UnitMin. Max. Min. Max. Min. Max.

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 9 of 31

Switching Waveforms

Note:

13. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.

FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight

CLKA

CLKB

MRST1

FWFT/STAN

FS1, FS0

FFA/IRA

EFB/ORB

AEB

AFA

MBF1

[13]

tRSF

tWFF

tFSS tFSH

tRSTH

tRSTS

tFWS

tRSF

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 10 of 31

Notes:

14. CSA=LOW , W/RA=HIGH, MBA=LOW . It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in paralle l

when FFA/IRA is HIGH.

15. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising

edge of CLKA and rising edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one cycle later than shown.

16. Written to FIFO1.

17. If W/RA switches from read to write before the assertion of CSA, tENS=tDIS+tENS.

Switching Waveforms (continued)

Programming of the Almo st-Fu ll Flag an d A lm o st-Em p ty Flag O ffset Va lue s after Re set

(CY Standard and FWFT Modes)

tWFF

tFSS

tDS

tFSH

tENS tENH

tDH

tSKEW1[15]

AFA Offset (Y1) AFB Offset (Y2) First Word to FIFO1

CLKA

MRST1, MRST2

FS1, FS0

FFA/IRA

ENA

A0−35

CLKB

FFB/IRB

[14]

AEB Offset (X1) AEA Offset (X2)

tWFF

tCLKH tCLKL

tENS tENH

tDS tDH

tENS tENH tENS tENH

HIGH

W1[16] W2[16]

tCLK

CLKA

FFA/IRA

CSA

W/RA

MBA

ENA

A0–35

Port A Write Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

[17]

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 11 of 31

Notes:

18. Written to FIFO2.

19. Read from FIFO1.

20. If W /RB switches from read to write before the assertion of CSB, tENS=tDIS+tENS.

Switching Waveforms (continued)

tCLKH tCLKL

tENS tENH

tDS tDH

tENS tENH tENS tENH

HIGH

W1[18] W2[18]

tCLK

Port B Write Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

CLKB

FFB/IRB

CSB

W/RB

MBB

ENB

B0−35

[20]

tCLKH tCLKL

tENS

tDIS

tENS tEN

tCLK

tDIS

tENH

tENS tENH

tEN

tMDV

W1[19] W2[19]

W3[19]

Previous Dat a

No Operation

CLKB

EFB/ORB

CSB

W/RB

MBB

ENB

B0–35

(FWFT Mode)

Port B Read Cycle Timing for FIFO1 (CY Standard and FWFT Modes)

HIGH

B0–35

(Standard Mode)

[20]

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 12 of 31

Note:

21. Read from FIFO2.

Switching Waveforms (continued)

tCLKH tCLKL

tENS

tDIS

tENS tENH

tCLK

tDIS

tENH

tENS tENH

tEN

tMDV

W1[21] W2[21]

W3[21

Previous D ata

No Operation

CLKA

EFA/ORA

CSA

W/RA

MBA

ENA

A0−35

(FWFT Mode)

Port A Read Cycle Timing for FIFO2 (CY Standard and FWFT Modes)

HIGH

A0–35

(Standard Mode)

[17]

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 13 of 31

Note:

22. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO 1 ou tput

register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and

load of the first word to the output register may occur one CLKB cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENS

tCLK

tENH

tENS

tENH

tDS

LOW

tDH

HIGH

FIFO1 Empty

LOW

HIGH

LOW

Old Data in FIFO1 Output Register W1

tENS tENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[22]

CLKA

CSA

W/RA

MBA

ENA

FFA/IRA

A0–35

CLKB

EFB/ORB

CSB

W/RB

MBB

ENB

B0–35

ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 14 of 31

Note:

23. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENS

tENH

tENS

tENH

tDS

LOW

tDH

HIGH

FIFO1 Empty

LOW

HIGH

LOW

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[23]

CLKA

CSA

W/RA

MBA

ENA

FFA/IRA

A0–35

CLKB

EFB/ORB

CSB

W/RB

MBB

ENB

B0–35

EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (CY Standard Mode)[23]

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 15 of 31

Notes:

24. tSKEW1 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.

25. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO 2 ou tput

register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and

load of the first word to the output register may occur one CLKA cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENS

tENH

tENS

tENH

LOW

tDH

LOW

HIGH

FIFO2 Empty

LOW

Old Data in FIFO2 Output Register W1

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[25]

tCLK

tDS

CLKB

CSB

W/RB

MBB

ENB

FFB/IRB

B0–35

CLKA

EFA/ORA

CSA

W/RA

MBA

ENA

A0–35

ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)[24]

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 16 of 31

Note:

26. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

Switching Waveforms (continued)

EFA Flag Timing and First Data Read when FIFO2 is Empty (CY Standard Mode)

tCLKH tCLKL

tENS

tENH

tENS

tENH

tDS

LOW

tDH

LOW

HIGH

FIFO2 Empty

LOW

tENStENH

tREF tREF

tCLKH tCLKL

tCLK

tSKEW1[26]

CLKB

CSB

W/RB

MBB

ENB

FFB/IRB

B0–35

CLKA

EFA/OFA

CSA

W/RA

MBA

ENA

A0–35

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 17 of 31

Note:

27. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time bet ween the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO1 Full

LOW

HIGH

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[27]

tDH

tDS

tENH

tENS

Previous Word in FIFO1 Output Register Next Wo rd From FIFO1

To FIFO1

CLKB

CSB

W/RB

MBB

ENB

EFB/ORB

B0–35

CLKA

FFA/IRA

CSA

W/RA

MBA

ENA

A0–35

IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)

LOW

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 18 of 31

Note:

28. tSKEW1 i s the minimum time between a rising CLKB edge and a rising CLKA edge for FF A to transition HIGH in the next CLKA cycle. If the time between the

rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FFA HIGH may occur one CLKA cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENStENH

LOW

HIGH

FIFO1 Full

LOW

HIGH

tENStENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[28]

tDH

tDS

tENH

tENS

Previous Word in FIFO1 Output Register Next Word Fro m FIF O 1

CLKB

CSB

W/RB

MBB

ENB

EFB/ORB

B0–35

CLKA

FFA/IRA

CSA

W/RA

MBA

ENA

A0−35

FFA Flag Timing and First Available Write when FIFO1 is Full (CY Standard Mode)

LOW

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 19 of 31

Note:

29. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time bet ween the

rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of IRB HIGH may occur one CLKB cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENS tENH

LOW

HIGH

FIFO2 Full

LOW

tENS tENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[29]

tDH

tDS

tENH

tENS

Previous Word in FIFO2 Output Register Next Word From FIFO2

To FIFO2

LOW

CLKA

CSA

W/RA

MBA

ENA

EFA/ORA

A0–35

CLKB

FFB/IRB

CSB

W/RB

MBB

ENB

B0–35

IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 20 of 31

Note:

30. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of FF B HIGH may occur one CLKB cycle later than shown.

Switching Waveforms (continued)

tCLKH tCLKL

tENS tENH

LOW

HIGH

FIFO2 Full

LOW

tENS tENH

tWFF tWFF

tCLKH tCLKL

tCLK

tSKEW1[30]

tDH

tDS

tENH

tENS

Previous Word in FIFO2 Output Register Next Word From FIFO2

To FI FO2

LOW

CLKA

CSA

W/RA

MBA

ENA

EFA/ORA

A0–35

CLKB

FFB/IRB

CSB

W/RB

MBB

ENB

B0–35

FFB Flag Timing and First Available Write when FIFO2 is Full (CY Standard Mode)

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 21 of 31

Notes:

31. FIFO1 Port A Write (CSA = LOW , W/RA = HIGH, MBA = LOW), FIFO1Port B read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output

32. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

33. FIFO2 Port B Write (CSB = LOW, W/ R B = LOW, MBB = LOW), FIFO2 Port A read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output

34. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

Switching Waveforms (continued)

X1 Word in FIFO1

CLKA

ENA

CLKB

AEB

ENB

Timing for AEB when FIFO1 is Almost Empty (CY Standard and FWFT Modes)[1, 31, 32]

tPAE

tENH

tENS

tSKEW2[32]

tENS tENH

(X1+2)Words in FIFO1

tENS tENH

tENH

tENS X1 Words in FIFO

(X1+1) Words in FIFO1 (X1+ 2) Word s in FIFO1

X2 Word in FIFO2

CLKB

ENB

CLKA

AEA

ENA

Timing for AEA when FIFO2 is Almost Empty (CY Standard and FWFT Modes)[1, 33, 34]

tPAE

tENH

tENS

tSKEW2[34]

tENS tENH

(X2+2)Words in FIFO2

tENS tENH

tENH

tENS X2 Words in FIFO

(X2+1) Words in FIFO2 (X2+ 2) Word s in FIFO2

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 22 of 31

Notes:

35. FIFO1 Port A Write (CSA = LOW , W/RA = HIGH, MBA = LOW), FIFO1 Port B read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output

36. D = Maximum FIFO Depth = 1K for the CY7C43642AV, 4K for the CY7C43662AV, and 16K for the CY7C43682AV.

37. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the

rising CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.

38. FIFO2Port A Wr ite (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 Port A Read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output

39. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between

the rising CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.

Switching Waveforms (continued)

Timing for AFA when FIFO1 is Almost Full (CY Standard and FWFT Modes)

tENH

tENS

tPAF

[D–(Y1+1)] Words in FIFO1 (D–Y1)Words in FIFO1

CLKA

ENA

AFA

CLKB

ENB

[35, 36, 37]

tPAF

tENS tENH

[D–(Y1+2)] words in FIFO1

tSKEW2[37]

tENS tENH

Timing for AFB when FIFO2 is Almost Full (CY Standard and FWFT Modes)

tENH

tENS

tPAF

[D–(Y2+2)] Words in FIFO2

CLKB

ENB

AFB

CLKA

ENA

[36, 38,39]

(D–Y2)Words in FIFO2

tPAF

tENS tENH

[D–(Y2+2)] words in FIFO2

tSKEW2[39]

tENS tENH

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 23 of 31

Switching Waveforms (continued)

tENH

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tDH

tDS

tPMF tPMF

tEN tMDV tPMR

tENS tENH

tDIS

FIFO1 Output Register W1 (Remains valid in Mail1 Register after read)

CLKA

CSA

W/RA

MBA

ENA

A0–35

CLKB

MBF1

CSB

W/RB

MBB

ENB

Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)

B0−35

[17]

[20]

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 24 of 31

Notes:

40. Retransmit is performed in the same manner for FIFO2.

41. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one write clock cycle before the falling edge of R T1, and

during the retransmit operation, i.e. when RT1 is LOW and tRTR after the RT1 rising edge.

42. The Empty and Full flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.

43. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary af ter tRTR to updat e thes e flags .

Switching Waveforms (continued)

tENH

tENS

tENH

tENS

tENH

tENS

tENH

tENS

tDH

tDS

tPMF tPMF

tEN tMDV tPMR

tENS tENH

tDIS

FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)

CLKB

CSB

W/RB

MBB

ENB

B0–35

CLKA

MBF2

CSA

W/RA

MBA

ENA

A0−35

Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes )

[17]

[20]

FIFO1 Retransmit Timing

ENB

RT1

tRTR

EFB/FFA

[40, 41, 42, 43]

tRSTS tRSTH

CLKA

CLKB

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 25 of 31

Signal Descript ion

Reset (MRST1, MRST2)

Each of the two FIFO me mo rie s o f th e CY 7C4 36X2 AV under-

goes a complete reset by taking its associated Master Reset

(MRST1, MRST2) input LOW for at least four Port A clock

(CLKA) and four Port B clock (CLKB) LOW-to-HIGH transi-

tions. The Master Reset inputs can switch asynchronously to

the clocks. A Master Reset initializes the internal read and

write pointers and forces the Full/Input Ready flag (FFA/IRA,

FFB/IRB) LOW, the Empty/Output Ready flag (EFA/ORA,

EFB/ORB) LOW , the Almost Empty flag (AEA, AEB) LOW , and

the Almost Full flag (AFA, AFB) HIGH. A Master Reset also

forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox

Ready flag is set HIGH after two clock cycles to begin normal

operation. A Master Reset must be performed on the FIFO

after power up, before data is written to its memory.

A LOW -to-HI GH tra nsi tio n on a FIFO rese t (MRST1, MRST2)

input latches the values of the Flag select (FS0, FS1) for

choosing the Almost Full and Almost Empty offset program-

ming method (see Almost Empty and Almost Full flag offset

programming below).

First-Word Fall-Through (FWFT/STAN)

After Mas ter Reset, the FWFT select functio n is active, perm it-

ting a choice between two possible timing modes: CY Stan-

dard Mode or First-Word Fall-Through (FWFT) Mode. Once

the Master R eset (MRST1, MRST2) input is HIG H, a HIGH on

the FWFT/STAN input at the second LOW-to-HIGH transition

of CLKA (for FIFO1) and CLKB (for FIFO2) will select CY Stan-

dard Mode. This mode uses the Empty Flag function (EFA,

EFB) to ind icate wh ether or not the re are a ny words present in

the FIFO memory. It uses the Ful l Fl ag f unc tio n (FFA, FFB) to

indicate whether or not the FIFO memory has any free space

for writing. In CY Standard mode, every word read from the

FIFO, including the first, must be requested using a formal

read operati on.

Once the Master Reset (MRST1, MRST2) input is HIGH, a

LOW on the FWFT/STAN input during the next LOW-to-HIGH

transition of CLKA (for FIFO1) and CLKB (for FIFO2) will select

FWFT Mode. This mode uses the Output Ready function

(ORA, ORB) to indicate whether or not there is valid data at

the data out puts (A0–35 or B0–35). It also uses the Input Ready

function (IRA, IRB) to indicate whether or not the FIFO mem-

ory has any free space f or wri ting. I n t he FWFT mode, the firs t

word written to an empty FIFO goes directly to data outputs,

no read request necessary. Subsequent words must be ac-

cessed by performing a formal read operation.

Following Master Reset, the level applied to the FWFT/STAN

input to choose the desired timing mode must remain static

throughout the FIFO operation.

Programming the Almost Empty and Almost Full Flags

Four registers in the CY7C436X2A V are used to hold the offset

values for the Almost Em pty a nd Alm ost Full fla gs. The Po rt B

Almost Empty flag (AEB) offset register is labeled X1 and the

Port A Almost Empty flag (AEA) offset register is labeled X2.

The Port A Almost Full flag (AFA) offset register is labeled Y1

and the Port B Al mo st Fu ll fla g (AF B) offset register i s lab ele d

Y2. The index of each register name corresponds with preset

values during the reset of a FIFO, programmed in parallel us-

ing the FIFO’s Port A data inputs.

To program the X1, X2, Y1, and Y2 registers in parallel from

Port A, perfo rm a Mas ter Rese t on both FI FOs simul taneousl y

with SPM HIGH and FS0 and FS1 LOW during the LOW-to-

HIGH transition of MRST1 and MRST2. Af ter this reset is com-

plete, the first four writes to FIFO1 do not store data in RAM

but load the offset registers in the order Y1, X1, Y2, X2. The

Port A data inputs used by the offset registers are (A0–9),

(A0–11), or (A0–13), for the CY7C436X2AV, respectively. The

highest numbered input is used as the most significant bit of

the bin ary numb er in ea ch case . Valid programm ing val ues for

the regis ter s rang e from 0 to 1 023 for the C Y7C4 3642AV; 0 to

4095 for the CY7C43662A V; 0 to 16383 for the CY7C43682A V .

(see foot note #1) After all the of fset reg isters are programmed

from Port A, the Port B Full/Input Ready (FFB/IRB) is set HIGH

and both FIFOs begin normal operation.

FS0 and F S1 f unctio n the same way in both C Y Stan dard an d

FWFT modes.

FIFO Write/Read Operation

The state of the Port A data (A0–35) lines is controlled by Port

A Chip Select (CSA) and Port A Write/Read Select (W/RA).

The A0–35 lines are in the high-impedance state when either

CSA or W/RA is HIGH. The A0–35 lines are active outputs

when both CSA and W/RA are LOW.

Data is loaded into FIFO1 from the A0–35 i nputs on a LOW -to-

HIGH transition of CLKA when CSA is LOW, W/RA is HIGH,

ENA is HIGH, MBA is LOW, and FF A/IRA is HIGH. Data is read

from FIFO2 to the A0–35 outputs by a LO W -to-HI GH transi tion

of CLKA when CSA is LOW, W/RA is LOW , ENA is HIGH, MBA

is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and

writes on Port A are independent of any concurrent Port B

operation.

The Port B c ontro l s ig nal s a re id ent ic al to those of Po rt A wi th

the exception that the Port B Write/Read select (W/RB) is the

inverse of the Port A Write/Read select (W/RA). The state of

the Port B data (B0–35) lines is controlled by the Port B Chip

Select (CSB) and Port B Write/Re ad select (W/RB). The B0–35

lines are in the high-impedance state when either CSB is

HIGH or W/RB is LOW. The B0–35 lines are active outputs

when CSB is LOW and W/RB is HIGH.

Data is loaded into FIFO2 from the B0–35 i nputs on a LOW -to-

HIGH transition of CLKB when CSB is LOW, W/RB is LOW,

ENB is HIGH, MBB is LOW , and FFB/IRB is HIGH. Data is read

from FIFO1 to the B0–35 outputs by a LO W -to-HI GH transi tion

of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH,

MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO

reads an d writ es on Po rt B are in depen dent of any co ncurre nt

Port A operation.

The set-up and hold tim e co ns trai nts to the port c loc ks for th e

port Ch ip Selects and Writ e/Read sel ects are on ly for enab ling

write and read operations and are not related to high-imped-

ance control of the data outputs. If a port enable is LOW during

a clock cycle, the port’s Chip Select and Write/Read select

may ch an ge s ta t es du ring th e s et-u p a nd hold ti me w in dow of

the cycle.

When operating the FIFO in FWFT Mode and the Output

Ready flag is LOW, the next word wr itten is automa ticall y sent

to the F IFO’s o utput regi ster by th e LOW- to-HIGH tra nsition of

the port clock that sets the Output Ready flag HIGH, data re-

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 26 of 31

siding in the FIFO’s memory array is clocke d to the output re g-

ister only when a read is selected using the port’s Chip Select,

Write/Read select, Enable, and Mailbox select.

When opera ting the FIFO in CY Standard M ode, regardless of

whether the Empty Flag is LOW or HIGH, data residing in the

FIFO’s memory array is clocked to the output register only

when a read is selected using the port’s Chip Select, Write/

Read select, Enable, and Mailbox select.

Synchronized Flags

Each FIFO is synchronized to its port clock through at least

two fli p-flop stages. Th is is done to improve flag-s ignal reliabi l-

ity by reducing the probability of the metastable events when

CLKA and CLKB operate asynchronously to one another . EF A/

ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.

EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to

CLKB. Table 4 and Table 5 show the rel ati ons hi p of ea ch port

flag to FIFO1 and FIFO2.

Empty/Output Ready Flags (EFA/ORA, EFB/ORB)

These are dual-purpose flags. In the FWFT Mode, the Output

Ready (ORA, ORB) function is selected. When the Output

Ready flag is HIGH, new data is present in the FIFO output

data word remains in the FIFO output register and any FIFO

reads are ignored.

In the CY Standard Mo de, the Empty Flag (E FA, EFB) function

is sele cted. When the Emp ty Flag is HIGH, dat a is availab le in

the FIFO’s RAM memory for reading to the output register.

When Empty Flag is LOW, the previous data word remains in

the FIFO output register and any FIFO reads are ignored.

The Emp ty/Outpu t Ready flag of a F IFO is sync hronized to the

port clock that reads data from its array. For both the FWFT

and CY Standa rd mo des , the FIFO read poin ter is in cre me nt-

ed each time a new word is clocked to its output register. The

state machine that controls an Output Ready flag monitors a

write poi nter and read poin ter comp arator tha t indica tes when

the FIFO SRAM status is empty, empty+1, or empty+2.

In FWFT Mod e, from the ti me a word is written to a FIFO, it ca n

be shifted to the FIFO output register in a minimum of three

cycles of the Output Ready flag synchronizing clock. There-

fore, an Output Ready flag is LOW if a word in memory is the

nex t dat a to be se nt to t he FI FO out p ut reg i st er and th r e e cy -

cles have not elapsed since the time the word was written. The

Output Ready flag of the FIFO remains LOW until the third

LOW -to-HIGH tran si tio n o f the sy nc hron iz ing c lo ck occ urs , s i-

multane ously fo rcing t he Output Ready flag H IGH and s hifting

the word to the FIFO output register.

In the CY Standard Mod e, from the time a word is writte n to a

FIFO, the Empty Flag will indicate the presence of data avail-

able for reading in a minimum of two cycles of the Empty flag

synchronizing clock. Therefore, an Empty flag is LOW if a word

in memory is the next data to be sent to the FIFO output reg-

ister an d tw o cy cl es hav e not ela ps ed s in ce the tim e t he w o rd

was written . The Empty flag of the FIFO remains LOW until th e

second LOW -to-HIGH transition of the synchronizing cl ock oc-

curs, forc ing the Empty flag H IGH; only then can d ata be read.

A LOW-to-HIGH transition on an Empty/Output Ready flag

synch ronizi ng cl ock beg ins the fir st sync hroniz ation cy cle of a

write if the clock transition occurs at time tSKEW1 or greater

after the write. Otherwise, the subsequent clock cycle will be

the first synchronization cycle.

Full/Input Ready Flags (FFA/IRA, FFB/IRB)

This is a dual-purpose flag. In FWFT Mode, the Input Ready

(IRA and IRB) fu nc tion is sel ected. In CY Stan dard Mode, th e

Full Flag (FFA and FFB) function is selected. For both timing

modes, when the Full/Input Ready flag is HIGH, a memory

location is free in the SRAM to receive new data. No memory

locations are free when the Full/Input Ready flag is LOW and

any writes to the FIFO are ignored.

The Full /Input Ready fl ag of a FIFO i s synchronize d to the port

clock that writes data to it s array . For both FWFT and CY Stan-

dard modes, each time a word is written to a FIFO, its write

pointer is incremen ted. The state machine th at controls a Ful l/

Input Ready flag monitors a write pointer and read pointer

compara tor tha t indi ca tes when the FIFO SRAM status is full,

full–1, or full–2. From the time a word is read from a FIFO, its

previous memory location is ready to be written to in a mini-

mum of two cycles of the Full/Input Ready flag synchronizing

clock. Therefore, an Full/Input Ready flag is LOW if less than

two cycles of the Full/Input Ready flag synchronizing clock

have elapsed since the next memory write location has been

read. The second LOW-to-HIGH transition on the Full/Input

Ready flag synchronizing clock after the read sets the Full/

Input Ready flag HIGH.

A LOW -to-HIGH tra nsition on a Ful l/Input R eady flag syn chro-

nizing clock begins the first synchronization cycle of a read if

the clock transition occurs at time tSKEW1 or greater after the

read. Otherwise, the subsequent clock cycle can be the first

synchronization cycle.

Almost Empty Flags (AEA, AEB)

The Almost Empty flag of a FIFO is synchronized to the port

clock that reads data from its array. The state machine that

controls an Almost Empty flag monitors a write pointer and

read pointer comparator that indicates when the FIFO SRAM

status is almost empty, almost empty+1, or almost empty+2.

The Almost Empty state is defined by the contents of register

X1 for AE B and register X2 for AEA . These regist ers are loa d-

ed with preset values during a FIFO reset, programmed from

Port A, or programmed serially (see Almost Empty flag and

Almost Full fl ag of fse t p rogram ming abo ve). An Almos t Empt y

flag is LOW when its FIFO contains X or less words and is

HIGH when its FIFO contains (X+2) or more words.[1]

The Almost Empty flag is set HIGH by the first LOW-to-HIGH

transition of its synchronizing clock after two FIFO writes that

fills memory to the (X+2) level. A LOW-to-HIGH transition of an

Almost Empty flag synchronizing clock begins the first syn-

chronization cycle if it occurs at time tSKEW2 or greater after

the write that fills the FIFO to (X+2) words. Otherwise, the sub-

sequent synchronizing clock cycle will be the first synchroni-

zation cycle.

Almost Full Flags (AFA, AFB)

The Almost Full flag of a FIFO is synchronized to the port clock

that write s data to its array. The state machi ne that controls an

Almost Full flag monitors a write pointer and read pointer com-

parator that indicates when the FIFO SRAM status is almost

full, almost full–1, or almost full–2. The Almost Full state is

defined by t he conte nts o f re gi ste r Y1 fo r AFA and regis ter Y2

for AFB. These re gis ters a re l oa ded w ith pr eset val ues d urin g

a FIFO reset, programmed from Port A, or programmed seri-

ally (see Almost Empty flag and Almost Full flag offset pro-

grammi ng above). An Al mo st Fu ll fl ag is LO W whe n th e num -

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Document #: 38-06020 Rev. ** Page 27 of 31

ber of wor ds in its F IFO is gr eater th an or e qual to (1 024–Y),

(4096–Y), or (16384–Y) for the CY7C436X2AV respectively.

An Almost Full flag is HIGH when the number of words in its

FIFO is less than or equal to [1024–(Y+2)], [4096–(Y+2)], or

[16384–(Y+2)], for the CY7C436X2AV respectively.[1]

The Almost Full flag is set HIGH by the first LOW-to-HIGH

transition of its synchronizing clock after two FIFO reads that

reduces the number of words in memory to [1024/4096/

16384–(Y+2)]. A LOW-to-HIGH transition of an Almost Full

flag sy nc hron iz ing cloc k b egi ns the firs t s ync hro ni zat ion cycl e

if it occurs at time tSKEW2 or greater after the read that reduces

the number of wor ds i n me mo ry to [1024/4 096 /16384–(Y+2)].

Otherwise, the subsequent synchronizing clock cycle will be

the first synchronization cycle.

Mailbox Regis ters

Each F IFO has a 36-b it bypas s registe r to pass com mand an d

control information between Port A and Port B without putting

it in queue. The Mailbox Select (MBA, MBB) inputs choose

between a mail register and a FIFO for a port data transfer

operation.

A LOW-to-HIGH transition on CLKA writes A0−35 data to the

Mail1 Re gister wh en a Port A writ e is selec ted by CSA, W/RA,

and ENA with MBA HIGH.

A LOW-to-HIGH transition on CLKB writes B0−35 data to the

Mail2 Re gister wh en a Port B writ e is selec ted by CSB, W/RB,

and ENB with MBB HIGH.

Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LO W . Attempt ed writes to a mail regi ster are

ignored while the mail flag is LOW.

When data outputs of a port are active, the data on the bus

comes from the FIFO output register when the port Mailbox

Select input is LOW and from the mail register when the port

Mailbox Select input is HIGH.

The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-

HIGH transition on CLKB when a Port B read is selected by

CSB, W/RB, and ENB with MBB HIGH.

The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH

transiti on on CLKA when a Port A read i s selected by CSA, W/

RA, and ENA with MBA HIGH.

The data in a mail register remains intact after it is read and

changes only when new data is written to the register. The

Endian Select feature has no effect on the mailbox data.

Retransmit (RT1, RT2)

The retransmit feature is beneficial when transferring packets

of data. It enables the receipt of data to be acknowledged by

the receiver and retransmitted if necessary. Retransmit func-

tion applies to CY standard mode only.

The retransmit feature is intended for use when a number of

writes equal to or less than the depth of the FIFO have oc-

curred and at least one word has been read since the last reset

cycle. A LOW pulse on RT1, RT2 resets the internal read point-

er to the first physical location of the FIFO. CLKA and CLKB

may be free running but ENB must be deasserted during and

tRTR after the retransmit pulse. With every valid read cycle after

retransmit, previously accessed data is read and the read

pointer is incremented until it is equal to the write pointer. Flags

are governed by the relative locations of the read and write

pointers and are u pda ted duri ng a retran sm it c yc le . Data wri t-

ten to the FIFO after activation of RT1, RT2 are transmitted

also.

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CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 28 of 31

Table 1. Flag Programming

FS1 FS0 MRST1 MRST2 X1 and Y1 Registers[44] X2 and Y2 Registers[45]

H H ↑X64 X

H H X ↑X64

H L ↑X16 X

H L X ↑X16

L H ↑X 8 X

L H X ↑X 8

L L ↑ ↑ Programming via Port A Programming via Port A

Table 2. Port A Enable Function

CSA W/RA ENA MBA CLKA A0–35 Port Function

H X X X X In high-impedance state None

L H L X X In high-impedance state None

LHHL↑In high-impedance state FIFO1 write

LHHH↑In high-impedance state Mail1 write

L L L L X Active, FIFO2 output register None

LLHL↑Active, FIFO2 output register FIFO2 read

L L L H X Active, Mail2 register None

LLHH↑Active, Mail2 register Mail2 read (set MBF2 HIGH)

Table 3. Port B Enable Function

CSB W/RB ENB MBB CLKB B0–35 Port Func tion

H X X X X In high-impedance state None

L L L X X In high-impedance state None

LLHL↑In high-impedance state FIFO2 write

LLHH↑In high-impedance state Mail2 write

L H L L X Active, FIFO1 output regi ste r None

LHHL↑Ac tiv e, FIFO1 out put regi ste r FIFO1 read

L H L H X Activ e, Ma il1 regist er None

LHHH↑Active, Mail1 register Mail1 read (set MBF1 HIGH)

Notes:

44. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.

45. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.

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PRELIMINARY

Document #: 38-06020 Rev. ** Page 29 of 31

Table 4. FIFO1 Flag Operation (CY Standard and FWFT Modes)

Number of Words in FIFO Memory[1 , 46, 47 , 4 8, 49] Synchronized to CLKB Synchronized to CLKA

CY7C43642AV CY7C43662AV CY7C43682AV EFB/ORB AEB AFA FFA/IRA

0 0 0 L L H H

1 to X1 1 to X1 1 to X1 H L H H

(X1+1) to

[1024–(Y1+1)] (X1+1) to

[4096–(Y1+1)] (X1+1) to

[16384–(Y1+1)] HH HH

(1024–Y1) to

1023 (4096–Y1) to

4095 (16384–Y1) to

16383 HH L H

1024 4096 16384 H H L L

Table 5. FIFO2 Flag Operation (CY Standard and FWFT modes)

Number of Words in FIFO Memory[1 , 47 , 48 , 50, 51 ] Synchronized to CLKA Synchronized to CLKB

CY7C43642AV CY7C43662AV CY7C43682AV EFA/ORA AEA AFB FFB/IRB

0 0 0 L L H H

1 to X2 1 to X2 1 to X2 H L H H

(X2+1) to

[1024–(Y2+1)] (X2+1) to

[4096–(Y2+1)] (X2+1) to

[16384–(Y2+1)] HHHH

(1024–Y2) to 1023 (4096–Y2) to 4095 (16384–Y2) to

16383 HHL H

1024 4096 16384 H H L L

Notes:

46. X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is t he alm o st - f ull o ffse t fo r FI FO1 u s ed by AFA. Both X1 and Y1 are selected during a FIFO1 reset

or port A programming.

47. When a word loaded to an empty FIFO is shifted to the output register , its previous FIFO memory location is free.

48. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to

the output register (no read operation necessary), it is not included in the FIFO memory count.

49. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in CY Standard mode.

50. X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset

or port A programming.

51. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in CY Standard mode.

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 30 of 31

of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi

ng so indemnifies Cypress Semiconductor against all charges.

3.3V 1K x36 x2 Bidirectional Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

7CY7C43642AV-7AC A120 1 20-L ea d Thin Qu ad Flat Package Commercial

10 CY7C43642AV-10AC A120 120-L ea d Thin Qu ad Flat Package Commercial

15 CY7C43642AV-15AC A120 120-L ea d Thin Qu ad Flat Package Commercial

3.3V 4K x36 x2 Bidirectional Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

7 CY7C43662AV -7AC A120 120-Lea d Thin Quad Flat Packa ge Comme rci al

10 CY7C 436 62AV - 10 AC A120 120-Lead Thin Qu ad Flat Package Comme rci al

15 CY7C 436 62AV - 15 AC A120 120-Lead Thin Qu ad Flat Package Comme rci al

3.3V 16K x36 x2 Bidirectiona l Synchronous FIFO

Speed

(ns) Ordering Code Package

Name Package

Type Operating

Range

7 CY7C43682AV -7AC A120 120-Lea d Thin Quad Flat Packa ge Comme rci al

10 CY7C 436 82AV - 10 AC A120 120-Lead Thin Qu ad Flat Package Comme rci al

15 CY7C 436 82AV - 15 AC A120 120-Lead Thin Qu ad Flat Package Comme rci al

15 CY7C43682AV-15AI A120 120-L ea d Thin Qu ad Flat Package Industrial

Shaded area contains advance information.

Package Diagram

120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) A120

51-85100

CY7C43642AV

CY7C43662AV/CY7C43682AV

PRELIMINARY

Document #: 38-06020 Rev. ** Page 31 of 31

Document Title: CY7C436 42AV, CY7C43662AV, CY7C4 3682AV 3.3V 1K/4K/16 K x36 x2 Bidirectiona l Synchronous FIFO

REV. ECN NO. Issue Date Orig. of Change Description of Change

** 106559 05/17/01 SZV Change from Spec #: 38-00775 to 38-06020