©2008 Integrated Device Technology, Inc.
OCTOBER 2008
DSC-2691/13
1
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM
WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
Features
◆◆
◆◆
◆High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 25/55ns (max.)
◆◆
◆◆
◆Low-power operation
– IDT71321/IDT71421SA
—Active: 325mW (typ.)
—Standby: 5mW (typ.)
– IDT71321/421LA
—Active: 325mW (typ.)
—Standby: 1mW (typ.)
◆◆
◆◆
◆Two INT flags for port-to-port communications
Functional Block Diagram
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
◆◆
◆◆
◆MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
◆◆
◆◆
◆On-chip port arbitration logic (IDT71321 only)
◆◆
◆◆
◆BUSY output flag on IDT71321; BUSY input on IDT71421
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆Battery backup operation – 2V data retention (LA only)
◆◆
◆◆
◆TTL-compatible, single 5V ±10% power supply
◆◆
◆◆
◆Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
◆◆
◆◆
◆Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆◆
◆◆
◆Green parts available, see ordering information
I/O
Control
Address
Decoder MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
2691 drw 01
I/O
0L
-I/O
7L
CE
L
OE
L
R/W
L
INT
L
BUSY
R
I/O
0R
-I/O
7R
A
10R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2) (1,2)
(2)
R/W
R
CE
R
OE
R
R/W
R
11
11
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
IDT71321/421J
J52-1
(4)
PLCC
Top View
(5)
I
NDEX
I/O
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
3L
2L
OE
A
A
A
A
A
A
A
A
A
A
NC
I/O
R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
4L
5L
6L
7L
NC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0R
1R
2R
3R
4R
6R
5R
A
0L
OE
A
INT
BUSY
R/W
CE
V
CE
R/W
BUSY
INT
A
L
10L
L
L
CC
R
R
R
10R
R
L
L
1
234567474849505152
9
8
10
11
12
13
14
15
16
17
18
19
20 27262524232221 333231302928
35
34
36
37
38
39
40
41
42
43
44
45
46
2691 drw 02
,
I
NDEX
IDT71321/421PF or TF
PN64-1 / PP64-1
(4)
64-Pin TQFP
64-Pin STQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33 I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
2691 drw 03
17
18
19
20
32
31
30
29
28
27
26
25
24
23
22
21
49
50
51
52
63
62
61
60
59
58
57
56
55
54
53
64
N/C
A
10R
N/C
N/C
A
10L
N/C
GND
N/C
N/C
GND
N/C
R/W
R
CE
R
V
CC
V
CC
BUSY
L
INT
L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
R/W
L
CE
L
BUSY
R
INT
R
,
Pin Configurations(1,2,3)
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs,
64-pin TQFPs, and 64-pin STQFPs.
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Recommended DC Operating
Conditions
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Symbol Rating Commercial
& Industrial Unit
V
TERM
(2)
Te rmi nal Vo l tag e
wi th Re s p e c t
to GND
-0.5 to +7.0 V
T
BIAS
Temperature
Unde r Bias -55 to +125
o
C
T
STG
Storage
Temperature -65 to +150
o
C
I
OUT
DC O utp ut
Current 50 mA
2691 tbl 01
Grade Ambient
Temperature GND Vcc
Commercial 0
O
C to + 70
O
C0V5.0V
+
10%
Industrial -40
O
C to + 85
O
C0V 5.0V
+
10%
2691 tbl 02
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup ply Voltag e 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Input High Voltag e 2.2
____
6.0
(2)
V
V
IL
Inp ut Lo w Vo l tag e -0. 5
(1)
____
0.8 V
2691 tb l 03
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol Parameter Conditions
(2)
Max. Unit
C
IN
Input Capacitance V
IN
= 3dV 9 pF
C
OUT
Outp ut Cap ac itanc e V
OUT
= 3dV 10 pF
2691 tbl 00
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& I nd
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Unit
I
CC
Dynamic Op erating
Current
(Both Ports Active )
CE
L
and CE
R
= V
IL
,
Outp uts Dis ab le d
f = f
MAX
(2)
COM'L SA
LA 110
110 250
200 110
110 220
170 mA
IND SA
LA
____
____
____
____
110
110 270
220
I
SB1
Standb y Current
(Both Ports - TTL
Lev el Inputs )
CE
L
and CE
R
= V
IH
f = f
MAX
(2)
COM'L SA
LA 30
30 65
45 30
30 65
45 mA
IND SA
LA
____
____
____
____
30
30 75
55
I
SB2
Standb y Current
(One P o rt - TTL
Lev el Inputs )
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(2)
COM'L SA
LA 65
65 165
125 65
65 150
115 mA
IND SA
LA
____
____
____
____
65
65 170
140
I
SB3
Full Standby Current
(Both Ports -
CMOS Le ve l Inp uts )
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0 .2V o r
V
IN
< 0.2V, f = 0
(3)
COM'L SA
LA 1.0
0.2 15
51.0
0.2 15
5mA
IND SA
LA
____
____
____
____
1.0
0.2 30
10
I
SB4
Full Standby Current
(One P o rt -
CMOS Le ve l Inp uts )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(2)
COM'L SA
LA 60
60 155
115 60
60 145
105 mA
IND SA
LA
____
____
____
____
60
60 165
130
2691 tbl 04a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& I nd
Symbol Parameter Test Condition Versi on Typ. Max. Typ. Max. Unit
I
CC
Dy na m i c O p era ti ng
Current
(Both Ports Active)
CE
L
and CE
R
= V
IL
,
Outp uts Disab le d
f = f
MAX
(2)
COM'L SA
LA 80
80 165
120 65
65 155
110 mA
IND SA
LA
____
____
____
____
65
65 190
140
I
SB1
Stand by Current
(Bo th Po rts - TTL
Lev el Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(2)
COM'L SA
LA 25
25 65
45 20
20 65
35 mA
IND SA
LA
____
____
____
____
20
20 70
50
I
SB2
Stand by Current
(One Po rt - TTL
Lev el Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
A c tiv e P o r t Outputs D i sa b l e d ,
f=f
MAX
(2)
COM'L SA
LA 50
50 125
90 40
40 110
75 mA
IND SA
LA
____
____
____
____
40
40 125
90
I
SB3
Full Standby Current
(Bo th Po rts -
CMOS Le v el Inp uts)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V o r
V
IN
< 0.2V, f = 0
(3)
COM'L SA
LA 1.0
0.2 15
41.0
0.2 15
4mA
IND SA
LA
____
____
____
____
1.0
0.2 30
10
I
SB4
Full Standby Current
(One Po rt -
CMOS Le v el Inp uts)
CE
"A"
< 0. 2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0 .2V o r V
IN
< 0.2V
A c tiv e P o r t Outputs D i sa b l e d ,
f = f
MAX
(2)
COM'L SA
LA 45
45 110
85 40
40 100
70 mA
IND SA
LA
____
____
____
____
40
40 110
85
2691 t bl 04b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
V
CC
CE
4.5V 4.5V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
2691 drw 04
≥
,
Symbol Parameter Test Conditions
71321SA
71421SA 71321LA
71421LA
UnitMin. Max. Min. Max.
|I
LI
| Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5µA
|I
LO
|Outp ut Le ak age Curre nt
(1)
CE = V
IH
, V
OUT
= 0V to V
CC
,
V
CC
- 5. 5V
___
10
___
5µA
V
OL
Outp ut Lo w Vo ltag e (I/O
0
-I/O
7
)I
OL
= 4mA
___
0.4
___
0.4 V
V
OL
Op e n Drain Outp ut
Lo w Vol tag e (BUSY/INT)I
OL
= 16mA
___
0.5
___
0.5 V
V
OH
Output Hig h Voltage I
OH
= -4mA 2.4
___
2.4
___
V
2691 t bl 0 5
Symbol Parameter Test Condition Min. Typ.
(1)
Max. Unit
V
DR
V
CC
fo r Da ta Re tenti o n 2. 0
____
0V
I
CCDR
Data Re te ntio n Current V
CC
= 2.0V, CE > V
CC
- 0. 2V COM' L
____
100 1500 µA
V
IN
> V
CC
- 0.2V o r VI
N
< 0. 2V IND
____
100 4000 µA
t
CDR
(3)
Chip Des e l e c t to Da ta Re tentio n Time 0
____ ____
ns
t
R
(3)
Operation Re covery Time t
RC
(2)
____ ____
ns
2691 tbl 06
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
6
5V
1250Ω
30pF*
775Ω
DATA
OUT
5V
1250Ω
775Ω5pF*
DATA
OUT
2691 drw 05
5V
270Ω
30pF*
BUSY or INT
*100pF for 55ns versions
*100pF for 55ns versions
,
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
Figure 3. BUSY and INT
AC Output Test Load
AC Test Conditions
Input Pulse Levels
Inp ut Ris e /Fall Tim e s
Inp ut Timing Refe rence Le v els
Outp ut Re fe re nc e Le ve ls
Outp ut Load
GND to 3.0V
5ns
1.5V
1.5V
Fi gu re s 1, 2 and 3
2691 tbl 07
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
7
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(2)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Re ad Cycle Time 20
____
25
____
ns
t
AA
Address Access Time
____
20
____
25 ns
t
ACE
Chip Enable Acce ss Time
____
20
____
25 ns
t
AOE
Outp ut Enab le Acce ss Ti me
____
11
____
12 ns
t
OH
Outp ut Hold fro m Ad d re ss Chang e 3
____
3
____
ns
t
LZ
O ut p u t L o w -Z Ti m e
(1,3)
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,3)
____
10
____
10 ns
t
PU
Chip Enab le to Powe r Up Time
(3)
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po we r Down Time
(3)
____
20
____
25 ns
2 691 tbl 08a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
UnitSymbol Parameter Min. Max. Min. Max.
READ CYCLE
t
RC
Re ad Cycle Time 35
____
55
____
ns
t
AA
Address Access Time
____
35
____
55 ns
t
ACE
Chip Enable Acce ss Time
____
35
____
55 ns
t
AOE
Outp ut Enab le A cc e ss Time
____
20
____
25 ns
t
OH
Outp ut Hold fro m Ad dre s s Chang e 3
____
3
____
ns
t
LZ
O ut p u t Low -Z Ti m e
(1,3)
0
____
5
____
ns
t
HZ
Output High-Z Time
(1,3)
____
15
____
25 ns
t
PU
Chip Enab le to Power Up Time
(3)
0
____
0
____
ns
t
PD
Chi p Dis ab le to Po wer Do wn Time
(3)
____
35
____
50 ns
2691 tbl 08b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
8
Timing Wa v eform of Read Cyc le No. 2, Either Side (3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4 . Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Wa veform of R ead Cyc le No. 1, Either Side(1)
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2691 drw 06
t
BDDH
(2,3)
BUSY
OUT
CE
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2691 drw 07
(4)
(1)
(1) (2)
(2)
(4)
t
LZ
t
HZ
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
9
AC Electrical Characteristics Over the
Operating Temeprature and Supply Voltage Range(4)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
Symbol Parameter
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
UnitMin. Max. Min. Max.
WR I T E CY CL E
t
WC
Wri te Cy cle Tim e
(2)
20
____
25
____
ns
t
EW
Chip Enable to End -o f-Write 15
____
20
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(3)
15
____
15
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 10
____
12
____
ns
t
HZ
Output High-Z Time
(1)
____
10
____
10 ns
t
DH
Data Ho l d Tim e 0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1)
____
10
____
10 ns
t
OW
Outp ut Activ e fro m E nd -of-Write
(1)
0
____
0
____
ns
2 691 tbl 09a
Symbol Parameter
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& In d
UnitMin. Max. Min. Max.
WR I T E CY CL E
t
WC
Wri te Cy cle Tim e
(2)
35
____
55
____
ns
t
EW
Chip Enable to End -o f-Write 30
____
40
____
ns
t
AW
Address Valid to End-of-Write 30
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
ns
t
WP
Write Pulse Width
(3)
25
____
30
____
ns
t
WR
Write Recovery Time 0
____
0
____
ns
t
DW
Data Valid to End-of-Write 15
____
20
____
ns
t
HZ
Output High-Z Time
(1)
____
15
____
25 ns
t
DH
Data Ho l d Tim e 0
____
0
____
ns
t
WZ
Write Enable to Output in High-Z
(1)
____
15
____
30 ns
t
OW
Outp ut Activ e fro m E nd -of-Write
(1)
0
____
0
____
ns
2691 tbl 09b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
10
Timing Wa v eform of Write Cyc le No. 2, (CE Controlled Timing)(1,5)
Timing Wav eform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
ADDRESS
OE
CE
R/W
DATA
OUT
DATA
IN
(4) (4)
2691 drw 08
t
WC
t
AS
(6)
t
WR
(3)
t
OW
t
DW
t
DH
t
AW
t
WP
(2)
t
HZ
(7)
t
WZ
(7)
t
HZ
(7)
t
WC
ADDRESS
CE
R/W
DATA
IN
t
AS
(6)
t
EW
(2)
t
WR
t
DW
t
DH
t
AW
2691 drw 09
(3)
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
11
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, t WDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA)..
71321X20
71421X20
Co m' l On ly
71321X25
71421X25
Com'l
& I nd
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71321)
t
BAA
BUSY Access Time from Address
____
20
____
20 ns
t
BDA
BUSY Disable Time from Ad dress
____
20
____
20 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
20 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
20 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data De lay
(1)
____
50
____
50 ns
t
DDD
Wri te Data Va li d to Re ad Data De lay
(1)
____
35
____
35 ns
t
APS
A rb itrati on Pri ority Se t-up Ti me
(2)
5
____
5
____
ns
t
BDD
BUSY Dis ab le to Vali d Data
(3)
____
25
____
35 ns
BUSY INPUT TIMING (For SLAVE 71421)
t
WB
Wri te to BUSY Inp ut
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
ns
t
WDD
Write Pulse to Data De lay
(1)
____
40
____
50 ns
t
DDD
Wri te Data Va li d to Re ad Data De lay
(1)
____
30
____
35 ns
2691 tb l 10a
71321X35
71421X35
Co m' l On ly
71321X55
71421X55
Com'l
& I nd
Symbol Parameter Min.Max.Min.Max.Unit
BUSY TIMING (For MASTER 71321)
t
BAA
BUSY Access Time from Address
____
20
____
30 ns
t
BDA
BUSY Disab le Time from Address
____
20
____
30 ns
t
BAC
BUSY Access Time from Chip Enable
____
20
____
30 ns
t
BDC
BUSY Disable Time from Chip Enable
____
20
____
30 ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Puls e to Data Delay
(1)
____
60
____
80 ns
t
DDD
Wri te Data Vali d to Re ad Data Delay
(1)
____
35
____
55 ns
t
APS
A rb itrati on Pri ority Se t-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Dis ab le to Valid Data
(3)
____
35
____
50 ns
BUSY INPUT TIMING (For SLAVE 71421)
t
WB
Wri te to BUSY Inp ut
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
20
____
20
____
ns
t
WDD
Write Puls e to Data Delay
(1)
____
60
____
80 ns
t
DDD
Wri te Data Vali d to Re ad Data Delay
(1)
____
35
____
55 ns
2691 tbl 10b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
12
t
WC
t
WP
t
DW
t
DH
t
BDD
t
DDD
t
BDA
t
WDD
ADDR
"B"
D
ATA
OUT"B"
DATA
IN"A"
ADDR
"A"
MATCH
VALID
MATCH
VALID
R/W
"A"
BUSY
"B"
t
APS
(1)
2691 drw 10
t
BAA
Timing W av eform of Write with P ort-to-Port R ead and BUSY(2,3,4)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B " is opposite from port "A".
NOTES:
1. tWH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version (IDT71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Wa veform of Write with BUSY(4)
BUSY
"B"
2691 drw 11
R/W
"A"
t
WP
t
WH
t
WB
R/W
"B"
(2)
(1)
(3)
,
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
13
Timing Wa veform of BUSY Arbitration Controlled by CE Timing(1)
Timing Wa v ef orm of BUSY Arbritration Controlled
by Address Match Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (IDT71321 only).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
tAPS
(2)
ADDR "A"
AND "B" ADDRESSES MATCH
tBAC tBDC
CE"B"
CE"A"
BUSY"A"
2691 drw 12
BUSY
"B"
ADDRESSES DO NOT MATCH
ADDRESSES MATCH
t
APS
(2)
ADDR
"A"
ADDR
"B"
2691 drw 13
t
BAA
t
BDA
t
RC
or t
WC
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l
& Ind
Symbol Parameter Min. Max. Min. Max. Unit
INTE RRUP T TI MI NG
t
AS
Address Set-up Time 0 ____ 0____ ns
t
WR
Write Recovery Time 0 ____ 0____ ns
t
INS
In te rru p t S e t Ti m e ____ 20 ____ 25 ns
t
INR
In te rru p t Res e t Ti me ____ 20 ____ 25 ns
26 91 tb l 11 a
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
14
Timing Waveform of Interrupt Mode(1)
SET INT
CLEAR INT
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(1)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
tINS
ADDR"A"
INT"B"
INTERRUPT ADDRESS
t
WC
tAS
R/W"A"
tWR
2691 drw 14
(3)
(3)
(2)
(4)
t
RC
INTERRUPT CLEAR ADDRESS
A
DDR
"B"
OE
"B"
t
INR
INT
"B"
2691 drw 15
t
AS
(3)
(3)
(2)
,
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& I n d
Symbol Parameter Min. Max. Min. Max. Unit
INTERRUP T TIMI NG
t
AS
Address Set-up Time 0
____
0
____
ns
t
WR
Write Recove ry Time 0
____
0
____
ns
t
INS
In te rru p t S e t Ti me
____
25
____
45 ns
t
INR
Inte rrup t Re se t Time
____
25
____
45 ns
2 691 tbl 11b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
15
Truth Table III — Address BUSY Arbitration
Truth Table I. Non-Contention Read/Write Control(4)
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71321 (Master). Both are inputs for IDT71421 (Slave). BUSYX outputs on the IDT71321 are open drain, not push-
pull outputs. On slaves the BUSYX input internally inhibits writes.
2 . 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3 . Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Tables
T ruth T able II. Interrupt Flag(1,4)
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Left or Right Port
(1)
FunctionR/WCE OE D
0-7
X H X Z Port Disab l ed and in Power-Down Mo d e, ISB
2
or ISB
4
XHX Z
CE
R
= CE
L
= V
IH
, Powe r-Down Mod e, ISB
1
or ISB
3
LLXDATA
IN
D ata o n Po rt Writte n Into Me m o ry
(2)
HLLDATA
OUT
Data in Memory Output on Por
t
(3)
H L H Z Hig h Imp e d ance Outp uts
2691 tbl 12
Left P ort Ri ght P ort
FunctionR/W
L
CE
L
OE
L
A
10L
-A
0L
INT
L
R/W
R
CE
R
OE
R
A
10R
-A
0R
INT
R
L LX7FFXXXX X L
(2)
S e t Ri g h t INT
R
Flag
XXXXXXLL7FF H
(3)
Re s et Ri g h t INT
R
Fl ag
XXX X L
(3)
L L X 7F E X S e t L e ft INT
L
Flag
XLL7FE H
(2)
X X X X X Res et L e ft INT
L
Flag
2691 tb l 13
Inputs Outputs
Function
CE
L
CE
R
A
0L
-A
10L
A
0R
-A
10R
BUSY
L
(1)
BUSY
R
(1)
XXNO MATCH H H Normal
HX MATCH H H Normal
XH MATCH H H Normal
L L MATCH (2) (2) Write Inhibit
(3)
2691 tbl 14
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
16
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic, one
master part is used to decide which side of the SRAM array will receive
a BUSY indication, and to output that indication. Any number of slaves to
be addressed in the same address range as the master, use the BUSY
signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs
the BUSY pin is an output if the part is Master (IDT71321), and the BUSY
pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Functional Description
The IDT71321/IDT71421 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT71321/IDT71421 has an automatic
power down feature controlled by CE. The CE controls on-chip power
down circuitry that permits the respective port to go into a standby mode
when not selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), where a write is defined as the CER = R/WR = VIL, per Truth Table
II. The left port clears the interrupt by accessing address location 7FE when
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag (INTR) is asserted when the left port writes to memory location 7FF
(HEX) and to clear the interrupt flag (INTR), the right port must access the
memory location 7FF. The message (8 bits) at 7FE or 7FF is user-defined,
since it is an addressable SRAM location. If the interrupt function is not used,
address locations 7FE and 7FF are not used as mail boxes, but as part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a busy indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. In slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT71321 (Master) are open drain type
outputs and require open drain resistors to operate. If these SRAMs are
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
2691 drw 16
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
MASTER
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
SLAVE
Dual Port
SRAM
BUSY
L
BUSY
R
CE
BUSY
L
BUSY
R
DECODER
5V 5V
270Ω
2
70Ω
,
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
17
Ordering Information
NOTES:
1. Contact your sales office for industrial temperature range availability in other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
XXXX
Device Type A 999 AA
Power Speed Package Process/
Temperature
Range
71321
71421
16K (2K x 8-Bit) MASTER Dual-Port SRAM
w/ Interrupt
16K (2K x 8-Bit) SLAVE Dual-Port SRAM
w/ Interrupt
Speed in nanoseconds
2691 drw 17
BLANK
I
(1)
J
PF
TF
20
25
35
55
LA
SA
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Low Power
Standard Power
Commercial Only
Commercial & Industrial
Commercial Only
Commercial & Industrial
,
A
GGreen
(2)
Datasheet Document History
03/24/99: Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Pages 2 and 3 Added additional notes to pin configurations
06/07/99: Changed drawing format
11/10/99: Replaced IDT logo
08/23/01: Page 3 Increased storage temperature parameters
Clarified TA parameter
Page 4 DC Electrical parameters–changed wording from "open" to "disabled"
Page 16 Fixed part numbers in "Width Expansion" paragraph
Changed ±500mV to 0mV in notes
Page 4 Industrial temperature range offering added to DC Electrical Characteristisc for 25ns and removed for
35ns
Page 7 and 9 Industrial temperature range added to AC Electrical Characteristics for 25ns
Page 17 Industrial offering removed for 35ns ordering information
01/17/06: Page 1 Added green availability to features
Page 17 Added green indicator to ordering information
Page 1 & 17 Replaced old IDTTM with new IDT TM logo
08/25/06: Page 14 Changed INT"A" to INT"B" in the CLEAR INT drawing in the Timing Waveform of Interrupt Mode
10/29/08: Page 17 Removed "IDT" from orderable part number
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794
San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com
www.idt.com
