General Description
The MAX2150 is a complete wideband direct upconver-
sion quadrature modulator IC incorporating a 28-bit
sigma-delta fractional-N synthesizer. The device is tar-
geted for applications in the 700MHz to 2300MHz fre-
quency range.
The super-high-resolution sigma-delta fractional-N syn-
thesizer is capable of better than 50mHz resolution
when used with a 10MHz reference. Other features:
fully differential I/Q modulation inputs, an internal LO
buffer, and a 50Ωwideband output driver amplifier.
A standard 3-wire interface is provided for synthesizer
programming and overall device configuration. An on-
chip low-noise crystal oscillator amplifier is also includ-
ed and can be configured as a buffer when an external
reference oscillator is used.
The device typically achieves 34dBc of carrier and side-
band suppression at a -1dBm output level. The wide-
band, internally matched RF output can also
be disabled while the synthesizer and 3-wire bus remain
powered up for continuous programming.
The device consumes 72mA from a single +3.0V sup-
ply and is packaged in an ultra-compact 28-pin QFN
package (5mm ✕5mm) with an exposed pad.
Applications
Wireless Broadband
Satellite Uplink
LMDS
Wireless Base Station
Features
♦Single Voltage Supply (2.7V to 3.6V)
♦75MHz 3dB I/Q Input Bandwidth
♦Wideband 50Ω RF Output: 700MHz to 2300MHz
♦Ultra-Fine Frequency Resolution: 100mHz
♦High Reference Frequency for Fast-Switching
Applications
♦Ultra-Low Phase Noise
♦Low Spurious and Reference Emissions
♦-1dBm RMS Output Power
♦60dB RF Muting Control
♦34dBc Typical Carrier Suppression
♦34dBc Typical Sideband Suppression
♦Software- and Hardware-Controlled Shutdown
Modes
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
________________________________________________________________
Maxim Integrated Products
1
RFOUT
N.C.
N.C.
TXEN
VCC_PA
VCC_RF
4
1
2
5
6
7
28 27 26 25 24 23 22
15
16
17
18
19
20
21
MAX2150
∑ Δ – MOD
90
0
PROGRAMMING
AND CONTROL
CLK DATA SYNEN
QFN
OSCIN VCC_XTAL
I+ Q+I- Q- BUFOUTBUFEN
LO+
LO-
VCC_LO
VCC_D
VCC_A
CHP
VCC_CHP
LOCK
VCC_SD
1/N
1/R
PFD CHP
EN SHDN
8910 11 12 13 14
3
Pin Configuration/
Functional Diagram
Ordering Information
19-2389; Rev 4; 6/08
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART TEMP RANGE PIN-PACKAGE
MAX2150ETI -40°C to +85°C 28 TQFN-EP*
MAX2150ETI+ -40°C to +85°C 28 TQFN-EP*
*
EP = Exposed paddle.
+
Denotes lead-free package.
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.3V to +6.0V
RF Signals: LO+, LO-, OSCIN ........................................+10dBm
I+ to I-, Q+ to Q-.......................................................................2V
LO+, LO-, I+, I-, Q+, Q-, BUFEN, TXEN, CLK, DATA,
EN, SYNEN, OSCIN, OSCOUT, BUFOUT, CHP,
SHDN, LOCK, VCC_CP to GND..............-0.3V to (VCC + 0.3V)
Digital Input Current .........................................................±10mA
Short-Circuit Duration RFOUT, BUFOUT, OSCOUT,
Lock, CHP...........................................................................10s
Continuous Power Dissipation
28-Pin TQFN (TA = +70°C)..................................................2W
(derate 28.5mW/°C above +70°C)
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature Range ..........................................+150°C
Storage Temperature.........................................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
DC ELECTRICAL CHARACTERISTICS
(MAX2150 EV kit. VCC = +2.7V to +3.6V, GND = 0V, SHDN = PLLEN = TXEN = high, BUFEN= low. No AC input signals. RFOUT and
BUFOUT output ports are terminated in 50Ω. TA= -40°C to +85°C. Typical values are at VCC = +3V, TA= +25°C, unless otherwise
noted.) (Note 1)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SUPPLY
Supply Voltage 2.7 3 3.6 V
TX mode, SHDN = PLLEN = TXEN = high
BUFEN = low 72 107
SYNTH mode, SHDN = PLLEN = high, TXEN =
BUFEN = low 25 38
Supply Current
MOD mode, SHDN = TXEN = high, SYNEN =
BUFEN = low 46 69
mA
LO Buffer Supply Current Additional current in all modes for BUFEN = high 3.3 5.5 mA
HW_SHDN mode, SHDN = low 0.3 600
Shutdown Supply Current SW_SHDN mode, PWDN bit at logic low 35 600 µA
CONTROL INPUT/OUTPUTS (SHDN, TXEN, SYNEN, BUFEN)
Input Logic High 2V
Input Logic Low 0.5 V
Input Logic High Current 1µA
Input Logic Low Current -1 µA
Lock Detect High (Locked) 2 V
Lock D etect Low ( U nl ocked ) 0.5 V
Power-Up Time MOD mode 25 µs
Power-Down Time MOD mode 1 µs
3-WIRE CONTROL INPUT (CLK, DATA, EN)
Input Logic High VCC -
0.5 V
Input Logic Low 0.5 V
Input Logic High Current 1µA
Input Logic Low Current -1 µA
CAUTION! ESD SENSITIVE DEVICE
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
MODULATION INPUT
BW (-1dB) 26
I/Q Input Bandwidth BW (-3dB) 75 MHz
I/Q Differential Input Level Assumes a sine-wave input to achieve the RFOUT output
power specified below 1V
P-P
I/Q DC Input Resistance 200 kΩ
I/Q Common-Mode Input Range (Note 2) 1.5 1.6 1.7 V
RF OUTPUT
Frequency Range 700 2300 MHz
TXEN = high, fRF = 1750MHz -7 -1
Output Power TXEN = low, fRF = 1750MHz -60 dBm
Output 1dB Compression Point 1 dBm
Output IP3 14 dBm
Carrier Suppression fRF = 1750MHz 34 dBc
Sideband Suppression fLO - fI/Q, fRF = 1750MHz 25 34 dBc
RF Output Noise Floor fOFFSET > 40MHz (Note 2) -148 -143 dBm/Hz
Output Return Loss (Note 3) -9 dB
LO INPUT/OUTPUT
Frequency Range 700 2300 MHz
LO Input Power (Note 2) -12 -10 -7 dBm
LO Input Return Loss fLO =2000MHz -15 dB
LO Buffer Output Level BUFEN = high (Note 2) -14 -9.5 dBm
SIGMA-DELTA FRACTIONAL-N SYNTHESIZER
SYSTEM REQUIREMENTS
Frequency Range (Note 2) 700 2300 MHz
Phase-Detector Input-Referred
Phase Noise Floor fCOMP = fREF = 20MHz, CP0 = CP1 = CPX = 1 (Note 4) -138 dBc/Hz
In-Loop Spurious Emissions fLO = 1740.005MHz, fCOMP = fREF = 20MHz, CP0 = CP1
= CPX = 1 (Note 5) -40 dBc
MAIN DIVIDER AND PHASE DETECTOR
Minimum Fractional-N Step Size fCOMP/
228
Phase-Detector Comparison
Frequency 20 30 MHz
Maximum N Division 251
Minimum N Division 35
AC ELECTRICAL CHARACTERISTICS
(MAX2150 EV kit. VCC = +2.7V to +3.6V, SHDN = PLLEN = TXEN = high, BUFEN =low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P.
I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT
output ports are terminated in 50Ωloads. fLO =1750MHz, PLO = -10dBm, typical values are at VCC = +3V, TA= +25°C, unless other-
wise noted.) (Note 1)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
4 _______________________________________________________________________________________
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFERENCE OSCILLATOR AND DIVIDER
Input Frequency Range 10 50 MHz
AC-Coupled Input Sensitivity AC-coupled, single ended (Note 2) 0.4 2.3 VP-P
Reference Division Ratio (Notes 2, 6) 1 4
CHARGE-PUMP OUTPUT
CPX = 0 0.12 0.17 0.22
CP1, CP0 = 00 CPX = 1 0.23 0.34 0.44
CPX = 0 0.23 0.35 0.46
CP1, CP0 = 01 CPX = 1 0.47 0.67 0.88
CPX = 0 0.36 0.52 0.68
CP1, CP0 = 10 CPX = 1 0.70 1.00 1.30
CPX = 0 0.48 0.69 0.90
Charge-Pump Current (Note 7)
CP1, CP0 = 11 CPX = 1 0.91 1.31 1.70
mA
Charge-Pump Voltage
Compliance Sink/source currents match within ±5% 0.5 VCC -
0.5 V
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2150 EV kit. VCC = +2.7V to +3.6V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P.
I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT
output ports are terminated in 50Ωloads. fLO =1750MHz, PLO = -10dBm, typical values are at VCC = +3V, TA= +25°C, unless other-
wise noted.) (Note 1)
Note 1: Parameters are guaranteed by production testing at +25°C and +85°C. Minimum and maximum values over the tempera-
ture and supply voltage range are guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
Note 3: Measured with MAX2150 EV kit.
Note 4: Measured with an on-chip crystal oscillator.
Note 5: In-loop spurious emissions occur when synthesizing a frequency at an integer multiple of the comparison frequency with
fractional offset within the PLL loop BW.
Note 6: If an on-chip oscillator is used, a fundamental tone crystal is needed.
Note 7: Minimum and maximum values at CPX = 1 are guaranteed by production testing. Values at CPX = 0 are guaranteed by
design and characterization.
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
_______________________________________________________________________________________
5
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
MAX2150 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.33.0
20
40
60
80 +85°C
+25°C
-40°C
TX MODE
100
0
2.7 3.6
MODULATION OUTPUT POWER
vs. FREQUENCY
MAX2150 toc02
FREQUENCY (MHz)
MODULATION OUTPUT POWER (dBm)
190015001100
-10
-8
-6
-4
-2
0
2
4
-12
700 2300
+85°C
+25°C
-40°C
TXEN = HIGH
MODULATION OUTPUT POWER
vs. FREQUENCY
MAX2150 toc03
FREQUENCY (MHz)
MODULATION OUTPUT POWER (dBm)
190015001100
-67
-64
-61
-58
-55
-70
700 2300
+85°C
+25°C
-40°C
TXEN = LOW
OUTPUT POWER vs. LO POWER
MAX2150 toc04
LO POWER (dBm)
OUTPUT POWER (dBm)
11108 9
-1.9
-1.8
-1.7
-1.6
-1.5
-1.4
-1.3
-1.2
-1.1
-1.0
-2.0
712
CARRIER AND SIDEBAND
SUPPRESSIONS vs. LO POWER
MAX2150 toc05
LO POWER (dBm)
CARRIER AND SIDEBAND SUPPRESSIONS (dB)
111098
33
34
35
36
37
38
32
712
SIDEBAND SUPPRESSION
CARRIER SUPPRESSION
MODULATOR OUTPUT POWER
vs. I/Q INPUT LEVEL
MAX2150 toc06
I/Q INPUT LEVEL (mV)
MODULATOR OUTPUT POWER (dBm)
140012001000800600400200
-20
-16
-12
-8
-4
0
4
-24
0
-40°C
+25°C
+85°C
Typical Operating Characteristics
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ sin-
gle-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports
are terminated in 50Ωloads. fLO =1750MHz, PLO = -10dBm, TA= +25°C, unless otherwise noted.)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
6 _______________________________________________________________________________________
MODULATOR OUTPUT IP3 vs. VCC
MAX2150 toc07
VCC (V)
MODULATOR OUTPUT IP3 (dBm)
3.33.0
11
12
13
14
15
16
10
2.7 3.6
-40°C
+25°C
+85°C
MODULATOR OUTPUT P1dB vs. VCC
MAX2150 toc08
VCC (V)
MODULATOR OUTPUT P1dB (dBm)
3.33.0
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
-1.0
2.7 3.6
-40°C
+25°C
+85°C
LO PORT INPUT RETURN LOSS
vs. FREQUENCY
MAX2150 toc09
FREQUENCY (MHz)
LO PORT RETURN LOSS (dB)
190015001100
-25
-20
-15
-10
-5
0
-30
700 2300
BUFOUT PORT RETURN LOSS
vs. FREQUENCY
MAX2150 toc10
FREQUENCY (MHz)
BUFOUT PORT RETURN LOSS (dB)
190015001100
-25
-20
-15
-10
-5
0
-30
700 2300
LO BUFFER OUTPUT POWER
vs. FREQUENCY
MAX2150 toc11
FREQUENCY (MHz)
LO BUFFER OUTPUT POWER (dBm)
190015001100
-13
-12
-11
-10
-9
-8
-7
-6
-5
-4
-14
700 2300
-40°C
+25°C
+85°C
BUFEN = HIGH
LO BUFFER OUTPUT POWER
vs. FREQUENCY
MAX2150 toc12
FREQUENCY (MHz)
LO BUFFER OUTPUT POWER (dBm)
190015001100
-52
-49
-46
-43
-40
-55
700 2300
-40°C
+25°C
+85°C
BUFEN = LOW
Typical Operating Characteristics (continued)
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+
single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output
ports are terminated in 50Ωloads. fLO =1750MHz, PLO = -10dBm, TA= +25°C, unless otherwise noted.)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
_______________________________________________________________________________________
7
OSCIN PORT SENSITIVITY
(SYNTHESIZER) vs. FREQUENCY
MAX2150 toc13
FREQUENCY (MHz)
OSCIN PORT SENSITIVITY (V)
45403530252015
1
2
3
4
5
6
0
0.10
0.20
0.30
0.40
0.50
0.60
0
10 50
-40°C
-40°C
+25°C
+25°C
+85°C
+85°C
OSCIN IMPEDANCE vs. FREQUENCY
MAX2150 toc14
FREQUENCY (MHz)
OSCIN PORT IMPEDANCE (Ω)
454030 3520 2515
-900
-800
-700
-600
-500
-400
-300
-200
-100
0
-1000
10 50
IMAGINARY
REAL
SYNTHESIZER PHASE NOISE
MAX2150 toc15
SPAN = 20kHzCENTER = 1.75MHz
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-8.5dBm
N/C = -99dBc/Hz
I/Q MODULATOR OUTPUT SPURS
MAX2150 toc16
SPAN = 2 MHzCENTER = 1.75 GHz
-100
-90
-80
-70
-60
1 AVG
-50
-40
-30
-20
-10
0
CARRIER
SUPPRESSION
-34dBc SIDEBAND
SUPPRESSION
-36dBc
Typical Operating Characteristics (continued)
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+
single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output
ports are terminated in 50Ωloads. fLO =1750MHz, PLO = -10dBm, TA= +25°C, unless otherwise noted.)
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
8 _______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 TXEN Modulator Enable Input. Set TXEN low to inhibit the RF and modulator circuits. This mode can be used
for quiet frequency synthesis.
2 VCC_PA Supply Voltage Input for RFOUT Output Driver Circuits. Bypass as close to the pin as possible. The
bypass capacitor should not share ground vias with other branches.
3 RFOUT Modulator RF Output. This is a wideband, internally matched 50Ω output. A DC-blocking capacitor is
required.
4, 5 N.C. Do Not Connect. (These pins must be left floating.)
6 LOCK Lock Status of the PLL. A static logic-level high indicates that the PLL is in the locked condition.
7 VCC_SD Supply Voltage Input for Sigma-Delta Modulator Circuits. Bypass as close to the pin as possible. The
bypass capacitor should not share ground vias with other branches.
8, 9, 10 CLK, DATA,
EN
Input Pins from 3-Wire Serial Bus. An RC lowpass filter on each of these pins can be used to reduce
digital noise.
11 SHDN Shutdown Control. Set SHDN low to disable all internal circuits for lowest power consumption. An RC
lowpass filter can be used to reduce digital noise.
12 SYNEN Synthesizer Enable Input. Set SYNTH low to disable the internal frequency synthesizer. An RC lowpass
filter can be used to reduce digital noise.
13 OSCIN
Reference Oscillator Input. Connect a parallel, resonant, fundamental-tone crystal between this pin and
ground to facilitate a crystal oscillator circuit. For applications with an external reference oscillator, the
OSCIN input can be driven through a large-value series capacitor.
14 VCC_XTAL Supply Voltage Input for Crystal Oscillator. Bypass as close to the pin as possible. The bypass capacitor
should not share ground vias with other branches.
15 VCC_CHP Supply Voltage Input for Charge Pump. Bypass as close to the pin as possible. The bypass capacitor
should not share ground vias with other branches.
16 CHP
High-Impedance Charge-Pump Output. Connect to the tune input of the VCO through the PLL loop filter.
Keep the line from this pin to the tune input as short as possible to prevent spurious pickup, and
connect the loop filter as close to the tune input as possible.
17 VCC_A Supply Voltage Input for PLL. Bypass as close to the pin as possible. The bypass capacitor should not
share ground vias with other branches.
18 VCC_D Supply Voltage Input for PLL. Bypass as close to the pin as possible. The bypass capacitor should not
share ground vias with other branches.
19 VCC_LO Supply Voltage Input for Internal LO Circuits. Bypass as close to the pin as possible. The bypass
capacitor should not share ground vias with other branches.
20, 21 LO-, LO+ Differential Local-Oscillator Input. These inputs require DC-blocking capacitors. The LO can be applied
with a single-ended input to the LO+/LO- pin. In this mode, the other pin should be AC-grounded.
22 BUFOUT Buffered LO Output. Internally matched to 50Ω, requires a DC-blocking capacitor.
23 BUFEN LO Output Buffer Amplifier Enable. Set BUFEN high to enable the on-chip output LO buffer for driving
external circuits. An RC lowpass filter can be used to reduce digital noise.
24, 25 Q-, Q+ Differential Q-Channel Baseband Inputs to the Modulator. These pins connect directly to the bases of
a differential pair and require an external common-mode bias voltage of 1.6V.
Detailed Description
Internally, the MAX2150 includes a broadband I/Q
modulator, internally matched broadband output driver
amplifier, fine-resolution fractional-N frequency synthe-
sizer, an LO buffer amplifier, and an on-chip low-noise
crystal oscillator circuit.
A simple 3-wire interface is provided for synthesizer
programming and device configuration and control.
Independent hardware and software power-down con-
trol of the I/Q modulator, frequency synthesizer, and LO
buffer amplifier is provided, as well as the ability to shut
down the entire chip.
I/Q Modulator
The MAX2150 modulator is composed of a pair of
matched double-balanced mixers, a broadband pas-
sive LO quadrature generator, and a summing amplifi-
er. The mixers accept differential I/Q baseband signals
that directly modulate the internal 0°and 90°LO sig-
nals applied to the I/Q mixers. An external LO source
drives an internal LO quadrature generator that shifts
the phase of the LO signal applied to the Q mixer by
90°relative to the LO signal applied to the I-channel
mixer. The modulated output of the I/Q mixers is
summed together, and the undesired sideband is sup-
pressed.
The I+, I-, Q+, and Q- input ports feature high-linearity
buffer amplifiers with a typical -3dB bandwidth of
75MHz and accept differential input voltages up to
1VP-P. The ports require external biasing and have an
input common-mode requirement of 1.6V. For single-
ended operation, bypass the I and Q ports to ground.
See the
Typical Application Circuit
for recommended
component values.
The broadband output driver amplifier is matched on
chip across the entire operating frequency range and
requires an output DC-blocking capacitor. For optimum
performance, the output match can be improved with
simple L-section and/or PI-section matching networks.
Always ensure that DC blocking is provided, because
internal bias voltages are present at this output.
The modulator can be shut down with both hardware
(pin 1) and software (TE bit). This mode is useful for
quiet synthesizer programming or to mute the RF out-
put signal. The hardware pin and software bits must be
set to logic-1 to enable the modulator. If the hardware
pin or software bit is set to logic-0, or if both are set to
logic-0, the modulator is disabled.
LO Buffer Amplifier
The broadband buffer amplifier output is internally
matched and requires a DC-blocking capacitor to iso-
late on-chip bias voltages. Power-down of the LO buffer
can be controlled by both BUFEN (pin 23), as well as
BUFEN by software by setting the BUFEN (BE) bit
through the 3-wire interface. The hardware pin and the
software bit must be a logic-1 to enable the buffer. If
the hardware or software bit is set to logic-0, the LO
buffer is disabled.
Frequency Synthesizer
The MAX2150 features an internal 28-bit sigma-delta
frequency synthesizer. This architecture enables the
use of very high (30MHz) comparison frequencies,
which significantly reduces the in-loop phase noise as
a result of reduced division ratios. The high comparison
frequency also allows significantly increased PLL
bandwidths for very fast switching speed applications.
Divider Programming
The MAX2150 frequency programming is determined
as follows. The overall division ratio (D) has an integer
value (N), as well as a fractional component (F):
D = N.F = N +F / 228
The N and F values are encoded as straight binary
numbers. Determination of these values is illustrated by
the following example:
FLO = 1721.125MHz, FCOMP = 20MHz
Then:
D = 1721.125 / 20 = 86.05625
Therefore:
N = 86 and F = 0.05625 x 228 = 15,099,494
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
_______________________________________________________________________________________ 9
Pin Description (continued)
PIN NAME FUNCTION
26, 27 I-, I+ Differential I-Channel Baseband Inputs to the Modulator. These pins connect directly to the bases of a
differential pair and require an external common-mode bias voltage of 1.6V.
28 VCC_RF Supply Voltage Input for RF Circuits. Bypass as close to pin as possible. The bypass capacitor should
not share ground vias with other branches.
— Exposed pad Ground
MAX2150
Converting each to binary representation results in the
following:
N register = 86 = 0101,0110
F register value =
0000,1110,0110,0110,0110,0110,0110
The F-register value is then split between an upper 14
bits and a lower 14 bits as follows:
Upper 14 bits + address 00 = 0000,1110,0110,0100
Lower 14 bits + address 01 = 1001,1001,1001,1001
Synthesizer Shutdown
The synthesizer can be disabled by setting SYNEN (pin
12) to a logic low. This mode is useful when an external
frequency synthesizer is employed.
Applications Information
Serial Interface and Register Definition
3-Wire Interface and Registers
The MAX2150 is programmed through a simple
3-wire (CLK, DATA, EN) interface. The programming
data is contained within 16-bit words loaded into four
unique address locations. Each location contains pro-
gramming information for setting operational modes
and device configuration. Two words (address 00, 01)
control the fractional divide number in the sigma-delta
synthesizer. The third word (address 10) sets the inte-
ger divide value, reference divide value, charge-pump
current, and charge-pump compensation DAC settings.
The fourth and final word (address 11) contains various
device configuration registers and test registers, as
well as additional charge-pump compensation regis-
ters. See Tables 1 through 11 for details.
3-Wire Interface Timing Diagram
Figure 1 shows the programming logic. The 16-bit shift
register is programmed by clocking in data at the rising
edge of CLK. Pulling enable low allows data to be
clocked into the shift register; pulling enable high loads
the register addressed.
Fractional Spurs
When synthesizing a frequency that is an integer multi-
ple of the reference divider and having a fractional off-
set with a value less than the PLL filter bandwidth,
fractional spurs can be observed at a typical level of
-40dBc. For example, to synthesize 1640.005MHz
when using a 20MHz reference and a PLL bandwidth of
25kHz, spurious products offset from the LO by 5kHz
can be observed. The 1640MHz is an integer multiple
of 20MHz, and the fractional offset of 5kHz is within the
PLL bandwidth.
It is possible to avoid the above-mentioned spurious
products by using two reference oscillators with slightly
offset frequencies or by using a higher reference fre-
quency and changing the comparison frequency of the
reference divider.
Crystal Oscillator
The MAX2150 includes a simple-to-use on-chip low-
noise reference oscillator circuit. The oscillator is
formed by connecting a fundamental mode parallel res-
onant crystal from OSCIN to ground. The oscillator cir-
cuit is useful from 10MHz to 50MHz.
The phase noise of the MAX2150 can be improved by
using a precision high-frequency external reference
oscillator (TCXO). The external oscillator is connected
through a DC-blocking capacitor directly to the OSCIN
pin.
Layout Considerations
A properly designed PC board is an essential part of
any RF circuit. A ground plane is essential. Keep RF
signal lines as short as possible to reduce losses, radi-
ation, and inductance. The exposed pad on the under-
side of the MAX2150 must be adequately grounded by
ensuring that the exposed paddle of the device pack-
age is soldered evenly to the board ground plane. Use
multiple, low-inductance vias to ground the exposed
paddle.
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
10 ______________________________________________________________________________________
tCS tCH
tCWL
tCWH
DATA
CLK
EN
tES
B19 (MSB) B18 B0 A3 A1 A0 (LSB) tCS > 50ns
tCH > 10ns
tCWH > 50ns
tES > 50ns
tCWL > 50ns
tEW > 50ns
tEW
Figure 1. 3-Wire Interface Timing Diagram
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
______________________________________________________________________________________ 11
R1 R0 REFERENCE DIVIDE VALUE
00 1
01 2
10 3
11 4
Table 2. Reference Divider
N7 N6 N5 N4 N3 N2 N1 N0 INTEGER DIVIDE VALUE
0 0100011 35
0 0100100 36
— ——————— —
1 1111010 250
1 1111011 251
Table 3. Integer Divider-N*
F27 F26 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14
00000000000000
00000000000000
——————————————
11111111111111
Table 4. Fractional Divider-F (Upper 14 Bits)
F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 INTEGER DIVIDE
VALUE
00000000000000 1
00000000000001 2
—————————————— —
11111111111110 268435454
11111111111111 268435455
Table 5. Fractional Divider-F (Lower 14 Bits)
*N divider is limited to 35 < N < 251.
Table 1. Register Tables
MSB SHIFT REGISTER DATA LSB ADDRESS
Upper (MSBs) Fractional Divider Value (F) 14 Bits (Default = 8192, 10000000000000) Address
27 26 25 24 23 22 21 20 19 18 17 16 15 14 0 0
Lower (LSBs) Fractional Divider Value (F)14 Bits (Default 0 DEC, 00000000000000 Address
13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1
R Divider
Default = 00
CP Bleed
Default = 00
CP Current
Default = 11
Integer Divide Value (N) 8 Bits
Default = 177 DEC Address
R1 R0 LIN1 LIN0 CP1 CP0 7 6 5 4 3 2 1 0 1 0
Reset Delay
Default = 00
Test Registers 6 Bits
Default = 0 DEC
Control Register 6 Bits
Default = 15 DEC Address
BL1 BL0 T5 T4 T3 T2 T1 T0 INT PD TE BE XX CPX 1 1
MAX2150
Power-Supply (VCC) Bypassing
Proper voltage-supply bypassing is essential to reduce
the spurious emissions mentioned above. It is recom-
mended that each VCC pin be bypassed independently
and share no common vias with any other ground con-
nection. See the
Typical Operating Circuit
for suggest-
ed bypass component values.
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
12 ______________________________________________________________________________________
BIT ID BIT
NAME
PWR-UP
STATE
BIT LOCATION
0 = LSB FUNCTION
CPX CP_MULT 1 0
A logic high doubles the charge pump current selected through registers
CP1 and CP0. Logic low sets the charge-pump current to the value
selected by registers CP1 and CP0.
XX XX XX 1 Unused.
BE BUFEN 1 2 High enables the VCO buffer. Low disables this output.
TE TXEN 1 3 Low enables SW_MUTE mode, which shuts down the RF circuits while
leaving the 3-wire interface, register, and PLL circuits active.
PD PWDN 0 4 Low enables register-based shutdown. This mode shuts down all circuits
except the 3-wire interface and internal registers.
INT INT_MODE 0 5 Logic high disables the sigma-delta modulator. Logic low enables the
sigma-delta modulator for normal operation.
Table 6. Control Register
HW PINS SOFTWARE CONTROL
BITS
MODE
SHDN TXEN SYNEN BUFEN PWDN TXEN BUFEN
DESCRIPTION
TX H H H H/L H H H/L All circuits active.
MOD H H L H/L H H H/L
Modulator circuits active. Synthesizer
blocks disabled. Mode is used with external
PLL circuit.
SYNTH H L H H/L H X H/L
Serial interface and synthesizer blocks
active. RF and modulator blocks disabled.
Mode is used to gate RF ON/OFF with
external logic control.
SW_MUTE H H H H/L H L H/L
Serial interface and synthesizer blocks all
active. Modulator blocks disabled. Mode is
used to gate RF ON/OFF with software
control.
HW_SHDN L X X X X X X All circuits disabled. Lowest current mode
of operation.
SW_SHDN H X X X L X X
Serial interface and registers active, all
other circuits inactive regardless of the
state of the HW pins with the exception of
HW_SHDN.
Table 7. Device Modes
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
______________________________________________________________________________________ 13
TXEN
PIN BIT
TX MODE
0 0 TX off
0 1 TX off
1 0 TX off
1 1 TX enabled
Table 8. TXEN Pin and Software Bit
Definitions
BUFEN
PIN BIT
BUF MODE
0 0 Buffer off
0 1 Buffer off
1 0 Buffer off
1 1 Buffer on
Table 11. BUFEN Pin and Software Bit
Definitions
CPX CP1 CP0 ICP (µA)
0 0 0 170
0 0 1 350
0 1 0 520
0 1 1 690
1 0 0 340
1 0 1 670
1 1 0 1000
1 1 1 1310
Table 9. Charge-Pump Registers
TEST MODE T5 T4 T3 T2 T1 T0 TEST PIN
Normal
Operating
Mode
000000 —
Charge Pump
Forced to
Source Icp
000001 CP
Charge Pump
Forced to Sink
Icp
000010 CP
Reference
Divider Output 0 1 0 0 0 0 Lock
Main Divider
Output 0 1 1 0 0 0 Lock
Table 10. Test Register Definition
(Default 0 Dec)*
*
All other logic states are undefined.
Chip Information
TRANSISTOR COUNT: 16,321
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP T2855-3 21-0140
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
14 ______________________________________________________________________________________
MAX2150
VCC
VCC
VCC
VCC
VCC
GND
J6
J7
C25
1μF
C31
0.1μF
R29
OPEN
C3
0.1μF
C17
100pF
C18
0.1μF
2VCC_PA
1TXEN
3RFOUT
4TEST2
C16
OPEN
C15
OPEN
R13
0Ω
J8
RFOUT
J16
5TEST1
J17
7VCC_SD
VCCSD
6LOCK
LOCK
J20
VCC
VCC
C14
100pF
C27
1.0μFCLK
8
DATA
9
EN
10
J10–5
J10–9
SHDN
11
J10–13
SYNEN
12
OSCIN VCC_XTAL
13 14
15
J10–17
J10–19
J10–15
J10–7
J10–11
J10–3
J10–1
J10–4
J10–8
J10–12
J10–16
J10–18
J10–20
J10–14
J10–6
J10–10
J10–2
C37
0.1μF
C36
0.1μF
L1
OPEN
EN
JUMP_PAD
LOCK
CLK
ENn
DATA
FILTVCC
SHDNn
TXEN
SYNEN
VCOSEL
SHDN
C30
0.1μFJ18 REFL In
R18
0ΩY1
C13
100pF
C21
0.1μF
VCC
VCC
VCC
VCC_VCO
C9
100pF
C19
0.1μF
VCC_CHP
16
CHP
17
VCC_A
C22
6800pF
C24
680pF
C26
470pF
C35
100pF
C34
0.1μF
R23
245Ω
C23
.068μF
R24
1.1kΩ
R25
1.1kΩ
R35
OPEN
TUNEOUT
VTUNE_OUT
1
2
3
6
5
4
VT
GND
VCC
VSW
GND
OUT
GND
GND
7
8
J5
J11
J19
GND
VCCVCO
U2 VC3R0A230967/
1750B350FUJI
C10
100pF
VCC
18
VCC_D
C4
100pF
VCC
19
VCC_LO
20
LO-
C12
100pF
C11
100pF
C8
22pF
J15
LOn
21
LO+
C7
OPEN
J14
LO
C5
OPEN
C6
OPEN
J13
BUFOUT
C32
0.1μF
C33
0.1μF
C20
0.1μF
R34
3.3kΩ
R33
3.3kΩ
R32
3.3kΩ
R31
3.3kΩ
C28
0.1μF
DCIN
R1
OPEN
R2
OPEN
R3
OPEN
R4
OPEN
J1
31-5239-52RFX
C50
0.1μF
J2
31-5239-52RFX
C52
0.1μF
C2
100pF
VCC_RF
28
I+
27
I-
26
Q+
25
Q-
24
BUFEN
23
BUFOUT
22
IIN QNQ
C1
0.1μF
BUFEN
VCC
R12
0Ω
U1
Typical Operating Circuit
MAX2150
Wideband I/Q Modulator with Sigma-Delta
Fractional-N Synthesizer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
15
© 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
4 6/08 Updated table in Package Information 13
