CY25702
Document #: 38-07721 Rev. *C Page 2 of 6
Functional Description
The CY25702 is a programmable high-frequency Crystal
Oscillator (XO) that uses a Cypress proprietary PLL to
synthesize the frequency of the embedded input crystal.
The CY25702 uses a programmable configuration memory
array to synthesize output frequency. The frequency CLK
output can be programmed from 1 MHz to 166 MHz.
The CY25702 is available in a 4-pin ceramic SMD package
with an operating temperature range of –40 to 85°C.
Programming Description
Field/Fact ory-Programmable CY25 702
Field/Factory programming is available for samples and
manufacturing by Cypress and its distributors. All requests
must be submitted to the local Cypress Field Application
Engineer (F AE) or sales representative. Once the request has
been processed, you will receive a new part number , samples,
and data sheet with the programmed values. This part number
will be used for additional sample requests and production
orders.
Additional information on the CY25702 can be obtained from
the Cypress web site at www.cypress.com.
Output Frequency, CLK Output (CLK, pin 3)
The frequency at the CLK output is produced by synthe s izing
the embedded crystal oscillator frequency input. The range of
the synthesized clock is from 1 MHz to 166 MHz.
Output Enable or Power Down (OE/PD#, pin 1)
Pin 1 can be programmed as either output enable (OE) or
Power Down (PD#).
Absolute Maximum Rating
Supply Voltage (VDD)......................... ... ..........–0.5V to +7.0V
DC Input Voltage .............. ... ..................–0.5V to V DD + 0.5V
Storag e Temperature (Non-condensing) ...... –55°C to 100°C
Junction Temperature.................................. –40°C to 125°C
Dat a Re tention @ T j = 12 5°C....... .. ... .............. ... ...> 10 years
Package Power Dissipation......................................350 mW
Pin Definition
Pin Name Description
1 OE/PD# Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.
Power Down pin: Active LOW. If PD# = 0, Power Down is enabled.
2 VSS Power supply ground.
3 CLK Clock output.
4 VDD 3.3V power supply.
Table 1. Programming Data Requirement
Pin Function Output Frequency Output Enable/Power Down
Pin Name CLK OE/PD#
Pin# 3 1
Units MHz N/A
Program Value ENTER DATA ENTER DATA
Operating Conditions
Parameter Description Min. Typ. Max. Unit
VDD Supply Voltage 3.00 3.30 3.60 V
TAAmbient Temperature (Commercial) –20 – 70 °C
TAAmbient Temperature (Industrial) –40 – 85 °C
CLOAD Max. Load Capacitance @ pin 3 – – 15 pF
FCLK CLK output frequency, CLOAD = 15 pF 1 – 166 MHz
TPU Power-up time for VDD to reach mini mum specified volt age (p ower ramp must be
monotonic) 0.05 – 500 ms