CY25702LXIZZZT - Cypress Semiconductor Corp.

Programmable High-Frequency Cryst al Oscillator (XO)

CY25702

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-07721 Rev. *C Revised December 07, 2006

Features

• Programmable High-frequency Crystal Oscillator (XO)

• Wide operating output clock frequency range of 1–166 MHz

• Integrated phase-locked loop (PLL)

• 85 ps typical cycle-to-cycle Jitter with CLK = 133 MHz

• 3.3V operation

• Output Enable and Power-down functions

• Package available in 4-Pin Ceramic LCC SMD

• Pb-free package

• Industrial Temperature from –40°C to 85°C

• For SSCG functionality refer to CY25701 data sheet

Benefits

• Internal PLL to generate up to 166 MHz output

• Suitable for most PC, consumer, and networking

applications

• Application compatibility in standard and low-power

systems

• CY25701 can be used as a direct replacement without any

PCB modification if spread spectrum clock (SSC) is required

for EMI reduction.

• In-house programming of samples and prototype quantities

is available using CY3672 programming kit and CY3724

socket adapters. Production qua ntities are available

through Cypress’s value-added distribution partners or by

using third-party programmers from BP Microsystems, HiLo

Systems, and others.

Logic Block Diagram

VDD 3

CLK

OE/PD# VSS

Pin Configuration

CY25702

4-pin Ceramic SMD

PLL

PROGRAMMABLE

CONFIGURATION OUTPUT

DIVIDERS

and

MUX

4 2

VDD VSS

OE/PD#

RFB

CXOUT

CXIN

CLK

CY25702

Document #: 38-07721 Rev. *C Page 2 of 6

Functional Description

The CY25702 is a programmable high-frequency Crystal

Oscillator (XO) that uses a Cypress proprietary PLL to

synthesize the frequency of the embedded input crystal.

The CY25702 uses a programmable configuration memory

array to synthesize output frequency. The frequency CLK

output can be programmed from 1 MHz to 166 MHz.

The CY25702 is available in a 4-pin ceramic SMD package

with an operating temperature range of –40 to 85°C.

Programming Description

Field/Fact ory-Programmable CY25 702

Field/Factory programming is available for samples and

manufacturing by Cypress and its distributors. All requests

must be submitted to the local Cypress Field Application

Engineer (F AE) or sales representative. Once the request has

been processed, you will receive a new part number , samples,

and data sheet with the programmed values. This part number

will be used for additional sample requests and production

orders.

Additional information on the CY25702 can be obtained from

the Cypress web site at www.cypress.com.

Output Frequency, CLK Output (CLK, pin 3)

The frequency at the CLK output is produced by synthe s izing

the embedded crystal oscillator frequency input. The range of

the synthesized clock is from 1 MHz to 166 MHz.

Output Enable or Power Down (OE/PD#, pin 1)

Pin 1 can be programmed as either output enable (OE) or

Power Down (PD#).

Absolute Maximum Rating

Supply Voltage (VDD)......................... ... ..........–0.5V to +7.0V

DC Input Voltage .............. ... ..................–0.5V to V DD + 0.5V

Storag e Temperature (Non-condensing) ...... –55°C to 100°C

Junction Temperature.................................. –40°C to 125°C

Dat a Re tention @ T j = 12 5°C....... .. ... .............. ... ...> 10 years

Package Power Dissipation......................................350 mW

Pin Definition

Pin Name Description

1 OE/PD# Output Enable pin: Active HIGH. If OE = 1, CLK is enabled.

Power Down pin: Active LOW. If PD# = 0, Power Down is enabled.

2 VSS Power supply ground.

3 CLK Clock output.

4 VDD 3.3V power supply.

Table 1. Programming Data Requirement

Pin Function Output Frequency Output Enable/Power Down

Pin Name CLK OE/PD#

Pin# 3 1

Units MHz N/A

Program Value ENTER DATA ENTER DATA

Operating Conditions

Parameter Description Min. Typ. Max. Unit

VDD Supply Voltage 3.00 3.30 3.60 V

TAAmbient Temperature (Commercial) –20 – 70 °C

TAAmbient Temperature (Industrial) –40 – 85 °C

CLOAD Max. Load Capacitance @ pin 3 – – 15 pF

FCLK CLK output frequency, CLOAD = 15 pF 1 – 166 MHz

TPU Power-up time for VDD to reach mini mum specified volt age (p ower ramp must be

monotonic) 0.05 – 500 ms

CY25702

Document #: 38-07721 Rev. *C Page 3 of 6

Note

1. Guaranteed by characterization, not 100% tested.

2. Jitter is configuration dep endent. Actual jitter is dependent o n output freque ncies, spread percentage, tempera ture, and output load. Fo r more informati on, refer

to the applicatio n note, “Jitt er in PLL Base d Systems: Causes, Effect s, and So lutions” availabl e at http:// www.cypress.com/clock/appnot es.html, or cont act your

local Cypress Field Application Engineer.

DC Electrical Characteristics

Parameter Description Condition Min. Typ. Max. Unit

IOH Output High Current (pin 3) VOH = VDD – 0.5, VDD = 3.3V (source) 10 12 – mA

IOL Output Low Current (pin 3) VOL = 0.5, VDD = 3.3V (sink) 10 12 – mA

VIH Input High Voltage (pin 1) CMOS levels, 70% of VDD 0.7VDD –V

DD V

VIL Input Low Voltage (pin 1) CMOS levels, 30% of VDD – – 0.3VDD V

IIH Input High Curre nt (pi n 1) Vin = VDD ––10

μA

IIL Input Low Current (pin 1) Vin = VSS ––10

μA

IOZ Output Leakage Current (pin 3) Three-state output, OE = 0 –10 – 10 μA

CIN[1] Input Capacitance (pin 1) Pin 1, or OE – 5 7 pF

IVDD Supply Current VDD = 3.3V, CLK = 1 to 166 MHz,

CLOAD = 0, OE = VDD ––50

Δf/f Initial Accuracy at Roo m Temp. TA = 25°C, 3.3V –25 – 25 ppm

Freq. Stability over Temp. Ran ge TA = –20°C to 70°C, 3.3V –25 – 25 ppm

Freq. S tability over V oltage Range 3.0 to 3.6V –12 – 12 ppm

Aging TA = 25°C, First year –5 – 5 ppm

AC Electrical Characteristics[1]

Parameter Description Condition Min. Typ. Max. Unit

DC Output Duty Cycle CLK, Measured at VDD/2 45 50 55 %

tROutput Rise Time 20%–80% of VDD, CL=15 pF – – 2.7 ns

tFOutput Fall Time 20%–80% of VDD, CL=15 pF – – 2.7 ns

TCCJ1[2] Cycle-to-Cycle Jitter CLK (Pin 3) CLK > 133 MHz, Measured at VDD/2 – 85 200 ps

25 MHz < CLK < 133 MHz, Measured at VDD/2 – 215 400 ps

CLK < 25 MHz, Measured at VDD/2 – – 500 ps

TOE1 Output Disable Time (pin1 = OE) Time from falling edge on OE to sto pped

outputs (Asynchronous) – 150 350 ns

TOE2 Output Enable Time (pin1 = OE) Time from rising edge on OE to outputs at a

valid frequency (Asynchronou s) – 150 350 ns

TLOCK PLL Lock Time Time for CLK to reach valid frequency – – 10 ms

CY25702

Document #: 38-07721 Rev. *C Page 4 of 6

Application Circuit Figure 1. Applic a tio n Circuit Diagram

0.1 µF

VDD

OE/PD# VSS

CLK

VDD

Power

CY25702

Switching Waveforms Figure 2. Duty Cycle Waveform

Figure 3. Outpu t Rise/Fall Time Waveform

Figure 4. Output En able/Disable Timing Waveforms

Cycle Timing (DC = t1A/t1B)

t1A t1B

CLK

VDD

Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)

Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)

Refer to AC Electrical Characteristics table for SR (Slew Rate) values.

CLK

VDD

TOE1

VIL

VIH

OUTPUT

ENABLE 0V

(Asynchronous) High Impedance

TOE2

CY25702

Document #: 38-07721 Rev. *C Page 5 of 6

© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic onductor Corporation assumes no resp onsibility f or the u se

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypr ess. Furtherm ore, Cypress doe s not authorize i ts

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant inju ry to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Package Drawings and Dimensions

Figure 5. 4-Lead (5.0 x3.2 mm) Ceramic LCC LZ04A

All product and company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

Part Number Package Description Product Flow

Lead-free (Pb-free)

CY25702FLXCT[3] 4-Lead Ceramic LCC SMD -Tape and Reel Comme r cial, –20° to 70°C

CY25702FLXIT[3] 4-Lead Ceramic LCC SMD -Tape and Reel Industrial, –40° to 85°C

CY25702LXCZZZT[4] 4 - Lead Ceramic LCC SMD -Tape and Reel Commercial, –20° to 70°C

CY25702LXIZZZT[4] 4-Lead Ceramic LCC SMD -Tape and Reel Industrial, –40° to 85°C

Actual Marking

[5]

X* YWW

CY25702F

Marketing Part Number (CY25702) F=Field

Programmable

YWW = Da te Code (Year & WW )

Temp

Pin 1 mark X = Pb free

L = LCC

X*zzzYWW

CY25702L

Marketing Part Number (CY25702) L = LCC

zzz = Programmable Dash Code YWW = Date Code (Year & WW)

Temp

Pin 1 mark X = Pb free

CY25702FLX* CY25702LX*

BOTTOM VIEWTOP VIEW

SIDE VIEW

5.0

3.2

0.50 1.30 Max

0.80

2.90

2.50

1.20

Dimensions in MM

General Tolerance: ± 0.15MM

Kyocera dwg ref KD-VA5G08

Package Weight ~ 0.12 grams

001-02743-*B

Notes

3. “FLX” suffix is used for products programmed in field by Cypress Distributors.

4. “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency programming data is received from the

customer.

5. Temp can be C (Commercial) or I (Industrial).

CY25702

Document #: 38-07721 Rev. *C Page 6 of 6

Document History Page

Document Title: CY25702 Programma ble High-Frequenc y Crystal Oscillator (XO)

Document Number: 38-07721

REV. ECN NO. Issue Date Orig. of

Change Description of Change

** 296081 See ECN RGL New data sheet

*A 333298 See ECN RGL Added Jitter Specifications

Corrected the Ordering Information table to match the DevMaster

*B 390406 See ECN RGL Removed CY25702FXC and CY25702XCZZZ

*C 595857 See ECN RGL Complete data sheet rewrite