MMDP-672061FV-15/883 - Atmel Corporation

Rev. E–20-Aug-01

Features

•First-in first-out dual port memory

•16384 x 9 organisation

•Fast Flag and access times: 15, 30 ns

•Wide temperature range: - 55 °C to + 125 °C

•Programmable Half Full Flag

•Fully expandable by word width or depth

•Asynchronous read/write operations

•Empty, full and half flags in single device mode

•Retransmit capability

•Bi-directional applications

•Battery back-up opera tion: 2V data retentio n

•TTL compatible

•Single 5V + 10% power supply

•QML Q and V with SMD 5962-93177

Description

The M672061F implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The E xpansio n logic allows unli mited ex pansion in wor d size and dept h with n o

timing penalties. Twin ad dres s p ointers autom ati ca ll y g ener a te in ter nal read and write

addresses, and no external address information are required for the Atmel FIFOs.

Address pointers are automatically incremented with the write pin and read pin. The 9

bits wide data are used in data communications applications where a par ity bit for

error c hecking is n eces sary. The Re trans mit pi n rese ts the Read point er to zero with-

out affecting the write pointer. This is very useful for retransmitting data when an error

is detected in the system.

Using an array of eight transistors (8 T) memory cell, the M672061F combines an

extremely low standby supply current (typ = 0.1 µA) with a fas t access time at 15 ns

over the fu ll temp erature ra nge. All versio ns offer batte ry back up data reten tion ca pa-

bility with a typical power consumption at less than 2 µW.

For military/space applications that demand superior levels of perform ance and reli-

ability the M672061F is processed according to the methods of the latest revision of

the MIL PRF 38535 (Q and V) or ESA SCC 9000.

Rad Tolerant

High Sp eed

16 x 9

Parallel FIFO +

Programmable

Flag

M672061F

Rev. E–20-Aug-01

Interface

Block Diagram

Pin Configuration

3M672061F Rev. E–20-Aug-01

Pin Names

NAMES DESCRIPTION

I0-8 Inputs

Q0-8 Outputs

WWrite Enable

RRead Enable

RS Reset

EF Empty Flag

FF Full Flag

XO/HF Expansion Out/Half-Full Flag

XI Expansion IN

FL/RT First Load/Retransmit

VCC Power Supply

GND Ground

M672061F

Rev. E–20-Aug-01

Signal Description

Data In (I0 - I8)Data inputs for 9 - bit data

Reset (RS ) Reset occur s whenever the Res et (RS) in put is taken to a low state. Reset returns both

internal read and write pointers to the first loc ation. A reset is required after power-up

before a write operation can be enabled. Both the Read Enable (R) and Wri te Enable

(W) inputs must be in the high state during the period shown in Figure 2 (i.e. tRSS before

the rising edge of RS) and should not change until tRSR after the rising edge of RS.

Otherwise , pu ls e write (or read) low du ring the r es et op erati on loa ds the Pr og ramm abl e

Half Full Flag register from the data Inputs I0-I8 (or data outputs Q0-Q8) (shown in fig-

ure 2). In these two cases the Full Flag and the Programmable Half Full Flag are

reseted to high and the Empty Flag to low.

Figure 1. Reset (no write to Programmable Half Full Flag register)

Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

Figure 2. Reset (write (read) to Programmable Half Full Flag register)

Write Enable (W)A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W) . Data is stor ed sequentially in the Ram arr ay, regardless o f any

current read operation.

5M672061F Rev. E–20-Aug-01

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be se t to low and remain in this state until the difference

between the wri te and read pointers is les s than or equ al to half of the total available

memory in the device. The Half-Full Flag (HF) is th en reset b y the risi ng edge of the

read operation.

To prev ent data o verflow, the Full Fla g (FF) will go low, inhibiti ng further write oper a-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including

any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0 -

Q8) will return to a hi gh impedan ce state unti l the next Rea d operati on. When al l the

data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance s tate. Once a valid write operation ha s been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

First Load/Retransmit

(FL/RT) This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to in dicat e that it is the first loaded (s ee Opera ting Mod es). In th e Single Dev ice

Mode, this pin a cts as the retr ans mit input. The Singl e Dev ice Mode is i nitia ted b y c on-

necting the Expan si on In (XI ) to ground.

The M6 72061F ca n be set to retran smit data when th e R etransmi t En able C ontrol ( RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the h igh state duri ng retransm it. The retran smit feat ure is intend ed for use when a

number of writes are equal to or less than the depth of the FIFO has occured s ince the

last RS cycle. The retrans mit featu re i s not c ompati ble with the D epth Expans ion Mode

and w ill affect the Hal f-Full Fl ag (HF), in accordance with the relative locations of the

read and write pointers.

Expansion In (XI)This input is a dual-purpose pin. Expansion In (XI) is connec ted to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

Full Flag (FF)The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, in dicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

Empty Flag (EF)The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

Expansion Out/Half-Full

Flag (XO/HF) This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-

nected to ground, this output acts as an indication of a half-full memory.

The M672061F offers a variable offset for the Hal f Full condition. T he offset is loaded

into a register during a reset cycle. When RS is low, the Pr ogrammable Half Full Flag

(PHF) can be loaded from the DATA inputs I0-I8 by pulsing W low or from the DATA out-

M672061F

Rev. E–20-Aug-01

puts Q0-Q8 by pulsing R low. The offset options are listed in table 1. If PHF is not loaded

during the reset cycle, the default offset will be the half of the total memory of the device.

The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the

differen ce between the wr ite a nd read pointe rs is less than or equal to th e Progr amma-

ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half

of the total memory (if the Half Full register has not been loaded during the reset cycle).

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Fl ag ( HF ) wi ll be se t to lo w an d wi ll remain se t un til the differe nc e be twee n th e

write and read pointe rs is less tha n or equal to half of the total memory of the de vice.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

provid ing a pul se to the ne xt devi ce w hen the prev ious de vic e reaches the last memo ry

location.

Data Output (Q0 - Q 8)DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

7M672061F Rev. E–20-Aug-01

Functional Description

Operating Modes

Single Device Mode A single M672061F may be used when the application requirements are for 16384

words or less. The M672061F is in a Single Device Configuration when the Expansion In (XI)

control input is grounded (see Figure 3.). In this mode the Half-Full Flag (HF), which is an acti ve

low output, is shared with Expansion Out (XO).

Figure 3. Block Diagram of Single 16384 × 9

Width Expansion Mode Word wid th ma y be increas ed simpl y by connecting the c orr esp ond in g input contro l si g-

nals of multiple devi ces. S tatus fla gs (EF, FF and HF) can be detected from any device.

Figure 4 demonstrates an 18-bit word width by using two M672061F. Any word width can be

attained by adding additional M672061F.

Figure 4. Block Diagram of 16384 X 18 FIFO Memory Used in Width Expansion Mode

Note: Flag detection is accomplished by monitoring the FF, EF and the HF signals on either

(any) device used in the width expansion configuration. Do not connect any output con-

trol signals together.

(HALF-FULL FLAG)

WRITE (W)(R) READ

DATAIN

(I) DATAOUT

(Q)

FULL FLAG

RESET

(FF)

(RS)

EMPTY F L AG

RETRANSMIT

(EF)

(RT)

EXPANSION IN (XI)

M672061F

Rev. E–20-Aug-01

Table 1. Programmable Half Full Flag Offset

Table 2. Reset and retransmit

Single Device Configuration/Width Expansion Mode

Table 3. Reset and First Load Truth Table

Depth Expansion/Compound Expansion Mode

I8I7I6I5I4I3I2I1I0OFFSET

000000000 0

000000001 32

000000010 64

...

100000000 8192 (Half Full)

Default Offset

...

111111110 16384-64

111111111 16384-32

MODE INPUTS INTERNAL STATUS OUTPUTS

RS RT XI Read Pointer Write Pointer EF FF HF

Reset 0 X 0 Location Zero Location Zero 0 1 1

Retransmit 1 0 0 Location Zero Unchanged X X X

Read/Write 1 1 0 Increment (1) Increment(1) XXX

1. Pointer will increment if flag is high.

MODE INPUTS INTERNAL STATUS OUTPUTS

RS FL XI Read Pointer Write Pointer EF FF

Reset First Device 0 0 (1) Location Zero Location Zero 0 1

Reset All Othe r Devi ces 0 1 (1) Location Zero Location Zero 0 1

Read/Write 1 X (1) XX XX

1. XI is connected to XO of previous device.

See Figure 5

9M672061F Rev. E–20-Aug-01

Depth Expansion (Daisy

Chain) Mode The M672061F can be easily adapted for applications which require more than 16384

words. Figure 5 de monstrate s Depth Expans ion using thre e M672061F . Any depth ca n

be achieved by adding additional 672061F.

The M672061F operates in the Depth Expansion configuration if the following conditions

are met:

1. The first device must be designated by connecting the First Load (FL) control

input to ground.

2. All other devices must have FL in the high stat e.

3. The Expansion Out (XO) pin of each device must be connected to the Expansion In

(XI) pin of the next device. See Figure 5

4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag

(EF). This requires that all EF’s and all FFs be ØRed (i.e. all must be set to generate the

correc t composite FF or EF). See Figure 5

5. The Retransmit (RT) fu nc tion an d Ha lf-F ull Fl ag (HF ) are not available in the Depth

Expansion Mode.

Compound Expansion

Module It is quite simple to apply the two expansion techniques described above together to cre-

ate large FIFO arrays (see Figure 6).

Bidirectional Mode Applications whic h require data buffering between two systems (each system being

capable of Read and Write operations) can be created by coupling M672061F as shown

in Fig ure 7 Car e m us t be taken to e ns ur e th at t he a ppr op riate fl ag is mon ito red by each

syste m (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device

on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow - Through

Modes Two types of flow-through modes are permitted : a read flow-through and a write flow-

through mode. In the read flow-through mode (Figure 18) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The da ta is

enabled on the bus at (tWEF + tA) ns after the lead ing edge of W which is known as the

first write edge and remains on the bus until the R line is raised from low to high, after which the

bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-

porary reset and then will be set. In the interval in which R is low, more words may be written to

the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag) ; how-

ever, the same word (written on the first write edge) presented to the output bus as the read

pointer will not be incremented if R is low. On to ggling R, the remaining words written to the

FIFO will appear on the output bus in accordance with the read cycle timings.

In the write flow -through mode (Figure 19), the F IFO stack allo ws a single word of da ta

to be written immediately after a single word of data has been read from a full FIFO

stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again

in antici pation of a new dat a wo rd. The new word is load ed int o th e FIFO stack on the lea ding

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIFO stack and to increment the write pointer.

M672061F

Rev. E–20-Aug-01

Figure 5. Block Diagram of 49152 x 9 FIFO Memory (Depth Expansion)

Figure 6. Compound FIFO Expansion

Notes: 1. For depth expansion block see section on Depth Expansion and Figure 4.

2. For Flag detection see section on Width Expansion and Figure 3

Figure 7. Bidirectional FIFO Mode

11 M672061F Rev. E–20-Aug-01

M672061F

Rev. E–20-Aug-01

Electrical Characteristics

Absolute Maximum Ratings

Supply voltage (VCC - GND):..................... 0.3V to 7.0V

Input or Output voltage applied: ................(GND - 0.3V) to (Vcc + 0.3V)

Storage temperature: ................................- 65 °C to + 150 °C

DC Parameters

OPERATING RANGE OPERATING SUPPLY VOLTAGE OPERATING TEMPERAT URE

Military Vcc = 5V ± 10% – 55 °C to + 125°C

Parameter Description M672061F-30 M672061F-15 UNIT VALUE

ICCOP (1)

1. Icc measurements are made with outputs open.

Operating supply current 110 120 mA Max

ICCSB (2)

2. R = W = RS = FL/RT = VIH.

Standby supply current 5 5 mA Max

ICCPD (3)

3. All input = Vcc.

Power down current 400 400 µAMax

PARAMETER DESCRIPTION M672061F UNIT VALUE

ILI (1) Input leakage current ± 1 µAMax

ILO (2) Output leakage current ± 1 µAMax

VIL (3) Input low voltage 0.8 V Max

VIH (3) Input high voltage 2.2 V Min

VOL (4) Output low voltage 0.4 V Max

VOH (4) Output high voltage 2.4 V Min

C IN (5) Input capacitance 8 pF Max

C OUT (5) Output capacitance 8 pF Max

1. 0.4 ≤ Vin ≤ Vcc.

2. R = VI H, 0.4 ≤ VOUT ≤ VCC.

3. VIH max = Vcc + 0.3 V. VIL min = -0.3 V or -1 V pulse width 50 ns. For XI input, VIH= 2.8V

4. Vcc min, IOL = 8 mA, IOH = -2 mA

5. Guaranteed but not tested .

13 M672061F Rev. E–20-Aug-01

AC Test Conditions

Input pulse levels: ................................Gnd to 3.0V

Input rise/Fall times: ................................5 ns

Input timing refer ence lev el s: .....................1.5V

Output reference levels: .............................1.5V

Output load: ................................See Figure 8.

Figure 8. Output Load

M672061F

Rev. E–20-Aug-01

SYMBOL (1) SYMBOL (2) PARAMETER (3) (4) M672061F- 30 M672061F- 15 UNIT

Min Max Min Max

READ CYCLE READ CYCLE

TRLRL tRC Read cyc le time 40 - 25 - ns

TRLQV tA Access time - 30 - 15 ns

TRHRL tRR Read recovery time 10 - 10 - ns

TRLRH tRPW Read pulse width (5) 30 - 15 - ns

TRLQX tRLZ Read low to data low Z (6) 5-0-ns

TWHQX tWLZ Write low to data low Z (6) (7) 5-3-ns

TRHQX tDV Data valid from read high 5 - 5 - ns

TRHQZ tRHZ Read high to data high Z (6) - 20 - 15 ns

WRITE CYCLE WRITE CYCLE

TWLWL tWC Write cycle time 40 - 25 - ns

TWLWH tWP W Write p u l s e w i dth (5) 30 - 15 - ns

TWHWL tWR Write recovery time 10 - 10 - ns

TDVWH tDS Data set-up time 18 - 9 - ns

TWHDX tDH Data hold time 0 - 0 - ns

RESET CYCLE RESET CYCLE

TRSLWL tRSC Rese t c ycle tim e 40 - 25 - ns

TRSLRSH tRS Res et pulse width (5) 30 - 15 - ns

TWHRSH tRSS Reset set-up time 30 - 20 - ns

TRSH W L tRSR Reset reco very time 10 - 10 - ns

RETRANSMIT CYCLE RETRANSMIT CYCLE

TRTLWL tRTC Retransmit cycle time 40 - 25 - ns

TRTLRTH tRT Retransmit pulse width (5) 30 - 15 - ns

TWHRTH tRTS Retransmit set-up time (6) 30 - 15 - ns

TRTHWL t RTR Retransmit recovery time 10 - 10 - ns

M672061F

Rev. E–20-Aug-01

FLAGS FLAGS

TRSLEF L tEF L Reset to EF low - 30 - 25 ns

TRSLFFH tHFH, tFFH Reset to HF/FF high - 30 - 25 ns

TRLEFL tREF Read low to EF low - 30 - 15 n s

TRHFFH tRFF Read high to FF high - 30 - 25 ns

TEFHRH tRPE Read width after EF high 30 - 15 - ns

TWHEFH tWEF Write high to EF high - 30 - 15 ns

TWLFFL tWFF Wr ite low to FF low - 30 - 20 ns

TWLHFL tWHF Wr ite low to HF low - 30 - 30 ns

TRHHFH tRHF Read high to HF high - 30 - 30 ns

TFFHWH tW PF Write width after FF high 30 - 15 - ns

EXPANSION EXPANSION

TWLXOL tXOL Read/Write to XO low - 30 - 15 ns

TWHXOH tXOH Read/Write to XO high - 30 - 15 ns

TXILXIH tXI X I pulse width 30 - 15 - ns

TX IH XIL tXIR XI reco v ery time 10 - 10 - ns

TXILRL tXIS XI set-up time 10 - 10 - ns

1. STD symbol.

2. ALT symbol.

3. Timings referenced as in ac t est conditions.

4. All pa rameters tested only.

5. Pulse widths less than minimum value are not allowed.

6. Values guaranteed by design, not currently tested.

7. Only applies to read data flow-through mode.

M672061F

Rev. E–20-Aug-01

Figure 9. Asynchronous Write and Read Operation

Figure 10. Full Flag from Last Write to First Read

M672061F

Rev. E–20-Aug-01

Figure 11 . Empty Flag from Last Read to First Write

Figure 12. Retransmit

Note: EF, FF and PHF may change status during Retransmit, but flags will be valid at tRTC

Figure 13. Empty Flag Timing

tWEF

tRPE

M672061F

Rev. E–20-Aug-01

Figure 14. Full Flag Timing

Figure 15. Programmable Half-Full Flag Timing

Figure 16. Expansion Out

19 M672061F Rev. E–20-Aug-01

Figure 17. Expansion In

Figure 18. Read Data Flow - Through Mode

Figure 19. Write Data Flow - Through Modes

M672061F

Rev. E–20-Aug-01

21 M672061F Rev. E–20-Aug-01

Ordering Information

Note: (*)contact factory

Reference Number Temperature Range Speed Package Quality Flow

MMCP-672061FV-15-E(*) 25°C 15ns SB28.3 Engineering Samples

MMCP-672061FV-15 -55 to +125°C 15ns SB28.3 Mil.

MMCP-672061FV-30 -55 to +125°C 30ns SB28.3 Mil.

SMCP-672061FV-15SB -55 to +125°C 15ns SB28.3 SCC B

SMCP-672061FV-30SB -55 to +125°C 30ns SB28.3 SCC B

SMCP-672061FV-15SC -55 to +125°C 15ns SB28.3 SCC C

SMCP-672061FV-30SC -55 to +125°C 30ns SB28.3 SCC C

MMCP-672061FV-15/883(*) -55 to +125°C 15ns SB28.3 MIL-883 B

MMCP-672061FV-30/883(*) -55 to +125°C 30ns SB28.3 MIL-883 B

SMCP-672061FV-15/883(*) -55 to +125°C 15ns SB28.3 MIL-883 S

SMCP-672061FV-30/883(*) -55 to +125°C 30ns SB28.3 MIL-883 S

5962-9317706QUC -55 to +125°C 15ns SB28.3 QML Q

5962-9317705QUC -55 to +125°C 30ns SB28.3 QML Q

5962-9317706VUC -55 to +125°C 15ns SB 28.3 QML V

5962-9317705VUC -55 to +125°C 30ns SB 28.3 QML V

MMDP-672061FV-15-E 25°C 15ns FP28.4 Engineering Samples

MMDP-672061FV-15 -55 to +125°C 15ns FP28.4 Mil.

MMDP-672061FV-30 -55 to +125°C 30ns FP28.4 Mil.

SMDP-672061FV-15SB -55 to +125°C 15ns FP28.4 SCC B

SMDP-672061FV-30SB -55 to +125°C 30ns FP28.4 SCC B

SMDP-672061FV-15SC -55 to +125°C 15ns FP28.4 SCC C

SMDP-672061FV-30SC -55 to +125°C 30ns FP28.4 SCC C

MMDP-672061FV-15/883(*) -55 to +125°C 15ns FP28.4 MIL-883 B

MMDP-672061FV-30/883(*) -55 to +125°C 30ns FP28.4 MIL-883 B

SMDP-672061FV-15/883(*) -55 to +125°C 15ns FP28.4 MIL-883 S

SMDP-672061FV-30/883(*) -55 to +125°C 30ns FP28.4 MIL-883 S

5962-9317706QZC -55 t o +125°C 15ns FP28.4 QML Q

5962-9317705QZC -55 t o +125°C 30ns FP28.4 QML Q

5962-9317706VZC -55 to +125°C 15ns FP28.4 QML V

5962-9317705VZC -55 to +125°C 30ns FP28.4 QML V

MM0-672061FV-15-E 25°C 15ns Die Engineering Samples

5962-9317706Q9A -55 to +125°C 15ns Die QML Q

5962-9317706V9A -55 to +125°C 15ns Die QML V

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this doc ument, reserves the right to change devices or specif ications detailed herein at any time without notice, and does

not make any co mmitment to update the inform ation contained herein. No licenses to patents or other intellectual property of Atmel are granted

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components in life support dev ices o r systems .

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