NRND LM2722 www.ti.com SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 LM2722 High Speed Synchronous/Asynchronous MOSFET Driver Check for Samples: LM2722 FEATURES DESCRIPTION * * * * * The LM2722, part of the LM2726 family, is designed to be used with multi-phase controllers. This part differs from the LM2726 by changing the functionality of the SYNC_EN pin from a whole chip enable to a low side MOSFET enable. As a result, the SYNC_EN pin now provides control between Synchronous and Asynchronous operations. Having this control can be advantageous in portable systems since Asynchronous operations can be more efficient at very light loads. 1 2 Synchronous or Asynchronous Operation Adaptive Shoot-Through Protection Input Under-Voltage-Lock-Out Typical 20ns Internal Delay Plastic 8-pin SOIC package APPLICATIONS * * * * Driver for LM2723 Intel Mobile Northwood CPU Core Power Supply. High Current DC/DC Power Supplies High Input Voltage Switching Regulators Fast Transient Microprocessors The LM2722 drives both top and bottom MOSFETs in a push-pull structure simultaneously. It takes a logic level PWM input and splits it into two complimentary signals with a typical 20ns dead time in between. The built-in cross-conduction protection circuitry prevents the top and bottom FETs from turning on simultaneously. The cross-conduction protection circuitry detects both the driver outputs and will not turn on a driver until the other driver output is low. With a bias voltage of 5V, the peak sourcing and sinking current for each driver of the LM2722 is typically 3A. In an SOIC-8 package, each driver is able to handle 50mA average current. Input UVLO (Under-Voltage-Lock-Out) forces both driver outputs low to ensure proper power-up and power-down operation. The gate drive bias voltage needed by the high side MOSFET is obtained through an external bootstrap. Minimum pulse width is as low as 55ns. Typical Application +5 Note: for ultra low-frequency operation (such as skip mode at light load), D1 should be a fast recovery type diode instead of a Schottky. 10 D1 VIN (up to 35V) + C2 1PF LM2722 6 SYNC_EN SIGNAL 5 PWM SIGNAL 4 8 VCC CBOOT SYNC_EN HG PWM_IN SW GND LG 3 C1 0.1PF CIN Q1 2 L1 VOUT 1 + 7 Q2 D2 COUT U1 NOTE TI is an Intel Mobile Voltage Positioning (IMVP) licensee. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2001-2013, Texas Instruments Incorporated NRND LM2722 SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 www.ti.com Connection Diagram SW 1 8 GND HG 2 7 LG CBOOT 3 6 VCC PWM_IN 4 5 SYNC_EN Figure 1. SOIC (D) (Top View) Pin Functions Pin Descriptions Pin Name 1 SW Top driver return. Should be connected to the common node of top and bottom FETs Function 2 HG Top gate drive output 3 CBOOT Bootstrap. Accepts a bootstrap voltage for powering the high-side driver 4 PWM_IN Accepts a 5V-logic control signal 5 SYNC_EN 6 VCC 7 LG 8 GND Low gate Enable Connect to +5V supply Bottom gate drive output Ground Block Diagram +4V ~ +7V D1 VIN (up to 35V) CBOOT CBYP CIN HG VCC Power On Reset Q1 SW VOUT + COUT SYNC_EN Q2 Logic D2 PWM_IN Items in bold are external to the IC. LG Shoot-through Protection GND These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LM2722 NRND LM2722 www.ti.com SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 Absolute Maximum Ratings (1) VCC 7.5V CBOOT 42V CBOOT to SW 8V SW to PGND 36V Junction Temperature +150C Power Dissipation (2) 720mW -65 to 150C Storage Temperature ESD Susceptibility Human Body Model (3) 1kV Soldering Time, Temperature (1) (2) (3) 10sec., 300C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. Operating Ratings do not imply ensured performance limits. Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal resistance, JA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PMAX = (TJMAX-TA) / JA. The junction-to-ambient thermal resistance, JA, for the LM2722, it is 172C/W. For a TJMAX of 150C and TA of 25C, the maximum allowable power dissipation is 0.7W. ESD machine model susceptibility is 100V. Operating Ratings (1) VCC 4V to 7V -40 to 125C Junction Temperature Range (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates correctly. Operating Ratings do not imply ensured performance limits. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LM2722 3 NRND LM2722 SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 www.ti.com Electrical Characteristics VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25C. Limits appearing in boldface type apply over the entire operating temperature range. Symbol Parameter Condition Min Typ Max Units 300 A POWER SUPPLY Iq_op Operating Quiescent Current PWM_IN = 0V 190 Peak Pull-Up Current Test Circuit 1, Vbias = 5V, R = 0.1 3.0 A Pull-Up Rds_on ICBOOT = IHG = 0.7A 1.0 Peak Pull-down Current Test Circuit 2, Vbias = 5V, R = 0.1 -3.2 A TOP DRIVER Pull-down Rds_on ISW = IHG = 0.7A 0.5 t4 Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns t6 Fall Time 12 ns t3 Pull-Up Dead Time Timing Diagram 23 ns t5 Pull-Down Delay Timing Diagram, from PWM_IN Falling Edge 27 ns Peak Pull-Up Current Test Circuit 3, Vbias = 5V, R = 0.1 3.2 A Pull-up Rds_on IVCC = ILG = 0.7A 1.0 Peak Pull-down Current Test Circuit 4, Vbias = 5V, R = 0.1 3.2 A BOTTOM DRIVER Pull-down Rds_on IGND = ILG = 0.7A 0.5 t8 Rise Time Timing Diagram, CLOAD = 3.3nF 17 ns t2 Fall Time 14 ns t7 Pull-up Dead Time Timing Diagram 28 ns t1 Pull-down Delay Timing Diagram, from PWM_IN Rising Edge 13 ns Vuvlo_up Power On Threshold VCC rises from 0V toward 5V 3.7 V Vuvlo_dn Under-Voltage-Lock-Out Threshold 3.0 Vuvlo_hys Under-Voltage-Lock-Out Hysteresis 0.7 VIH_EN SYNC_EN Pin High Input VIL_EN SYNC_EN Pin Low Input Ileak_EN SYNC_EN Pin Leakage Current LOGIC ton_min 4 0.8 -2 2 EN = 0V -2 2 A ns Minimum Negative Input Pulse Width 55 VIH_PWM PWM_IN High Level Input Voltage When PWM_IN pin goes high from 0V VIL_PWM PWM_IN Low Level Input Voltage When PWM_IN pin goes low from 5V 4 V 55 (2) (2) V EN = 5V (1) (1) V V 2.4 Minimum Positive Input Pulse Width toff_min 2.5 2.4 V 0.8 If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is off. As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LM2722 NRND LM2722 www.ti.com SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 TEST CIRCUIT DIAGRAMS Timing Diagram Test Circuits 3 5 Vbias 6 4 CBOOT HG SYNC_EN LG VCC SW PWM_IN GND 2 7 VX R 3 Vbias 1 6 8 4 5 6 4 CBOOT LG SYNC_EN HG VCC SW PWM_IN GND 7 2 LG VCC SW PWM_IN GND 7 VX R 1 8 Figure 3. Test Circuit 2 VX R 3 Vbias 5 1 6 8 4 Width = 200ns, One Shot CBOOT LG SYNC_EN HG VCC SW PWM_IN GND 7 2 VX R 1 8 Vbias Width = 200ns, One Shot Figure 4. Test Circuit 3 Ipull_up = SYNC_EN 2 Vbias Figure 2. Test Circuit 1 Vbias HG Width = 200ns,One Shot Width = 200ns, One Shot. 3 5 CBOOT Figure 5. Test Circuit 4 Vx R Ipull_down = (1) Vbias - Vx R Rds_pull_up = (2) Vbias - Vx .R Vx Rds_pull_down = Vx (3) .R Vbias - Vx (4) Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LM2722 5 NRND LM2722 SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 www.ti.com Typical Waveforms Figure 6. Switching Waveforms of Test Circuit Figure 7. When Input Goes High Figure 8. When Input Goes Low Figure 9. Minimum Positive Pulse Application Information MINIMUM PULSE WIDTH In order for the shoot-through prevention circuitry in the LM2722 to work properly, the pulses into the PWM_IN pin must be longer than 55ns. The internal logic waits until the first FET is off plus 20ns before turning on the opposite FET. If, after a falling edge, a rising edge occurs sooner than the specified time, toff_min, the IC may intermittently fail to turn on the top gate when the bottom gate is off. As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output. This condition results in the PWM_IN pin in a high state and neither FET turned on. To get out of this state, the PWM_IN pin must see a low signal for greater than 55ns, before the rising edge. This will also assure that the gate drive bias voltage has been restored by forcing the top FET source and Cboot to ground first. Then the internal circuitry is reset and normal operation will resume. Conversely, if, after a rising edge, a falling edge occurs sooner than the specified miniumum pulse width, ton_min, the IC may intermittently fail to turn on the bottom FET. As the falling edge occurs sooner and sooner, the driver will start to ignore the pulse and produce no output. This will result in the toff inductor current taking a path through a diode provided for non-synchronous operation. The circuit will resume synchronous operation when the rising PWM pulses exceed 55ns in duration. HIGH INPUT VOLTAGES OR HIGH OUTPUT CURRENTS At input voltages above twice the output voltage and at higher power levels, the designer may find snubber networks and gate drive limiting useful in reducing EMI and preventing injurious transients. A small resistor, 1 to 5, between the driver outputs and the MOSFET gates will slightly increase the rise time and fall time of the output stage and reduce switching noise. The trade-off is 1% to 2% in efficiency. A series R-C snubber across in parallel with the bottom FET can also be used to reduce ringing. Values of 10nF and 10 to 100 are a good starting point. 6 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LM2722 NRND LM2722 www.ti.com SNVS169D - NOVEMBER 2001 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D * Page Changed layout of National Data Sheet to TI format ............................................................................................................ 6 Submit Documentation Feedback Copyright (c) 2001-2013, Texas Instruments Incorporated Product Folder Links: LM2722 7 PACKAGE OPTION ADDENDUM www.ti.com 25-Aug-2017 PACKAGING INFORMATION Orderable Device Status (1) LM2722MX/NOPB LIFEBUY Package Type Package Pins Package Drawing Qty SOIC D 8 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM Op Temp (C) Device Marking (4/5) 2722 M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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