Rev.3.0 Dec 22, 2005 page 1 of 17
M61571AFP
2 × 50W Digital Audio Power Amplifier
REJ03F0118-0300
Rev.3.0
Dec 22, 2005
Description
M61571AFP is a Digital power amplifier IC developed for home audio.
M61571AFP can realize maximum Power 50W × 2ch(VD = 21V,THD = 10%, BTL) at 4 Ω load.
It is possible to replace from the conventional analog amplifier system to the digital amplifier system easily.
Features
• Output power Maximum 50W at RL = 4Ω,VD = 21V,THD = 10%, BTL
Rating 37W at RL = 4Ω,VD = 18V,THD = 10%, BTL
• The RENESAS original circuits realize low noise and low distortion characteristics.
• Built-in the 2 channels (BTL) output drivers by Nch-MOS FE T.
• High power efficiency
• High speed switching
• Package: Power SSOP with 52pin (52P9F)
Applications
• Home audio, TV, PDP, LCD Monitor etc.
Recommended Operating Conditions
• Power supply voltage for analog & pre-driver stage: Rating 10V
• Power supply voltage for power stage: Rating 18V,
Recommended operation supply voltage range: from 10V to 21V
• Speaker impedance: operating from 4 to 8Ω
M61571AFP
Rev.3.0 Dec 22, 2005 page 2 of 17
System Block Diagram
OUTA1
VDA1
HBA1
GND1
OUTB1
VDB1
HBB1
GND1
Renesas
Original
Architectural
Processor
Same Above 1 Channel
OUTB2
OUTA2
ASP
M61529FP
M62420FP
etc.
Tone
Control
Electronic
Volume
IN1
IN2
VDD Under
Voltage Detector
Over Temperature
Detector
Over Current
Detector
Level
Shift
Level
Shift
M61571AFP
Rev.3.0 Dec 22, 2005 page 3 of 17
Pin Layout and Internal Block Diagram
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
46
45
44
43
42
41
40
39
38
37
35
34
33
32
31
30
29
28
27
9
36
47
51
50
49
48
521
2
3
5
4
Protect
Circuit
VREF
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Function
Control
Carrier
Generator
DVDD1
PWM2B1
DGND2
IN2
PWM1B2
PWM2B2
VREF
AGND
CLKCTRL
AVCC
PWM1B1
CLK
DGND1
SUB
DVDD2
SUB
MUTEC
VCOR
STBY/MUTE
IN1
OP1O
PWM1A1
PWM2A1
OP2O
PWM1A2
PWM2A2
VDB2
VSB2
OUTB2
SUB
OUTB2
HBB1
OUTB1
OUTB1
VSB1
VSA1
VSA1
VDB1
VDA1
OUTA1
SUB
OUTA1
VSB1
VSB2
VDA2
OUTA2
OUTA2
VSA2
VSA2
HBA1
HBA2
HBB2
Renesas
Original
Architectural
Processor
Renesas
Original
Architectural
Processor
Top View (Facing up Heat Spreader)
M61571AFP
Rev.3.0 Dec 22, 2005 page 4 of 17
Pin Description
No. Symbol Description
49, 50 VSA1 CH1-A block: Ground pin for power output stage
47, 48 OUTA1 CH1-A block: Power output pin
51 VDA1 CH1-A block: Power supply pin for power output stage (VD is supplied)
52 HBA1 CH1-A block: Capacitor connection pin for bootstrap on "H" side
44, 45 VSB1 CH1-B block: Ground pin for power output stage
41, 43 OUTB1 CH1-B block: Power output pin
46 VDB1 CH1-B block: Power supply pin for power output stage (VD is supplied)
40 HBB1 CH1-B block: Capacitor connection pin for bootstrap on "H" side
2 DGND1 CH1 Ground pin for digital pre-driver stage
CH1 power block
1 DVDD1 CH1 Power supply pin for digital pre-driver stage (DVDD=10V supply)
29, 30 VSA2 CH2-A block: Ground pin for power output stage
31, 32 OUTA2 CH2-A block: Power output pin
28 VDA2 CH2-A block: Power supply pin for power output stage (VD is supplied)
27 HBA2 CH2-A block: Capacitor connection pin for bootstrap on "H" side
34, 35 VSB2 CH2-B block: Ground pin for power output stage
36, 38 OUTB2 CH2-B block: Power output pin
33 VDB2 CH2-B block: Power supply pin for power output stage (VD is supplied)
39 HBB2 CH2-B block: Capacitor connection pin for bootstrap on "H" side
25 DGND2 CH2 Ground pin for digital pre-driver stage
CH2 power block
26 DVDD2 CH2 Power supply pin for digital pre-driver stage (DVDD=10V supply)
8 IN1 CH1 Analog signal input pin
7 OP1O CH1 Amp output
4 PWM1A1 CH1-A block PWM generate pin1
3 PWM2A1 CH1-A block PWM generate pin2
5 PWM1B1 CH1-B block PWM generate pin1
6 PWM2B1 CH1-B block PWM generate pin2
19 IN2 CH2 Analog signal input pin
20 OP2O CH2 Amp output
23 PWM1A2 CH2-A block PWM generate pin1
24 PWM2A2 CH2-A block PWM generate pin2
22 PWM1B2 CH2-B block PWM generate pin1
21 PWM2B2 CH2-B block PWM generate pin2
15 AVCC Analog Block: Power supply pin (AVCC=10V supply)
14 VREF Analog Block: Reference voltage pin
Analog block
13 AGND Analog Block: Ground
18 CLKCNTL Pin for frequency setting of internal carrier generator
17 CLK Clock Input/Output pin
12 VCOR Carrier frequency controlled pin
10 MUTEC Capacitor connection pin for mute control
9 STBY/ MUTE Stand-by/ Mute control input pin
Common
11, 16, 37, 42 SUB SUB terminal of IC is connected to exposed heat sink pad.
M61571AFP
Rev.3.0 Dec 22, 2005 page 5 of 17
Absolute Maximum Ratings
Parameter Symbol Value Unit Condition
40 DC
HBA*, HBB*
Maximum supply voltage HBmax 50 V HBA*, HBB* Pin
Voltage AC: under 100ns of
pulse width
25 DC
VD* Maximum supply voltage VDmax 40 V VD* Power Supply
Voltage AC: under 100ns of
pulse width
Absolute maximum rating
voltage VDDmax 16 V VDD* power supply voltage
Power dissipation Pd 7.5 W Ideal heat dissipation
condition at Ta = 75°C
Thermal resistance θjc 10 °C/W from junction to case
Junction temperature Tj 150 °C
Operating ambient
temperature Ta –20 to +75 °C
Storage temperature Tstg –40 to +125 °C
Note: * marks mean the number of channel 1 to 2.
Notes regarding this product
Notes: 1. This product may generate heat, even while operating normally, and it may become high temperature. This
product may seldom become high temperature further by the poor property, failure, etc. not only including
peripheral parts.
Moreover, since it is used for the last stage of a product, and that one may be damaged according to an
external factor, please fully take into consideration in use!
This product is designed on the assumption that a consumer product. Please be sure to use it within the heat
dissipation condit ion of this specificatio n. If heat d issipation conditio n becomes fall, there is fear of damage
on a fall or abnormalities of the p erformance.
2. If the instant peak value of the VD power supply current exceeds 8A per channel (design value), included
over current protector will the PWM operation. It is unnecessary to supply more over this current value,
please mind.
The maximum current value at typical 4Ω operation is a little less than 3.5A.
When you use it, please take notice the stability of supply vo ltage t hat each ter mi nal power does not exceed
rated value.
3. This product includes a MOS transistor and a CMOS logic circuit.
Since there are possibilities generated in a MOS transistor o r a CMOS logic circ uit, such as destruction and a
latch up, please set for use it and be careful of it like a MOS transistor or the CMOS logic LSI.
M61571AFP
Rev.3.0 Dec 22, 2005 page 6 of 17
Thermal Derating
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0 25 50 75 100 125 150
Using an ideal Heat Sink(*1)
Power Dissipation Pd (W)
Ambient Temperature Ta (°C)
Heat reduction characteristic measurement
RENESAS recommended board(*2)
(Reference data)
*1. Maximum output power Pd = 12.5W under Ta = 25°C, using an ideal Heat Sink
*2. Renesas recommended board specification
(Board specification)
• Material: Glass epoxy FR-4
• Size: 70 × 70 mm
• Thickness: t = 1.6 mm
(Wiring specification of 1/2 layer)
• Material: Copper
• Thickness: t = 18 µm
1st layer(Top View) 2nd layrer(Back View)
Note: Please be sure to use it within the hea t d issipation condition of this specification. If heat dissipatio n condition
becomes fall, there is fear of damage on a fall or abnormalities of the performance.
Recommended Operating condition
Limits
Parameter
Symbol Min Typ Max
Unit
Condition
Power supply voltage
for power output stage VD* AVCC 18 21 V VD* (pins 28,33,46,51)
Power supply voltage
for digital pre-driver stage DVDD* 9 10 11 V
DVDD1 (pin 1),
DVDD2 (pin 26)
Power supply voltage
for analog stage AVCC 9 10 11 V AVCC (pin 15)
Control voltage of low level VL 0 — 1 V pin 9, AVCC = 10V
Control voltage of middle level VM 2.3 — 5.5 V pin 9, AVCC = 10V
Control voltage of high level VH 7.5 — AVCC V pin 9, AVCC = 10V
Note: 1. * marks mean the number of channel 1 to 2.
2. Please use DVDD and AVCC on same voltage.
3. ”Absolute maximum rating” means the limitation value to available to let the device destroyed.
4. "Recommended operation conditions" indicates the conditions as which a device functions correctly. However,
this doesn’t guarantee the specific performance limit.
5. Moreover, "Electronic characteristics" is the electric specification of DC and AC which guarantees the specific
performance limit, when the examination conditions indicated are fulfilled. Although the specification as
which the limit value is not specified among parameters is not guaranteed, central value (TYP) serves as an
index, which shows the performance of a device
This is because these parameters are greatly dependent on evaluation board layout design / specification
parts / power supply section design, and is a standard value in the board /parts of our company’s
specification
M61571AFP
Rev.3.0 Dec 22, 2005 page 7 of 17
Electronic Characteristics
(Unless otherwise noted,
Ta=25°C, VD=18V, DVDD,AVCC=10V, Gv=18dB, Carrier Frequency=550kHz,, f = 1kHz, RL=4Ω)
DC Characteristics
Limit
Parameter
Symbol Min Typ Max
Unit
Measurement Condition
Circuit current
VD Circuit current IVD 16 35 mA No signal (Power stage)
VDD Circuit current IVDD 60 100 mA No signal (Pre-driver + Analog)
Stand-by Circuit current ISTVD 80 250 µA Stand-by
Under voltage detection
Detection level of under-voltage AVCCR 5.5 6.0 7.0 V Between VDD and GND
Under-voltage hysteresis voltage AVCCH 1 V Detection → Recovery
Heating detection
Temperature of protection starting TPRH 150 °C Note 1
Temperature of protection release TPRL 130 °C
Over current detection
Over current detection value IMAX 8 A
Output ON resistance of power MOS
H side 300 mΩ IF=100mA
Output ON resistance L side Ron 280 mΩ IF=100mA
Note 1: The detection temperature of a heat detection circuit is the objective value at designing, and it does not
guarantee the detection value. (These measurements are not checked by the temperature test.)
AC Characterist ic s
Limit
Parameter
Symbol Min Typ Max
Unit
Measurement Condition
Output power1 Po1 37 W THD + N = 10%
400HzHPF, 30kHzLPF
Output power2 Po2 30 W THD + N = 1%
400HzHPF, 30kHzLPF
Maximum output power Pomax 50 W VD = 21V, THD + N = 10%, 30kHzLPF
400HzHPF
Total harmonic
distortion THD + N 0.02 0.1 % Po = 15W, 400HzHPF, 30kHzLPF
Output noise level No 50 100 μVrms A-Weighted filter
Gain voltage Gv 16 18 20 dB Po = 1W, Analog block: Gv = 0dB
Mute level Mute 85 dB
Channel balance CBAL –0.5 0 +0.5 dB Po = 1W, Analog block: Gv = 0dB
Ripple rejection ratio PSRR 60 dB Vripple = 400mV, Fi = 1kHz
Power efficiency Eff 85 % Po = 30W, Fi = 1kHz, at 1ch input
M61571AFP
Rev.3.0 Dec 22, 2005 page 8 of 17
Functional Explanation
1. System Block Diagram / 1ch
Level
Shift
Level
Shift
VD=18Vtyp
DVDD=10Vtyp
IN
RL=4
M61571AFP
12
1.5
1.5
12
R1
R2
System Total Gain
Gv = 20log R1
R2 6
++
Analog
Stage
Gain
Internal
Gain
BTL
12
When R1=20k , R2=75k
Gv = 29.5dB
AVcc=10Vtyp
Renesas
Original
Architectural
Processor
Ω
[ dB ]
Ω
Ω
μF
μH
μF
μH
M61571AFP
Rev.3.0 Dec 22, 2005 page 9 of 17
2. Carrier Generator
This IC is built-in the functions for (1) changing a carrier frequency and (2) switching the master/slave mode. These
functions can perform easily improvement adjustment of efficiency / performance / EMI performance. And, the
measure is possible also for the beat problem which originates in the carrier frequency gap in the case of carrying out
two or more simultaneous operation of this IC by the multi-channel system etc.
(1) The setting method of Carrier frequency
It is possible to set up the reference clock of PWM generator by controlled DC voltage of VCOR (12pin).
That is able to change the frequency value from 300kHz to 2.0MHz.
However, please evaluate enough in the case of use the carrier frequency under our recommendation value (550kHz).
In the case of the conditions which made low carrier frequency and high supply voltage, please be careful for that
PWM modulating operation may become unstable.
17
CLKCTRL
CLK
CLKSW
18
12
VCOR
VCOR: over 0.5V
<Reference Data>
Carrier Control Voltage(12pin DC Voltage) vs Carrier Frequency
<Condition> VD=18V, Vcc=10V, Ta=27°C, RL=4Ω
Carrier Frequency (kHz)
Control Voltage (V)
2500
2000
1500
1000
500
00246810
Carrier Input/Output
Carrier
Generator
Carrier Control Voltage
Carrier Input/Output SW
To Internal PWM Generator
M61571AFP
Rev.3.0 Dec 22, 2005 page 10 of 17
(2) The setting method of Carrier signal I/O
18pin: The mode control of a career generation circ uit of operation by setup of CLKCTRL pin.
The control mode has the two modes, the master mode which outputs the carrier signal generated in internal VCO to
CLK terminal (17pin : CLK), and the slave mode which stops internal VCO and receives the carrier of a master chip
from CLK terminal (17pin : CLK).
The control table for operation mode
CLKCNTL CLK CLKSW Operation Mode
AVCC Output ON Master mode: Internal VCO generates carrier and sends it to slave chips.
AGND Input OFF Slave mode: It receives carrier from other master chip.
Note: When using two or more M61571AFP, It is possible to generate a master clock from one IC and to operate other
ICs using the clock. The beat generated by the difference of the carrier frequency of each IC can be prevented.
In the case of multi channel use
Carrier
Generator
17
CLKSW
IC1:Maste
r
IC2:Slave
IC3:Slave
A
VCC
18
17
CLKSW
18
17
CLKSW
18
12
12
12
Carrier
Generator
Carrier
Generator
M61571AFP
Rev.3.0 Dec 22, 2005 page 11 of 17
3. Function Control
This IC has Stand-by /Mute function and it is possib le to control by changing the volta ge of 9pin: STB Y/MUTE.
(1) Fu nctio n setti ng
9 pin: Stand-by/Mute Operating Condition Output FET Condition
L Stand-by Hi-Z
M Mute Duty = 50%
H Normal operation Normal operation
(a) Stand-by
While cutting off the output of all output MOSFET and muting the music play, the standby current can be made
into the minimum.
Moreover, at the standby mode all circuits except for the standby circuit stop completely and also stop the pulse
modulation signal. So , an output noise isn't generated.
(b) Mute
It mutes an output signal at th e same time it mutes an input signal. Ho wever, the pulse modulation signal outputs
by 50% duty. (Mute level: 85dB typ.)
If it turns on the mute for preventing a shock noise, it will shift to the mute statu s s moot hl y.
(Soft muting function)
(2) 9pin: STBY/ M UTE Control voltage ran ge
0 1 2.3 5.5 7.5 10
Stand-by Mute Normal
9pin: STBY/MUTE Voltage (V)
operation
(3) S oft Mut ing
The time of Soft Muting is decided by the external capacitor of 10pin: MUTEC. When C = 0.1µF, this becomes
about 50ms. We recommend the setting over 0.1µF (50ms) for preventing shock sound.
About 50ms
Normal Operation Normal Operation
Mute
Soft
Muting ON
Soft
Muting OFF
Muting
ON
Muting
OFF
About 50ms
By External Condenser
of MUTEC: 10pin
(at C=0.1μF)
By External Condenser
of MUTEC: 10pin
(at C=0.1μF)
M61571AFP
Rev.3.0 Dec 22, 2005 page 12 of 17
4. Protection Circuit
When M61571AFP detects some protect factor, it has built-in the various protection circuits.
(1) Over Current Protection Circuit
This circuit protects by detecting the unusual over current of Output Power FETs. The detection current values are
8A(typ).
If over current protection circuit are operated, M61571AFP makes all output FETs to “ Hi-Z” state and output pins
to “Open”.
(2) Over Temperature Protection Circuit
This circuit detects unusual over temperature and protects IC (chip). It operates before reach out to thermal run away
such as internal junction temperature and the protection circ uit op e rates until it falls to the temperature of hysteresis
condition.
When over temperature protection circuit is operated, it makes all output FET to “ Hi-Z” state and output pins to
“Open”.
Protection start temperature: 150ºC typ Protection restore temperature: 130ºC typ
(3) Under Voltage P r otection Circuit
This circuit detects an unusual und er voltage of analog pre stage power supply and protects. When under voltage
detected, it makes all output FET to “ Hi-Z” state and output pins to “Open”.
When the transient at power ON, the power supply of AC line falls, the load impedance changes and the supply
voltage falls temporarily, this is the function committed effectively and it is possible to prevent unusual de struction
and t o make POP sound by th e unusual output into t he minimum
Under voltage detection voltage: 6.0V(typ)
Under voltage release voltage: 7.0V(typ)
(4) The table of protection circuit operation
Protection Mode Protect Condition Output Stage Condition
Over current protection Detection current: 8A typ Hi-Z
Over temperature protection Protection starting: 150ºC typ
Protection release: 130ºC typ Hi-Z
AVCC under voltage Detection voltage: 6.0V
Release voltage: 7.0V Hi-Z
(5) T he restoring from a protection state
• At the case of over current protection, over temperature protection and under voltage protection
The restoring from a protection state is performed automatically. While the protection is operating, restoring to
normal oper ation is usual ly p erfor med for every constant time.
Then, if protection conditions are canceled, it returns to normal operation, if operation is not canceled, a protection
state will usually be continued. The cycle of return operation is decided by capacity value of the capacitor linked to
14pin: VREF, and becomes about 1 second at the time of 47µF (design value).
For stable operation, we recommend over 10μF as a capacitor value. The protection state can monitor in this
oscillation condition of REF ter minal. (Refer to the follo win g figure about the restoring sequence)
Operation Normal Operation
VREF pin
(14pin)
Under Protection Normal Operation
1/2AVcc
(5V)
About 1sec
Internal protect signal
Protection Off Protection On Protection Off
M61571AFP
Rev.3.0 Dec 22, 2005 page 13 of 17
Notes at the time of Power ON and Power OFF
When the power ON, M61571AFP automatically operates the soft mute release from the mute state by the following
sequence.
Timing at the power ON
t
(Power Supply Voltage)
PWM Output
VREF
1/2AVCC
1/2VD
AVCC
VD
About 50ms
Duty 50%
T
START
About 1sec
Output Wave Envelope
By External Capacitor
of MUTEC: 10 pin
(at C=0.1μF)
By External Capacitor
of VREF: 14 pin
(at C=47μF)
TSTART mea ns the time by reached VREF to 1/2Avcc and determined automatically by the value of capacitor CREF
connected to external parts according to the following formula.
()
sec
10500
AVC
T6
CCREF
START −
×
⋅
=
When VCC=10V and CREF=47μF, TSTART=940 ms(Typ)
14
V
REF
C
REF
7
8
R3
R2
R1
V
C1
C1
1/2Vcc
Condition 1) It is necessary to set a system as a stable state by completing to charge of
the input coupling capacitor C1 by T
START
.
correspond to
a signal
+
-
T
VC1
=
1.7
×
(C
1
(
R
1
+
R
2
)
) < T
START
M61571AFP
Rev.3.0 Dec 22, 2005 page 14 of 17
The example of an application circuit
SBDi2
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
46
45
44
43
42
41
40
39
38
37
35
34
33
32
31
30
29
28
27
9
36
47
51
50
49
48
52
1
2
3
5
4
Carrier
Generator
Protect
Circuit
VREF
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Function
Control
Renesas
Original
Architectural
SBDi1
SBDi3
SBDi4
SBDi5
SBDi6
SBDi7
SBDi8
*A
*A
*A
*A
*B
*B
*B
*B
*C
*C
*C
*C
*C
*C
*C
*C
*1
22μHμ
10
L6 22μH
L5 C26
2.2 μ
1.5K
1.5K
560p
56p
56p
560p
75K
C22
C8
C9
C23
R6
C29
R1
R2
R8
20K
STBY/
MUTE
0.1
C35
μ
R12
22K
R13
180K
*1
22μH
L7
10
C27
μ
0.1
C18
μ
47
C3
μ
CLK
CLKCNTL
2.2
C30
μ
+
20K
R9
1.5K
R3
1.5K
R4
22
L8
μH
10
C28
μ
IN1
100
R10
+
+
IN2
560p
56p
56p
560p
C24
C10
C11
C25
-
+
Processor
-
+
Renesas
Original
Architectural
Processor
μ
47
C2
F
+
μ
0.1
C12
Fμ
0.1
C13
F
+
10V
Reg.
VD=+18V
VS
μ
47
C1
F
μ
1
C18
12
L1
H
μ
*2) C31
1.5
μ
C32
1.5
μ
12
L2
H
μ
12
L3
H
μ
C33
1.5
μ
12
L4
H
μ
C21
1μ
C19
1
μ
*2)
C20
1
μ
C14
μ
0.1
C4μ
47
C15
μ
0.1
C5
μ
47
+
C16
μ
0.1
C17
μ
0.1
C7
μ
47
C6
μ
47
+
+
RL = 4Ω
RL = 4Ω
C34
1.5
μ
75K
R7
+
+
*1: In the case of a substrate design, I recommend arranging in advance on the point near IC of a power
supply and a GND line. So, an improvement of an audio performance (distortion and noise) and an
EMI performance can be expected. The can delete, if satisfactory by prior evaluation.
*2: Since high frequency big current flows to this capacitor and diode, please arrange to an output
terminal and the power supply terminal directly and consider at the time of a layout design to
become the smallest possible loop. Otherwise, it becomes the cause of malfunction, performance
aggravation, and destruction.
M61571AFP
Rev.3.0 Dec 22, 2005 page 15 of 17
Special External Parts Lists
Parts No. Parts NameType NamePcs
A C31, 32, C33, C34 C-FILM 1.5μ-50V 4
B L1, L2, L3, L4 CHOKE-COIL 12μH 7G09B-120M(SAGAMI ELEC CO., LTD.) 4
C SBDi1,2,3,4,5,6,7,8 DIODE (Shot key barrier ) RB160L40 (made by RHOM) 8
(Note1) Choke coil(*B) are consisted of Second Butterworth LPF in a pair with the capacitor(*A) of from C31 to C34, it
is expressed with cut off frequency fc = 1/(2*3.14√LC).
Since they are the important parts which determine EMI performance and audio performance, please select
after sufficient examination EMI.
Especially, in order to gather electric power efficiency, we recommend the small thing of DC resistance.
Moreover, when excitation current is taken into consideration, it sets at carrier frequency the o'clock of
550kHz, and it is 12μH (I recommend constituting above H.).
When use is carried out on high carrier frequency, it is possible to use a still smaller choke coil.
Notes about mounting
a) Reduction of high frequency impedance for digital GND
At digital GND for pre-driver (2pin and 25pin : DGND terminal) the very big pulse current for high frequency is
flowing in order to carry out the high-speed drive of the output power MOS transistor. Therefore, if the board layout
design of this digital GND i s b ad, the high frequency noise from this PWM oscillation becomes large and has a bad
influence on function operation and the analog circuit of the internal circuits. So, this may cause malfunction,
perfor mance degr ada tion and destruction. In orde r to red uce the influence of t his high freq uenc y noise, i t is very
effective to lower the high frequency impedance of GND pattern, and we recommend to make GND pattern of a digital
system to thickly GND.
b) Disposal of SUB terminal (11, 16, 37, 42 pins)
This IC has 4 pins of SUB terminal (11, 16, 37 and 42pin) and connects to the substrate (substrate: chip back) of IC chip.
The leakage current of the high frequency generated at the timing of the edge of PWM may flow into this terminal. If
the impedance of the substrate is high, noise level may become large and the parasitism transi stor inside IC may operate,
and malfunction may be caused.
In order to avoid this, it is effective to reduce the impedance as much as possible. W e recommend to connect each SUB
terminal to GND which the high frequenc y impedance is low (DGND of the thickl y GND of recommendation by a
clause)
c) Disposal of analog GND
In order to reduce interference from the output power stage’s GND (VS terminal of each bridge) and pre-driver stage of
digital GND (DGND terminal) as much as possible, please connect analog GND by one point at the electric supply
GND point, and consider as wiring without a common impedance. Moreo ver, we recommend to insert a coil/resistance
(L6, R10) which separates between the GND electric supply point and high frequency if needed.
d) Destructive measure
Although this IC built in various protection circuits, there is a case which the unusual current occurs in output terminal
at the time of a load short circuit, the output ground short and PWM operation starting. In t his case, the overshoot of
PWM output becomes very large. If this voltage becomes over absolute maximum supply voltage, there is a case where
IC breaks. So, please design the board layout whic h the voltage for each terminal becomes less than the absolute
maximum rating s’ suppl y voltage (5page).
In addition, please design that a guide of maximum over shoot is P WM output=under 40V and HB (Bootstrap)
terminal=under 50V.
M61571AFP
Rev.3.0 Dec 22, 2005 page 16 of 17
The typical example of an overshoot measure
(1) The bypass capacitor (Laminated ceramic capacitor) from the power supply of output power transistor (VD) to GND
(VS) is arranged at the pin in near. (Recommendation: Under 1mm from the pin). (Refer to the 2 in page14)
(2) Connect to Schottky barrier diode among PWM output (VD) to GND (VS).
(3) Zener diode (35V) is connected between PWM output (VS terminal) to GND (VS), and it prevents so that it is
prevented so that the voltage exceeding pressure prevention may not be built over a terminal.
(4) Add to the Snaber circuit of CR in-series composition among the PWM output to GND (VS).
VD
VS
HB
VD
VS
OUT
HB
VD
VS
OUT
Countermeasure 1:Bypass Capacitor for High Frequency
Recommending position is under 1mm from pin.
(nearest at a pin)
(Note) We recommend to short this distance.
LC Filter
Countermeasure 2:Shottky barrier Diode for oppression of surge voltge
The design guide of the worst overshoot value at the short-circuit test
(We recommend terminal proximity arrangement of IC)
OUT terminal : under +40V
HB terminal : under +50V
Load (Speaker)
M61571AFP
(Note) These descriptions are notes in having our company digital amplifier IC M61571AFP used, and do not
guarantee all of the operation and a property.
In a board design, you advise these contents and have it confirmed that operation and a property are satisfactory
in your compa ny after IC mounting.
M61571AFP
Rev.3.0 Dec 22, 2005 page 17 of 17
Package Dime nsions
2.
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
NOTE)
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
Detail F
L
A1
A2
Index mark
*3
*2
F
27
26
1
52
*1
x
y
E
1
D2
A
bp
D
c
E
H
E
A1
HE
y 0.10
e0.65
c
0
°
10
°
L 0.3 0.5 0.7
0 0.1 0.2
A 2.2
11.63 11.93 12.23
A22.0
E8.28.48.6
D 17.317.517.7
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.23 0.25 0.3
P-HSSOP52-8.4x17.5-0.65 0.8g
MASS[Typ.]
52P9F-KPRSP0052JB-B
RENESAS CodeJEITA Package Code Previous Code
bp0.22 0.27 0.32
x 0.12
D28.8
E15.0
8.6
4.6 4.8
9.0
e
Under development
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .5.0
