M61571AFP 2 x 50W Digital Audio Power Amplifier REJ03F0118-0300 Rev.3.0 Dec 22, 2005 Description M61571AFP is a Digital power amplifier IC developed for home audio. M61571AFP can realize maximum Power 50W x 2ch(VD = 21V,THD = 10%, BTL) at 4 load. It is possible to replace from the conventional analog amplifier system to the digital amplifier system easily. Features * Output power Maximum 50W at RL = 4,VD = 21V,THD = 10%, BTL Rating 37W at RL = 4,VD = 18V,THD = 10%, BTL * The RENESAS original circuits realize low noise and low distortion characteristics. * Built-in the 2 channels (BTL) output drivers by Nch-MOS FET. * High power efficiency * High speed switching * Package: Power SSOP with 52pin (52P9F) Applications * Home audio, TV, PDP, LCD Monitor etc. Recommended Operating Conditions * Power supply voltage for analog & pre-driver stage: Rating 10V * Power supply voltage for power stage: Rating 18V, Recommended operation supply voltage range: from 10V to 21V * Speaker impedance: operating from 4 to 8 Rev.3.0 Dec 22, 2005 page 1 of 17 M61571AFP System Block Diagram HBA1 VDA1 IN1 Level Shift ASP OUTA1 M61529FP M62420FP etc. GND1 Renesas Original HBB1 Architectural Processor Tone Control VDB1 Level Shift OUTB1 Electronic Volume GND1 Over Temperature Detector VDD Under Voltage Detector Over Current Detector IN2 OUTA2 Same Above 1 Channel OUTB2 Rev.3.0 Dec 22, 2005 page 2 of 17 M61571AFP Pin Layout and Internal Block Diagram DVDD1 1 52 HBA1 DGND1 2 51 VDA1 PWM2A1 3 50 VSA1 PWM1A1 4 49 VSA1 PWM1B1 5 Renesas 48 OUTA1 PWM2B1 6 Original 47 OUTA1 OP1O 7 46 VDB1 45 VSB1 44 VSB1 43 OUTB1 SUB 11 42 SUB VCOR 12 41 OUTB1 40 HBB1 39 HBB2 38 OUTB2 37 SUB 36 OUTB2 35 VSB2 34 VSB2 33 VDB2 32 OUTA2 31 OUTA2 30 VSA2 29 VSA2 DGND2 25 28 VDA2 DVDD2 26 27 HBA2 IN1 STBY/MUTE Level Shift Architectural Processor 8 Level Shift 9 MUTEC 10 Function Control AGND 13 VREF 14 AVCC 15 SUB 16 CLK 17 Protect Circuit VREF Carrier Generator Level Shift CLKCTRL 18 IN2 19 Renesas OP2O 20 PWM2B2 21 Original PWM1B2 22 Architectural Processor PWM1A2 23 PWM2A2 24 Level Shift Top View (Facing up Heat Spreader) Rev.3.0 Dec 22, 2005 page 3 of 17 M61571AFP Pin Description Common Analog block CH2 power block CH1 power block No. Symbol Description 49, 50 47, 48 VSA1 OUTA1 CH1-A block: Ground pin for power output stage CH1-A block: Power output pin 51 52 VDA1 HBA1 CH1-A block: Power supply pin for power output stage (VD is supplied) CH1-A block: Capacitor connection pin for bootstrap on "H" side 44, 45 41, 43 VSB1 OUTB1 CH1-B block: Ground pin for power output stage CH1-B block: Power output pin 46 40 VDB1 HBB1 CH1-B block: Power supply pin for power output stage (VD is supplied) CH1-B block: Capacitor connection pin for bootstrap on "H" side 2 1 DGND1 DVDD1 CH1 Ground pin for digital pre-driver stage CH1 Power supply pin for digital pre-driver stage (DVDD=10V supply) 29, 30 31, 32 VSA2 OUTA2 CH2-A block: Ground pin for power output stage CH2-A block: Power output pin 28 27 VDA2 HBA2 CH2-A block: Power supply pin for power output stage (VD is supplied) CH2-A block: Capacitor connection pin for bootstrap on "H" side 34, 35 36, 38 VSB2 OUTB2 CH2-B block: Ground pin for power output stage CH2-B block: Power output pin 33 39 VDB2 HBB2 CH2-B block: Power supply pin for power output stage (VD is supplied) CH2-B block: Capacitor connection pin for bootstrap on "H" side 25 26 DGND2 DVDD2 CH2 Ground pin for digital pre-driver stage CH2 Power supply pin for digital pre-driver stage (DVDD=10V supply) 8 7 IN1 OP1O CH1 Analog signal input pin CH1 Amp output 4 3 PWM1A1 PWM2A1 CH1-A block PWM generate pin1 CH1-A block PWM generate pin2 5 6 PWM1B1 PWM2B1 CH1-B block PWM generate pin1 CH1-B block PWM generate pin2 19 20 IN2 OP2O CH2 Analog signal input pin CH2 Amp output 23 24 PWM1A2 PWM2A2 CH2-A block PWM generate pin1 CH2-A block PWM generate pin2 22 21 PWM1B2 PWM2B2 CH2-B block PWM generate pin1 CH2-B block PWM generate pin2 15 14 AVCC VREF Analog Block: Power supply pin (AVCC=10V supply) Analog Block: Reference voltage pin 13 18 AGND CLKCNTL Analog Block: Ground Pin for frequency setting of internal carrier generator 17 12 CLK VCOR Clock Input/Output pin Carrier frequency controlled pin 10 9 MUTEC STBY/ MUTE Capacitor connection pin for mute control Stand-by/ Mute control input pin 11, 16, 37, 42 SUB SUB terminal of IC is connected to exposed heat sink pad. Rev.3.0 Dec 22, 2005 page 4 of 17 M61571AFP Absolute Maximum Ratings Parameter Symbol Value Unit 40 V HBA*, HBB* Pin Voltage DC AC: under 100ns of pulse width V VD* Power Supply Voltage DC AC: under 100ns of pulse width 16 V VDD* power supply voltage Pd 7.5 W Ideal heat dissipation condition at Ta = 75C jc Tj 10 150 C/W C Ta -20 to +75 C Tstg -40 to +125 C HBA*, HBB* Maximum supply voltage HBmax VD* Maximum supply voltage VDmax Absolute maximum rating voltage VDDmax Power dissipation Thermal resistance Junction temperature 50 25 Operating ambient temperature Storage temperature Condition 40 from junction to case Note: * marks mean the number of channel 1 to 2. Notes regarding this product Notes: 1. This product may generate heat, even while operating normally, and it may become high temperature. This product may seldom become high temperature further by the poor property, failure, etc. not only including peripheral parts. Moreover, since it is used for the last stage of a product, and that one may be damaged according to an external factor, please fully take into consideration in use! This product is designed on the assumption that a consumer product. Please be sure to use it within the heat dissipation condition of this specification. If heat dissipation condition becomes fall, there is fear of damage on a fall or abnormalities of the performance. 2. If the instant peak value of the VD power supply current exceeds 8A per channel (design value), included over current protector will the PWM operation. It is unnecessary to supply more over this current value, please mind. The maximum current value at typical 4 operation is a little less than 3.5A. When you use it, please take notice the stability of supply voltage that each terminal power does not exceed rated value. 3. This product includes a MOS transistor and a CMOS logic circuit. Since there are possibilities generated in a MOS transistor or a CMOS logic circuit, such as destruction and a latch up, please set for use it and be careful of it like a MOS transistor or the CMOS logic LSI. Rev.3.0 Dec 22, 2005 page 5 of 17 M61571AFP Power Dissipation Pd (W) Thermal Derating 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Using an ideal Heat Sink(*1) Heat reduction characteristic measurement RENESAS recommended board(*2) 0 25 50 75 100 125 150 Ambient Temperature Ta (C) (Reference data) *1. Maximum output power Pd = 12.5W under Ta = 25C, using an ideal Heat Sink *2. Renesas recommended board specification (Board specification) * Material: Glass epoxy FR-4 * Size: 70 x 70 mm * Thickness: t = 1.6 mm (Wiring specification of 1/2 layer) * Material: Copper * Thickness: t = 18 m 1st layer(Top View) 2nd layrer(Back View) Note: Please be sure to use it within the heat dissipation condition of this specification. If heat dissipation condition becomes fall, there is fear of damage on a fall or abnormalities of the performance. Recommended Operating condition Limits Parameter Symbol Min Typ Max Unit Condition AVCC 18 21 V VD* (pins 28,33,46,51) Power supply voltage for power output stage VD* Power supply voltage for digital pre-driver stage DVDD* 9 10 11 V DVDD1 (pin 1), DVDD2 (pin 26) Power supply voltage for analog stage AVCC 9 10 11 V AVCC (pin 15) Control voltage of low level VL 0 -- 1 V pin 9, AVCC = 10V Control voltage of middle level VM 2.3 -- 5.5 V pin 9, AVCC = 10V Control voltage of high level VH 7.5 -- AVCC V pin 9, AVCC = 10V Note: 1. 2. 3. 4. * marks mean the number of channel 1 to 2. Please use DVDD and AVCC on same voltage. "Absolute maximum rating" means the limitation value to available to let the device destroyed. "Recommended operation conditions" indicates the conditions as which a device functions correctly. However, this doesn't guarantee the specific performance limit. 5. Moreover, "Electronic characteristics" is the electric specification of DC and AC which guarantees the specific performance limit, when the examination conditions indicated are fulfilled. Although the specification as which the limit value is not specified among parameters is not guaranteed, central value (TYP) serves as an index, which shows the performance of a device This is because these parameters are greatly dependent on evaluation board layout design / specification parts / power supply section design, and is a standard value in the board /parts of our company's specification Rev.3.0 Dec 22, 2005 page 6 of 17 M61571AFP Electronic Characteristics (Unless otherwise noted, Ta=25C, VD=18V, DVDD,AVCC=10V, Gv=18dB, Carrier Frequency=550kHz,, f = 1kHz, RL=4) DC Characteristics Parameter Symbol Limit Typ Min Max Unit Measurement Condition Circuit current VD Circuit current IVD 16 35 mA No signal (Power stage) VDD Circuit current Stand-by Circuit current IVDD ISTVD 60 80 100 250 mA A No signal (Pre-driver + Analog) Stand-by Under voltage detection Detection level of under-voltage AVCCR 6.0 7.0 V Between VDD and GND 1 V Detection Recovery TPRH TPRL 150 130 C C Note 1 IMAX 8 A Under-voltage hysteresis voltage Heating detection AVCCH Temperature of protection starting Temperature of protection release Over current detection Over current detection value 5.5 Output ON resistance of power MOS H side 300 m IF=100mA Output ON resistance Ron L side 280 m IF=100mA Note 1: The detection temperature of a heat detection circuit is the objective value at designing, and it does not guarantee the detection value. (These measurements are not checked by the temperature test.) AC Characteristics Parameter Symbol Min Limit Typ Max Unit Measurement Condition THD + N = 10% 400HzHPF, 30kHzLPF THD + N = 1% 400HzHPF, 30kHzLPF Output power1 Po1 37 W Output power2 Po2 30 W Maximum output power Pomax 50 W VD = 21V, THD + N = 10%, 30kHzLPF 400HzHPF Total harmonic distortion THD + N Output noise level Gain voltage No Gv Mute level Channel balance Mute CBAL Ripple rejection ratio Power efficiency PSRR Eff Rev.3.0 Dec 22, 2005 page 7 of 17 0.02 0.1 % Po = 15W, 400HzHPF, 30kHzLPF 16 50 18 100 20 Vrms dB A-Weighted filter Po = 1W, Analog block: Gv = 0dB -0.5 85 0 +0.5 dB dB Po = 1W, Analog block: Gv = 0dB dB % Vripple = 400mV, Fi = 1kHz Po = 30W, Fi = 1kHz, at 1ch input 60 85 M61571AFP Functional Explanation 1. System Block Diagram / 1ch AVcc = 1 0 V t y p DVDD=10Vtyp VD=18Vtyp R2 1 2 H Level Shift IN R1 1 . 5 F Renesas Original RL=4 Architectural Processor Level 1 2 H Shift 1 . 5F M61571AFP System Total Gain Gv = 20log R2 + 12 + 6 R1 Analog Stage Gain Internal Gain BTL When R1=20k , R2=75k Gv = 29.5dB Rev.3.0 Dec 22, 2005 page 8 of 17 [ dB ] M61571AFP 2. Carrier Generator This IC is built-in the functions for (1) changing a carrier frequency and (2) switching the master/slave mode. These functions can perform easily improvement adjustment of efficiency / performance / EMI performance. And, the measure is possible also for the beat problem which originates in the carrier frequency gap in the case of carrying out two or more simultaneous operation of this IC by the multi-channel system etc. (1) The setting method of Carrier frequency It is possible to set up the reference clock of PWM generator by controlled DC voltage of VCOR (12pin). That is able to change the frequency value from 300kHz to 2.0MHz. However, please evaluate enough in the case of use the carrier frequency under our recommendation value (550kHz). In the case of the conditions which made low carrier frequency and high supply voltage, please be careful for that PWM modulating operation may become unstable. CLKCTRL Carrier Input/Output SW 18 VCOR Carrier Control Voltage CLK Carrier Input/Output 12 CLKSW Carrier Generator To Internal PWM Generator 17 Carrier Frequency (kHz) <Reference Data> Carrier Control Voltage(12pin DC Voltage) vs Carrier Frequency <Condition> VD=18V, Vcc=10V, Ta=27C, RL=4 2500 2000 1500 1000 500 0 0 2 4 6 VCOR: over 0.5V Control Voltage (V) Rev.3.0 Dec 22, 2005 page 9 of 17 8 10 M61571AFP (2) The setting method of Carrier signal I/O 18pin: The mode control of a career generation circuit of operation by setup of CLKCTRL pin. The control mode has the two modes, the master mode which outputs the carrier signal generated in internal VCO to CLK terminal (17pin : CLK), and the slave mode which stops internal VCO and receives the carrier of a master chip from CLK terminal (17pin : CLK). The control table for operation mode CLKCNTL AVCC AGND CLK Output Input CLKSW ON OFF Operation Mode Master mode: Internal VCO generates carrier and sends it to slave chips. Slave mode: It receives carrier from other master chip. Note: When using two or more M61571AFP, It is possible to generate a master clock from one IC and to operate other ICs using the clock. The beat generated by the difference of the carrier frequency of each IC can be prevented. In the case of multi channel use AVCC IC1:Master 18 CLKSW 12 Carrier Generator 17 18 12 CLKSW IC2:Slave CLKSW IC3:Slave Carrier Generator 17 18 12 Carrier Generator 17 Rev.3.0 Dec 22, 2005 page 10 of 17 M61571AFP 3. Function Control This IC has Stand-by /Mute function and it is possible to control by changing the voltage of 9pin: STBY/MUTE. (1) Function setting 9 pin: Stand-by/Mute Operating Condition Output FET Condition L M Stand-by Mute Hi-Z Duty = 50% H Normal operation Normal operation (a) Stand-by While cutting off the output of all output MOSFET and muting the music play, the standby current can be made into the minimum. Moreover, at the standby mode all circuits except for the standby circuit stop completely and also stop the pulse modulation signal. So, an output noise isn't generated. (b) Mute It mutes an output signal at the same time it mutes an input signal. However, the pulse modulation signal outputs by 50% duty. (Mute level: 85dB typ.) If it turns on the mute for preventing a shock noise, it will shift to the mute status smoothly. (Soft muting function) (2) 9pin: STBY/ MUTE Control voltage range 0 Normal operation Mute Stand-by 1 2.3 5.5 7.5 10 9pin: STBY/MUTE Voltage (V) (3) Soft Muting The time of Soft Muting is decided by the external capacitor of 10pin: MUTEC. When C = 0.1F, this becomes about 50ms. We recommend the setting over 0.1F (50ms) for preventing shock sound. Soft Muting ON Normal Operation Muting ON About 50ms By External Condenser of MUTEC: 10pin (at C=0.1F) Rev.3.0 Dec 22, 2005 page 11 of 17 Mute Soft Normal Operation Muting OFF Muting OFF About 50ms By External Condenser of MUTEC: 10pin (at C=0.1F) M61571AFP 4. Protection Circuit When M61571AFP detects some protect factor, it has built-in the various protection circuits. (1) Over Current Protection Circuit This circuit protects by detecting the unusual over current of Output Power FETs. The detection current values are 8A(typ). If over current protection circuit are operated, M61571AFP makes all output FETs to " Hi-Z" state and output pins to "Open". (2) Over Temperature Protection Circuit This circuit detects unusual over temperature and protects IC (chip). It operates before reach out to thermal run away such as internal junction temperature and the protection circuit operates until it falls to the temperature of hysteresis condition. When over temperature protection circuit is operated, it makes all output FET to " Hi-Z" state and output pins to "Open". Protection start temperature: 150C typ Protection restore temperature: 130C typ (3) Under Voltage Protection Circuit This circuit detects an unusual under voltage of analog pre stage power supply and protects. When under voltage detected, it makes all output FET to " Hi-Z" state and output pins to "Open". When the transient at power ON, the power supply of AC line falls, the load impedance changes and the supply voltage falls temporarily, this is the function committed effectively and it is possible to prevent unusual destruction and to make POP sound by the unusual output into the minimum Under voltage detection voltage: 6.0V(typ) Under voltage release voltage: 7.0V(typ) (4) The table of protection circuit operation Protection Mode Protect Condition Over current protection Over temperature protection Output Stage Condition Detection current: 8A typ Protection starting: 150C typ Protection release: 130C typ Detection voltage: 6.0V Release voltage: 7.0V AVCC under voltage Hi-Z Hi-Z Hi-Z (5) The restoring from a protection state * At the case of over current protection, over temperature protection and under voltage protection The restoring from a protection state is performed automatically. While the protection is operating, restoring to normal operation is usually performed for every constant time. Then, if protection conditions are canceled, it returns to normal operation, if operation is not canceled, a protection state will usually be continued. The cycle of return operation is decided by capacity value of the capacitor linked to 14pin: VREF, and becomes about 1 second at the time of 47F (design value). For stable operation, we recommend over 10F as a capacitor value. The protection state can monitor in this oscillation condition of REF terminal. (Refer to the following figure about the restoring sequence) Internal protect signal Protection Off Protection On Protection Off 1/2AVcc (5V) VREF pin (14pin) About 1sec Operation Normal Operation Rev.3.0 Dec 22, 2005 page 12 of 17 Under Protection Normal Operation M61571AFP Notes at the time of Power ON and Power OFF When the power ON, M61571AFP automatically operates the soft mute release from the mute state by the following sequence. Timing at the power ON VD (Power Supply Voltage) AVCC 1/2VD 1/2AVCC Output Wave Envelope VREF t About 1sec PWM Output By External Capacitor of VREF: 14 pin (at C=47F) By External Capacitor of MUTEC: 10 pin (at C=0.1F) About 50ms TSTART Duty 50% TSTART means the time by reached VREF to 1/2Avcc and determined automatically by the value of capacitor CREF connected to external parts according to the following formula. TSTART = C REF AVCC 500 x 10 VREF (sec ) -6 When VCC=10V and CREF=47F, TSTART=940ms(Typ) 14 CREF Condition 1) It is necessary to set a system as a stable state by completing to charge of the input coupling capacitor C1 by TSTART. 7 C1 R2 TVC1 = 1.7 x (C1(R1+R2)) < TSTART R3 8 + R1 VC1 correspond to a signal Rev.3.0 Dec 22, 2005 page 13 of 17 1/2Vcc M61571AFP The example of an application circuit C12 0.1 F C2 47 F R10 100 C26 10 Renesas 7 8 STBY/ MUTE C35 0.1 *1 L7 22 H + + C30 2.2 + R9 20K 13 40 19 Level Shift + 21 R4 1.5K L8 22H C4 47 *B 39 C20 1 L3 12 H *B SBDi5 *C 35 34 Renesas Original 33 Architectural C10 56p C19 1 36 - L2 12 H 37 Carrier Generator 20 C24 560p RL = 4 38 18 R7 75K R3 1.5K Protect Circuit VREF 17 CLKCNTL C32 1.5 *A SBDi3 *C SBDi4 *C 42 41 16 CLK 44 43 Function Control C3 47 15 C27 10 IN2 Level Shift 12 14 + 45 + 11 C18 0.1 R13 180K - 9 10 R12 22K Processor C31 1.5 *A *2) Processor + 22 31 C11 56p 23 30 C25 560p 24 Level Shift 28 26 27 *A C34 1.5 *A SBDi7 *C 29 25 C33 1.5 SBDi6 *C *2) 32 RL = 4 L4 12 H *B SBDi8 + *C C7 47 IN1 R6 75K 46 C5 47 47 C15 0.1 Original 6 *B *C C16 0.1 + L1 12 H 48 5 Architectural R8 20K SBDi1 *C SBDi2 C23 560p C29 2.2 + 50 49 4 C9 56p R2 1.5K Level Shift 3 C8 56p VS 51 2 C22 560p C14 0.1 C18 1 52 1 R1 1.5K VD=+18V C6 47 L5 22 H + C1 47 F C17 0.1 *1 L6 22 H + C13 0.1 F 10V Reg. C21 1 C28 10 *1: *2: In the case of a substrate design, I recommend arranging in advance on the point near IC of a power supply and a GND line. So, an improvement of an audio performance (distortion and noise) and an EMI performance can be expected. The can delete, if satisfactory by prior evaluation. Since high frequency big current flows to this capacitor and diode, please arrange to an output terminal and the power supply terminal directly and consider at the time of a layout design to become the smallest possible loop. Otherwise, it becomes the cause of malfunction, performance aggravation, and destruction. Rev.3.0 Dec 22, 2005 page 14 of 17 M61571AFP Special External Parts Lists Parts No. A B C31, 32, C33, C34 L1, L2, L3, L4 Parts Name C-FILM CHOKE-COIL Type Name 1.5-50V 12H 7G09B-120M(SAGAMI ELEC CO., LTD.) Pcs 4 4 C SBDi1,2,3,4,5,6,7,8 DIODE (Shot key barrier ) RB160L40 (made by RHOM) 8 (Note1) Choke coil(*B) are consisted of Second Butterworth LPF in a pair with the capacitor(*A) of from C31 to C34, it is expressed with cut off frequency fc = 1/(2*3.14LC). Since they are the important parts which determine EMI performance and audio performance, please select after sufficient examination EMI. Especially, in order to gather electric power efficiency, we recommend the small thing of DC resistance. Moreover, when excitation current is taken into consideration, it sets at carrier frequency the o'clock of 550kHz, and it is 12H (I recommend constituting above H.). When use is carried out on high carrier frequency, it is possible to use a still smaller choke coil. Notes about mounting a) Reduction of high frequency impedance for digital GND At digital GND for pre-driver (2pin and 25pin : DGND terminal) the very big pulse current for high frequency is flowing in order to carry out the high-speed drive of the output power MOS transistor. Therefore, if the board layout design of this digital GND is bad, the high frequency noise from this PWM oscillation becomes large and has a bad influence on function operation and the analog circuit of the internal circuits. So, this may cause malfunction, performance degradation and destruction. In order to reduce the influence of this high frequency noise, it is very effective to lower the high frequency impedance of GND pattern, and we recommend to make GND pattern of a digital system to thickly GND. b) Disposal of SUB terminal (11, 16, 37, 42 pins) This IC has 4 pins of SUB terminal (11, 16, 37 and 42pin) and connects to the substrate (substrate: chip back) of IC chip. The leakage current of the high frequency generated at the timing of the edge of PWM may flow into this terminal. If the impedance of the substrate is high, noise level may become large and the parasitism transistor inside IC may operate, and malfunction may be caused. In order to avoid this, it is effective to reduce the impedance as much as possible. We recommend to connect each SUB terminal to GND which the high frequency impedance is low (DGND of the thickly GND of recommendation by a clause) c) Disposal of analog GND In order to reduce interference from the output power stage's GND (VS terminal of each bridge) and pre-driver stage of digital GND (DGND terminal) as much as possible, please connect analog GND by one point at the electric supply GND point, and consider as wiring without a common impedance. Moreover, we recommend to insert a coil/resistance (L6, R10) which separates between the GND electric supply point and high frequency if needed. d) Destructive measure Although this IC built in various protection circuits, there is a case which the unusual current occurs in output terminal at the time of a load short circuit, the output ground short and PWM operation starting. In this case, the overshoot of PWM output becomes very large. If this voltage becomes over absolute maximum supply voltage, there is a case where IC breaks. So, please design the board layout which the voltage for each terminal becomes less than the absolute maximum ratings' supply voltage (5page). In addition, please design that a guide of maximum over shoot is PWM output=under 40V and HB (Bootstrap) terminal=under 50V. Rev.3.0 Dec 22, 2005 page 15 of 17 M61571AFP The typical example of an overshoot measure (1) The bypass capacitor (Laminated ceramic capacitor) from the power supply of output power transistor (VD) to GND (VS) is arranged at the pin in near. (Recommendation: Under 1mm from the pin). (Refer to the 2 in page14) (2) Connect to Schottky barrier diode among PWM output (VD) to GND (VS). (3) Zener diode (35V) is connected between PWM output (VS terminal) to GND (VS), and it prevents so that it is prevented so that the voltage exceeding pressure prevention may not be built over a terminal. (4) Add to the Snaber circuit of CR in-series composition among the PWM output to GND (VS). Countermeasure 1:Bypass Capacitor for High Frequency Recommending position is under 1mm from pin. (nearest at a pin) (Note) We recommend to short this distance. VD HB M61571AFP VD VS OUT HB LC Filter VD Load (Speaker) VS OUT VS Countermeasure 2:Shottky barrier Diode for oppression of surge voltge (We recommend terminal proximity arrangement of IC) The design guide of the worst overshoot value at the short-circuit test OUT terminal : under +40V HB terminal : under +50V (Note) These descriptions are notes in having our company digital amplifier IC M61571AFP used, and do not guarantee all of the operation and a property. In a board design, you advise these contents and have it confirmed that operation and a property are satisfactory in your company after IC mounting. Rev.3.0 Dec 22, 2005 page 16 of 17 M61571AFP Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-HSSOP52-8.4x17.5-0.65 PRSP0052JB-B 52P9F-K 0.8g Under development F 52 27 E *1 E1 HE D2 1 Index mark 26 Reference Symbol D L *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. c Dimension in Millimeters Min Nom Max D 17.3 17.5 17.7 E 8.2 8.4 8.6 A2 A 2.0 A *3 e bp y x 2.2 A1 0 0.1 0.2 bp 0.22 0.27 0.32 c 0.23 0.25 0 A2 Detail F A1 HE 11.63 e 11.93 12.23 0.65 x 0.12 y Rev.3.0 Dec 22, 2005 page 17 of 17 0.3 10 0.10 L 0.3 0.5 0.7 D2 8.6 8.8 9.0 E1 4.6 4.8 5.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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