1
FEATURES
25ns maximum (3.3 volt supply) address access time
Dual cavity package contains two (2) 512K x 8 industry-
standard asynchronous SRAMs; the control architecture
allows operation as an 8-bit data width
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krad(Si)
- SEL Immune >80 MeV-cm2/mg
- LETTH(0.25) = >10 MeV-cm2/mg
- Saturated Cross Section cm2 per bit, 5.0E-9
- <1E-8 errors/bit-day, Adams 90% geosynchronous
heavy ion
Packaging options:
- 44-lead bottom brazed dual CFP (BBTFP) (4.6 grams)
Standard Microcircuit Drawing 5962-01532
- QML T and Q compliant part
INTRODUCTION
The QCOTSTM UT8Q1024K8 Quantified Commercial Off-the-
Shelf product is a high-performance 1M byte (8Mbit) CMOS
static RAM built with two individual 524,288 x 8 bit SRAMs
with a common output enable. Memory access and control is
provided by an active LOW chip enable (En), an active LOW
output enable (G). This device has a power-down feature that
reduces power consumption by more than 90% when deselected.
Writing to each memory is accomplished by taking one of the
chip enable (En) inputs LOW and write enable (Wn) inputs
LOW. Data on the I/O pins is then written into the location
specified on the address pins (A0 through A18). Reading from
the device is accomplished by taking one of the chip enable (En)
and output enable (G) LOW while forcing write enable (Wn)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
Only one SRAM can be read or written at a time.
The input/output pins are placed in a high impedance state when
the device is deselected (En HIGH), the outputs are disabled (G
HIGH), or during a write operation (En LOW and Wn LOW).
Figure 1. UT8Q1024K8 SRAM Block Diagram
512K x 8 512K x 8
DQ(7:0)
G
A(18:0)
E1E0
W1W0
Standard Products
QCOTSTM UT8Q1024K8 SRAM
Data Sheet
January, 2003
2
PIN NAMES
Notes:
1. To avoid bus contention, on the DQ(7:0) bus, only one En can be driven low
simultaneously while G is low.
DEVICE OPERATION
Each die in the UT8Q1024K8 has three control inputs called
Enable (En), Write Enable (Wn), and Output Enable (G); 19
address inputs, A(18:0); and eight bidirectional data lines,
DQ(7:0). The device enable (En) controls device selection,
active, and standby modes. Asserting En enables the device,
causes IDD to rise to its active value, and decodes the 19 address
inputs to each memory die. Wn controls read and write
operations. During a read cycle, G must be asserted to enable
the outputs.
Table 1. Device Operation Truth Table
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of Wn greater than VIH
(min) with En and G less
than VIL (max) defines a read cycle. Read access time is
measured from the latter of device enable, output enable, or valid
address to valid data output.
SRAM Read Cycle 1, the Address Access is initiated by a change
in address inputs while the chip is enabled with G asserted and
Wn deasserted. Valid data appears on data outputs DQ(7:0) after
the specified tAVQV is satisfied. Outputs remain active
throughout the entire cycle. As long as device enable and output
enable are active, the address inputs may change at a rate equal
to the minimum read cycle time (tAVAV).
SRAM Read Cycle 2, the Chip Enable-controlled Access is
initiated by En going active while G remains asserted, Wn
remains deasserted, and the addresses remain stable for the
entire cycle. After the specified tETQV is satisfied, the eight-bit
word addressed by A(18:0) is accessed and appears at the data
outputs DQ(7:0).
SRAM Read Cycle 3, the Output Enable-controlled Access is
initiated by G going active while En is asserted, Wn is
deasserted, and the addresses are stable. Read access time is
tGLQV unless tAVQV or tETQV have not been satisfied.
A(18:0) Address
DQ(7:0) Data Input/Output
EnDevice Enable
WnWriteEnable
GOutput Enable
VDD Power
VSS Ground
Figure 2. 25ns SRAM Pinout (44)
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
NC
E2
NC
A18
A17
A16
A15
G
DQ7
DQ6
VSS
VDD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
NC
NC
NC
NC
A0
A1
A2
A3
A4
E1
DQ0
DQ1
VDD
VSS
DQ2
DQ3
W1
A5
A6
A7
A8
A9
W2
NC
GWnEnI/O Mode Mode
X1X13-state Standby
X0 0 Data in Write
1103-state Read2
010Data out Read
3
WRITE CYCLE
A combination of Wn less than VIL(max) and En less than
VIL(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than VIH(min), or when Wn is less
than VIL(max).
Write Cycle 1, the Write Enable-controlled Access is defined
by a write terminated by Wn going high, with En still active.
The write pulse width is defined by tWLWH when the write is
initiated by Wn, and by tETWH when the write is initiated by En.
Unless the outputs have been previously placed in the high-
impedance state by G, the user must wait tWLQZ before applying
data to the eight bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the former of En or Wn going inactive.
The write pulse width is defined by tWLEF when the write is
initiated by Wn, and by tETEF when the write is initiated by the
En going active. For the Wn initiated write, unless the outputs
have been previously placed in the high-impedance state by G,
the user must wait tWLQZ before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
The UT8Q 1024K8 SRAM incorporates features which allow
operation in a limited radiation environment.
Table 2. Typical Radiation Hardness
Design Specifications1
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
Total Dose 50 krad(Si) nominal
Heavy Ion
Error Rate2<1E-8 Errors/Bit-Day
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 4.6V
VI/O Voltage on any pin -0.5 to 4.6V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 1.0W (per byte)
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -40 to +125°C
VIN DC input voltage 0V to VDD
5
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (CMOS) 2.0 V
VIL Low-level input voltage (CMOS) 0.8 V
VOL1 Low-level output voltage IOL = 8mA, VDD =3.0V 0.4 V
VOL2 Low-level output voltage IOL = 200µA,VDD =3.0V 0.08 V
VOH1High-level output voltage IOH = -4mA,VDD =3.0V 2.4 V
VOH2High-level output voltage IOH = -200µA,VDD =3.0V VDD-0.10 V
CIN1Input capacitance ƒ = 1MHz @ 0V 20 pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 24 pF
IIN Input leakage current VSS < VIN < VDD, VDD = VDD (max) -2 2µA
IOZ Three-state output leakage current 0V < VO < VDD
VDD = VDD (max)
G = VDD (max)
-2 2µA
IOS2, 3 Short-circuit output current 0V < VO < VDD -90 90 mA
IDD(OP) Supply current operating
@ 1MHz Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
150 mA
IDD1(OP) Supply current operating
@40MHz Inputs: VIL = 0.8V,
VIH = 2.0V
IOUT = 0mA
VDD = VDD (max)
220 mA
IDD2(SB) Nominal standby supply current
@0MHz Inputs: VIL = VSS
IOUT = 0mA
En = VDD - 0.5,
VDD = VDD (max)
VIH = VDD - 0.5V
4
25
mA
mA
-40°C and 25°C
+125°C
6
AC CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
Notes: * Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test.
2. Three-state is defined as a 300mV change from steady-state output voltage.
3. The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
4. The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Read cycle time 25 ns
tAVQV Read access time 25 ns
tAXQX2Output hold time 3ns
tGLQX2G-controlled Output Enable time 0ns
tGLQV G-controlled Output Enable time (Read Cycle 3) 10 ns
tGHQZ2G-controlled output three-state time 10 ns
tETQX2,3 En-controlled Output Enable time 3ns
tETQV3En-controlled access time 25 ns
tEFQZ1,2,4 En-controlled output three-state time 10 ns
{
{}
}
VLOAD + 300mV
VLOAD - 300mV
VLOAD
VH - 300mV
VL + 300mV
Active to High Z LevelsHigh Z to Active Levels
Figure 3. 3-Volt SRAM Loading
7
Assumptions:
1. En and G < V IL (max) and Wn > V IH (min)
A(18:0)
DQ(7:0)
Figure 4a. SRAM Read Cycle 1: Address Access
tAVAV
tAVQV
tAXQX
Previous Valid Data Valid Data
Assumptions:
1. G < V IL (max) and Wn > VIH (min)
A(18:0)
Figure 4b. SRAM Read Cycle 2: Chip Enable-Controlled Access
En
DATA VALID
tEFQZ
tETQX
tETQV
DQ(7:0)
Figure 4c. SRAM Read Cycle 3: Output Enable-Controlled Access
A(18:0)
DQ(7:0)
GtGHQZ
Assumptions:
1. En < VIL (max) and Wn > V IH (min)
tGLQV
tGLQX
tAVQV
DATA VALID
8
AC CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)*
(-40°C to +125°C) (VDD = 3.3V + 0.3)
Notes :
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Functional test performed with outputs disabled (G high).
2. Three-state is defined as 300mV change from steady-state output voltage.
SYMBOL PARAMETER MIN MAX UNIT
tAVAV1Write cycle time 25 ns
tETWH Device Enable to end of write 20 ns
tAVET Address setup time for write (En - controlled) 0ns
tAVWL Address setup time for write (Wn - controlled) 0ns
tWLWH Write pulse width 20 ns
tWHAX Address hold time for write (Wn - controlled) 2ns
tEFAX Address hold time for Device Enable (En - controlled) 2ns
tWLQZ2Wn- controlled three-state time 10 ns
tWHQX2Wn - controlled Output Enable time 5ns
tETEF Device Enable pulse width (En - controlled) 20 ns
tDVWH Data setup time 15 ns
tWHDX2Data hold time 2ns
tWLEF Device Enable controlled write pulse width 20 ns
tDVEF2Data setup time 15 ns
tEFDX Data hold time 2ns
tAVWH Address valid to end of write 20 ns
tWHWL1Write disable time 5ns
9
Assumptions:
1. G < VIL (max). If G > VIH (min) then Qn(8:0) will be
in three-state for the entire cycle.
2. G high for t AVAV cycle.
Wn
tAVWL
Figure 5a. SRAM Write Cycle 1: Write Enable - Controlled Access
A(18:0)
Q(7:0)
En
tAVAV2
D(7:0) APPLIED DATA
tDVWH tWHDX
tETWH
tWLWH tWHAX
tWHQX
tWLQZ
tAVWH
tWHWL
tEFDX
Assumptions & Notes:
1. G < VIL (max). If G > VIH (min) then Q(7:0) will be in three-state for the entire cycle.
2. Either En scenario above can occur.
3. G high for t AVAV cycle.
A(18:0)
Figure 5b. SRAM Write Cycle 2: Chip Enable - Controlled Access
Wn
En
D(7:0) APPLIED DATA
En
Q(7:0) tWLQZ
tETEF
tWLEF
tDVEF
tAVAV3
tAVET
tAVET
tETEF
tEFAX
tEFAX
or
10
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(1 Second Data Retention Test)
Notes:
1. En = VDD - .2V, all other inputs = VDR or VSS.
2. Data retention current (IDDR) Tc = 25oC.
3. Not guaranteed or tested.
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation)
(10 Second Data Retention Test, TC=-40oC to +125oC)
Notes:
1. Performed at VDD
(min) and VDD
(max).
2. En = VSS, all other inputs = VDR or VSS.
3. Not guaranteed or tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDR VDD for data retention 2.0 -- V
IDDR 1,2 Data retention current (per byte) -- 4.0 mA
tEFR1,3Chip select to data retention time 0ns
tR1,3Operation recovery time tAVAV ns
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
VDD1VDD for data retention 3.0 3.6 V
tEFR2, 3 Chip select to data retention time 0ns
tR2, 3 Operation recovery time tAVAV ns
VDD
DATA RETENTION MODE
tR
50%
50% VDR > 2.0V
Figure 7. Low VDD Data Retention Waveform
tEFR
En
11
12
PACKAGING
1. All exposed metalized areas must be plated per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Index mark configuration is optional.
4. Total weight is approx. 4.6 g.
Figure 9. 44-lead bottom brazed dual CFP (BBTFP) package
13
ORDERING INFORMATION
1024K8 SRAM:
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed.
4. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40°C to +125°C. Radiation neither
tested nor guaranteed.
Device Type:
- = 25ns access, 3.3V operation
Package Type:
(U) = 44-lead bottom brazed dual CFP (BBTFP)
Screening:
(P) = Prototype flow
(W) = Extended Industrial Temperature Range Flow (-40oC to +125oC)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
UT8Q1024K8 - * * * *
Aeroflex UTMC Core Part Number
14
1024K8 SRAM: SMD
5962 - 01532 * * *
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Total dose radiation must be specified when ordering.
Federal Stock Class Designator: No Options
Total Dose
(-) = None
(D) = 1E4 (10krad(Si))
(P) = 3E4 (30krad(Si)) (contact factory)
(L) = 5E4 (50krad(Si)) (contact factory)
Drawing Number: 01532
Device Type
01 = 25ns access time, 3.3V operation, Extended Industrial Temp (-40oC to +125oC)
Class Designator:
(T) = QML Class T
(Q) = QML Class Q
Case Outline:
(Y) = 44-lead dual cavity CFP
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
**
1
COLORADO
Toll Free: 800-645-8862
Fax: 719-594-8468
SE AND MID-ATLANTIC
Tel: 321-951-4164
Fax: 321-951-4254
INTERNATIONAL
Tel: 805-778-9229
Fax: 805-778-1980
WEST COAST
Tel: 949-362-2260
Fax: 949-362-2266
NORTHEAST
Tel: 603-888-3975
Fax: 603-888-4585
CENTRAL
Tel: 719-594-8017
Fax: 719-594-8468
www.aeroflex.com info-ams@aeroflex.com
Our passion for performance is defined by three
attributes represented by these three icons:
solution-minded, performance-driven and customer-focused
Aeroflex UTMC Microelectronic Systems Inc. (Aeroflex)
reserves the right to make changes to any products and
services herein at any time without notice. Consult Aeroflex
or an authorized sales representative to verify that the
information in this data sheet is current before using this
product. Aeroflex does not assume any responsibility or
liability arising out of the application or use of any product
or service described herein, except as expressly agreed to in
writing by Aeroflex; nor does the purchase, lease, or use of a
product or service from Aeroflex convey a license under any
patent rights, copyrights, trademark rights, or any other of the
intellectual rights of Aeroflex or of third parties.
