HY5V22ELMP-H - SK Hynix - Product.Network

This document is a general pro duct descriptio n and is subject to change wit hout no tice. Hyni x does no t assu me any respon sibilit y for

use of circuits described. No patent licenses are implied.

Rev. 0.3 / Mar. 2005 1

128Mb Synchronous DRAM based on 1M x 4Bank x32 I/O

Document Title

4Bank x 1M x 32bits(4Bank x1M x16 *2 Stack) Synchronous DRAM

Revision History

Revision No. History Draft Date Remark

0.1 Initial Draft Dec. 2004 Preliminary

0.2 Dec. 2004 Preliminary

0.3 1. Corrected Functional Block Diagram

2. Changed CI1 and CI2 Mar. 2005 Preliminary

Rev. 0.3 / Mar. 2005 2

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

DESCRIPTION

The Hynix HY5V22E(L)M(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory appli-

cations which require wide data I/O and high bandwidth. HY5V22E(L)M(P) is organized as 4banks of 1,048,576 x

32(organized 128M bit SDRAM into two 64M bit SDRAM).

HY5V22E(L)M(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write

cycles initiated by a single control command (Burst length of 1, 2, 4 , 8 or full page), and the burst count sequence(se-

quential or interleave). A burst of r ead or write cycles in progress can be terminated by a burst terminate command or

can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-

stricted by a '2N' rule)

FEATURES

• Voltage on VDD and VDDQ

- HY5V22E(L)M(P) Series: 3.3V

• All device pins are compatible with LVTTL interface

• 90Ball FBGA with 0.8mm of pin pitch-

HY5V22E(L)M(P) Series: 3.3V

• All inputs and outputs referenced to positive edge of

system clock

• Data mask function by DQM0, 1, 2 and 3

• Internal four banks operation

• Auto refresh and self refresh

• 4096 Refresh cycles / 64ms

• Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

• Programmable CAS Latency; 2, 3 Clocks

• Burst Read Single Write operation

Rev. 0.3 / Mar. 2005 3

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

ORDERING INFORMATION

Note:

1. HY5V22EM Series: Normal power

2. HY5V22ELM Series: Low Power

3. HY5V22E(L)M Series: Leaded 90Ball FBGA

4. HY5V22E(L)MP Series: Lead Free 90Ball FBGA

Part Number Voltage Clock

Frequency CAS

Latency Power Organization Interface 90Ball

FBGA

HY5V22EM-6

3.3V

166MHz

Normal

4Banks x

1Mbits x32 LVTTL

Leaded

HY5V22EM-H 133MHz

HY5V22ELM-6 166MHz Low

Power

HY5V22ELM-H 133MHz

HY5V22EMP-6 166MHz Normal Lead

Free

HY5V22EMP-H 133MHz

HY5V22ELMP-6 166MHz Low

Power

HY5V22ELMP-H 133MHz

Rev. 0.3 / Mar. 2005 4

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

BALL CONFIGURATION

DQ26 DQ24 VSS

DQ28 VDD

QVSSQ

VSSQ DQ27 DQ25

VSSQ DQ29 DQ30

VDD

QDQ31 NC

VSS DQM

3A3

A4 A5 A6

A7 A8 NC

CLK CKE A9

DQM

1NC NC

VDD

QDQ8 VSS

VSSQ DQ10 DQ9

VSSQ DQ12 DQ14

DQ11 VDD

QVSSQ

DQ13 DQ15 VSS

VDD DQ23 DQ21

VDD

QVSSQ DQ19

DQ22 DQ20 VDD

DQ17 DQ18 VDD

NC DQ16 VSSQ

A2 DQM

2VDD

A10 A0 A1

NC BA1 A11

BA0 /CS /RAS

/CAS /WE DQM

VDD DQ7 VSSQ

DQ6 DQ5 VDD

DQ1 DQ3 VDD

VDD

QVSSQ DQ4

VDD DQ0 DQ2

Top

View

123 789

456

Rev. 0.3 / Mar. 2005 5

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

BALL DESCRIPTIONS

SYMBOL TYPE DESCRIPTION

CLK INPUT Clock :

The system clock input. All other inputs are re gistered to the SDRAM on the rising e dge

of CLK

CKE INPUT Clock Enable:

Controls internal clock signal a nd when deactivate d, the SDRAM will be one of the states

among power down, suspend or self refresh

CS INPUT Chip Select:

Enables or disables all inputs except CLK, CKE and DQM

BA0, BA1 INPUT Bank Address:

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

A0 ~ A11 INPUT Row Address:

RA0 ~ RA11, Column Address: CA0 ~ CA7

Auto-prech arge flag: A10

RAS, CAS, WE INPUT Command Inputs:

RAS, CAS and WE define the operation

Refer function truth table for details

DQM0 ~

DQM3 I/O Data Mask:

Controls output buffers in read mode and masks input data in write mode

DQ0 ~ DQ31 I/O Data Input / Output:

Multiplexed data input / output pin

VDD / VSS SUPPLY Power supply

VDDQ / VSSQ SUPPLY I/O Power supply

NC - No connection : These pads should be left unconnected

Rev. 0.3 / Mar. 2005 6

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

FUNCTIONAL BLOCK DIAGRAM

1Mbit x 4banks x 32 I/O Synchronous DRAM (4Bank x1M x16 *2 Stack)

Row decoders

Column decoders

1Mx16 Bank0

1Mx16 Bank1

1Mx16 Bank2

1Mx16 Bank3

Memory

Cell

Array

VDD VDDQ VSS

Row decoders

Column decoders

1Mx16 Bank0

1Mx16 Bank1

1Mx16 Bank2

1Mx16 Bank3

Memory

Cell

Array

VDD VDDQ VSS

CLK

CKE

RAS

CAS

LDQM

UDQM

DQ0

DQ15

DQ16

DQ31

BA1

A11

BA0

Rev. 0.3 / Mar. 2005 7

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

BASIC FUNCTIONAL DESCRIPTION

Mode Register

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0000 OP Code 00 CAS Latency BT Burst Length

OP Code

A9 Write Mode

0Burst Read and Burst Write

1 Burst Read and Single Write Burst Type

A3 Burst Type

0Sequential

1Interleave

Burst Length

A2 A1 A0 Burst Length

A3 = 0 A3=1

000 1 1

001 2 2

010 4 4

011 8 8

1 0 0 Reserve d Reserved

1 0 1 Reserve d Reserved

1 1 0 Reserved Reserved

1 11 Full Page Reserved

CAS Latency

A6 A5 A4 CAS Latency

0 0 0 Res e r v ed

0 0 1 1

0 1 0 2

0 1 1 3

1 0 0 Reserved

1 0 1 R e s e r v e d

1 1 0 Re s e r v e d

1 1 1 Reserved

Rev. 0.3 / Mar. 2005 8

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

ABSOLUTE MAXIMUM RATING

DC OPERATING CONDITION

Note: 1. All voltages are referenced to VSS = 0V.

2. VIH(Max) is acceptable VDDQ + 2V for a pulse width with <= 3ns of duration.

3. VIL(min) is acceptable -2.0V for a pulse width with <= 3ns of duration.

AC OPERATING TEST CONDITION (TA= 0 to 70oC, VDD=3.3±0.3V / VSS=0V)

Note: 1. See Next Page

Parameter Symbol Rating Unit

Ambient Temperature TA0 ~ 70 oC

Storage Temperature TSTG -55 ~ 125 oC

Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Short Circuit Output Current IOS 50 mA

Power Dissipation PD1W

Soldering Temper atur e . Time TSOLDER 260 . 10 oC . Sec

Parameter Symbol Min Max Unit Note

Power Supply Voltage VDD, VDDQ 3.0 3.6 V 1

Input High Voltage VIH 2.0 VDDQ + 0.3 V 1, 2

Input Low Voltage VIL -0.3 0.8 V 1, 3

Parameter Symbol Value Unit Note

AC Input High / Low Level Voltage VIH / VIL 2.4 / 0.4 V

Input Timing Measurement Reference Level Voltage Vtrip 0.5 x VDDQ V

Input Rise / Fall Time tR / tF 1 ns

Output Timing Measurement Reference Level Voltage Voutref 0.5 x VDDQ V

Output Load Capacitance for Access Time Measurement CL 30 pF 1

Rev. 0.3 / Mar. 2005 9

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

CAPACITANCE (TA= 0 to 70oC, f=1MHz)

DC CHARACTERRISTICS I (TA= 0 to 70oC)

Note:

1. VIN = 0 to 3.6V, All other balls are not tested under VIN =0V

2. DOUT is disabled, VOUT=0 to 3.6

Parameter Pin Symbol Min Max Unit

Input capacitance

CLK CI1 3.5 7.5 pF

A0 ~ A11, BA0, BA1, CKE,

CS, RAS, CAS, WE CI2 3.5 7.5 pF

DQM0 ~ DQM3 CI3 2.5 5.0 pF

Data input / output capacitance DQ0 ~ DQ31 CI/O 3.0 5.5 pF

Parameter Symbol Min Max Unit Note

Input Leakage Current ILI -1 1 uA 1

Output Leakage Current ILO -1 1 uA 2

Output High Voltage VOH 2.4 - V IOH = -2mA

Output Low Voltage VOL - 0.4 V IOL = +2mA

Vtt=1.4V

RT=500 Ω

30pF

Output

DC O utput Load Circuit AC O utput Load C ircuit

Vtt=1.4V

RT=50 Ω

30pF

Output Z0 = 50Ω

Rev. 0.3 / Mar. 2005 10

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

DC CHARACTERISTICS II (TA= 0 to 70oC)

Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.

2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3. HY5V22EM(P) Series: Normal, HY5V22ELM(P) Series: Low Power

Parameter Symbol Test Condition Speed Unit Note

6 H

Operating Current IDD1 Burst length=1, One bank active

tRC ≥ tRC(min), IOL=0mA 180 170 mA 1

Precharge Standby

Current

in Power Down Mode

IDD2P CKE ≤ VIL(max), tCK = 15ns 3 mA

IDD2PS CKE ≤ VIL(max), tCK = ∞ 2mA

Precharge Standby

Current

in Non Power Down

Mode

IDD2N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V 36 mA

IDD2NS CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 30

Active Standby Cur-

rent

in Power Down Mode

IDD3P CKE ≤ VIL(max), tCK = 15ns 4 mA

IDD3PS CKE ≤ VIL(max), tCK = ∞ 3

Active Standby

Current in Non Power

Down Mode

IDD3N CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns

Input signals are changed one time during 2clks.

All other pins ≥ VDD-0.2V or ≤ 0.2V 70 mA

IDD3NS CKE ≥ VIH(min), tCK = ∞

Input signals are stable. 65

Burst Mode Operating

Current IDD4 tCK ≥ tCK(min), IOL=0mA

All banks active 180 160 mA 1

Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 260 250 mA 2

Self Refresh Current IDD6 CKE ≤ 0.2V Normal 2 mA 3

Low P ower 1

Rev. 0.3 / Mar. 2005 11

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)

Note:

1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.

2. Access time t o be measured with input s ignals of 1V/ns edge rate, f rom 0.8V to 0.2V. If t R > 1ns, then (tR/2-0.5)n s should be added

to the parameter.

Parameter Symbol 6 H Unit Note

Min Max Min Max

System Clock Cycle Time CL = 3 tCK3 6.0 1000 7.5 1000 ns

Clock High Pulse Width tCHW 2.0 - 2.5 - ns 1

Clock Low Pulse Width tCLW 2.0 - 2.5 - ns 1

Access Time From Clock CL = 3 tAC3 -5.4-5.4ns 2

Data-out Hold Time tOH 2.0 - 2.5 - ns

Data-Input Setup Time tDS 1.5 - 1.5 - ns 1

Data-Input Hold Time tDH 0.8 - 0.8 - ns 1

Address Setup Time tAS 1.5 - 1.5 - ns 1

Address Hold Time tAH 0.8 - 0.8 - ns 1

CKE Setup Time tCKS 1.5 - 1.5 - ns 1

CKE Hold Time tCKH 0.8 - 0.8 - ns 1

Command Setup Time tCS 1.5 - 1.5 - ns 1

Command Hold Time tCH 0.8 - 0.8 - ns 1

CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.5 - ns

CLK to Data Output in High-Z

Time CL = 3 tOHZ3 5.4 5.4 ns

Rev. 0.3 / Mar. 2005 12

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)

Note: 1. A new command can be given tRC after self refresh exit.

Parameter Symbol 6 H Unit Note

Min Max Min Max

RAS Cycle Time Operation tRC 60 - 63 - ns

Auto Refresh tRRC 60 - 63 - ns

RAS to CAS Delay tRCD 18 - 20 - ns

RAS Active Time tRAS 42 100K 42 100K ns

RAS Precharge Time tRP 18 - 20 - ns

RAS to RAS Bank Active Delay tRRD 12 - 15 - ns

CAS to CAS Delay tCCD 1-1-CLK

Write Command to Data-In Delay tWTL 0 - 0 - CLK

Data-in to Precharge Command tDPL 2-2-CLK

Data-In to Active Command tDAL tDPL + tRP

DQM to Data-Out Hi-Z tDQZ 2-2-CLK

DQM to Data-In Mask tDQM 0-0-CLK

MRS to New Command tMRD 2-2-CLK

Precharge to Data Output High-Z CL = 3 tPROZ3 3-3-CLK

Power Down Exit Time tDPE 1-1-CLK

Self Refresh Exit Time tSRE 1-1-CLK1

Refresh Time tREF -64-64ms

Rev. 0.3 / Mar. 2005 13

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

COMMAND TRUTH TABLE

Command CKEn-

1CKE

nCS RA

SCAS WE DQ

MADD

RA10/

AP BA Not

Mode Register Set H X L L L L X OP code

No Operation H X HXXXXX

LHHH

Bank Active H X LLHHX RA V

Read HXLHLHXCALV

Read with Autopre-

charge H

Write HXLHLLXCALV

Write with Autopre-

charge H

Precharge All Banks H X LLHLX X HX

Precharge selected

Bank LV

Burst Stop H X L H H L X X

DQM H X V X

Auto Refresh H H L L L H X X

Burst-Read-Single-

WRITE HXLLLLX A9 ball High

(Other balls OP code)

MRS

Mod

Self Refresh1

Entry H L L L L H X

Exit L H HXXXX

LHHH

Precharge

power down

Entry H L HXXXX

LHHH

Exit L H HXXXX

LHHH

Clock

Suspend Entry H L HXXXXXLVVV

Exit L H X X

Rev. 0.3 / Mar. 2005 14

11Preliminary

Synchronous DRAM Memory 128Mbit (4Mx16bit *2stack)

HY5V22E(L)M(P) Series

PACKAGE INFORMATION

90 Ball FBGA, 8mm x 13mm x 1.2mm, 0.8mm pitch

3.20

0.05 4.00

0.05

6.50 ±0.056.50 ±0.05

11.20 BSC

13.0 ±0.10

8.00

0.10

6.40 BSC

0.8

0.8(Typ)

A1 Index Mark

1.2 max

0.450

0.05

0.340

0.05

Unit [mm]

Bottom

View

Side View