[AK4420]
MS0683-E-06 2010/06
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GENERAL DESCRIPTION
The AK4420 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the
buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output.
Using AKM’s multi bit modulator architecture, the AK4420 delivers a wide dynamic range while preserving
linearity for improved THD+N performance. The AK4420 integrates a combination of switched-capacitor
and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit
word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio
applications, such as DVD, AV receiver system and set-top boxes. The AK4420 is offered in a space
saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
Switched-Capacitor Filter with High Tolerance to Clock Jitter
Single Ended 2Vrms Output Buffer
Soft mute
I/F format: 24-Bit MSB justified or I2S
Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -92dB
Dynamic Range: 105dB
Automatic Power-on Reset Circuit
Power supply: +4.5 ∼ +5.5V
Ta = -20 to 85°C (ET), -40 to 85°C (VT)
Small Package: 16pin TSSOP (6.4mm x 5.0mm)
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
AK4420
DIF
LRCK
BICK
SDTI
Audio
Data
Interface
MCLK
ΔΣ
Modulator AOUTL
8X
Interpolator
SCF
LPF
AOUTR
VDD
VSS1
Control
Interface
Clock
Divider
ΔΣ
8X
Interpolator SCF
LPF
Charge
Pump
CP CN VEE VSS2 CVDD
1μ 1μ
DZF
SMUTE
Modulator
[AK4420]
MS0683-E-06 2010/06
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■ Ordering Guide
AK4420ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AK4420VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4420 Evaluation Board for AK4420
■ Pin Layout
6
5
4
3
2
1 CN
CP
MCLK
SMUTE
BICK
SDTI
7
DIF 8
VEE
VSS2
CVDD
DZF
VSS1
VDD
AOUTL
AOUTR
AK4420
Top
View
11
12
13
14
15
16
10
9
LRCK
Compatibility with AK4421 and AK4424
AK4420 AK4421 AK4424
Digital de-emphasis - - X
I/F format 24-bit MSB justified
I²S
24-bit MSB justified
I²S I²S
Pin#3 SMUTE SMUTE DEM
Pin out Pin#8 DIF DIF SMUTE
Power Supply +4.5 ∼ +5.5V +3.0 ∼ +3.6V +4.5 ∼ +5.5V
THD+N -92dB -92dB (-3dBFS) -92dB
DR 105dB 102dB 105dB
Operating Temperature ET: -20 ∼ +85°C
VT: -40 ∼ +85°C ET: -20 ∼ +85°C ET: -20 ∼ +85°C
-: Not available
X: Available
[AK4420]
MS0683-E-06 2010/06
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PIN/FUNCTION
No. Pin Name I/O Function
1 CN I
Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor that should have the low ESR
(Equivalent Series Resistance) over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
CP pin. Non polarity capacitors can also be used.
2 CP I
Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor that should have the low ESR
(Equivalent Series Resistance) over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
CP pin. Non polarity capacitors can also be used.
3 SMUTE I Soft Mute Enable Pin (Internal pull down: 100kΩ)
“H”: Enable, “L”: Disable
4 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
5 BICK I Audio Serial Data Clock Pin
6 SDTI I Audio Serial Data Input Pin
7 LRCK I L/R Clock Pin
8 DIF I Audio Data Interface Format Pin
“L”: Left Justified, “H”: I2S
9 AOUTR O Rch Analog Output Pin
When power down, outputs VSS(0V, typ).
10 AOUTL O Lch Analog Output Pin
When power down, outputs VSS(0V, typ).
11 VDD - DAC Power Supply Pin: 4.5V∼5.5V
12 VSS1 - Ground Pin1
13 DZF O Zero Input Detect Pin
14 CVDD -
Charge Pump Power Supply Pin: 4.5V∼5.5V
15 VSS2 - Ground Pin2
16 VEE O
Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR
(Equivalent Series Resistance) over all temperature range. When this
capacitor has the polarity, the positive polarity pin should be connected to the
VSS2 pin. Non polarity capacitors can also be used.
Note: All input pins except for the CN pin should not be left floating.
[AK4420]
MS0683-E-06 2010/06
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ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD
CVDD
-0.3
-0.3
+6.0
+6.0
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 VDD+0.3 V
AK4420ET Ta -20 85 °C
Ambient Operating Temperature
AK4420VT Ta -40 85 °C
Storage Temperature Tstg -65 150 °C
Note 1. All voltages with respect to ground.
Note 2. VSS1, VSS2 connect to the same analog grand.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply
VDD
CVDD
+4.5
+5.0
VDD
+5.5
V
Note 3. CVDD should be equal to VDD
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4420]
MS0683-E-06 2010/06
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ANALOG CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 4)
fs=44.1kHz, BW=20kHz -92 -84 dB
fs=96kHz, BW=40kHz -92 - dB
THD+N (0dBFS)
fs=192kHz, BW=40kHz -92 - dB
Dynamic Range (-60dBFS with A-weighted. (Note 5) 98 105 dB
S/N (A-weighted. (Note 6) 98 105 dB
Interchannel Isolation (1kHz) 90 100 dB
Interchannel Gain Mismatch 0.2 0.5 dB
DC Accuracy
DC Offset (at output pin) -60 0 +60 mV
Gain Drift 100 - ppm/°C
Output Voltage (Note 7) 1.97 2.12 2.27 Vrms
Load Capacitance (Note 8) 25 pF
Load Resistance 5 kΩ
Power Supplies
Power Supply Current: (Note 9)
Normal Operation (fs≤96kHz)
Normal Operation (fs=192kHz)
Power-Down Mode (Note 10)
24
27
10
36
40
100
mA
mA
μA
Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 5. 98dB for 16bit input data
Note 6. S/N does not depend on input data size.
Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD,
AOUT (typ.@0dB) = 2.12Vrms × VDD/5.
Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load.
Note 9. The current into VDD and CVDD.
Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD
[AK4420]
MS0683-E-06 2010/06
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FILTER CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz)
Parameter Symbol min Typ max Units
Digital filter
Passband ±0.05dB (Note 11)
–6.0dB
PB 0
-
22.05
20.0
-
kHz
kHz
Stopband (Note 11) SB 24.1 kHz
Passband Ripple PR ± 0.02 dB
Stopband Attenuation SA 54 dB
Group Delay (Note 12) GD - 19.3 - 1/fs
Digital Filter + LPF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.05
± 0.05
± 0.05
-
-
-
dB
dB
dB
Note 11. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data
of both channels to input register to the output of the analog signal.
DC CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
2.2
-
-
-
-
0.8
V
V
High-Level Output Voltage (Iout = -80uA)
Low-Level Output Voltage (Iout = 80uA)
VOH
VOL
VDD-0.4
-
-
-
-
0.4
V
V
Input Leakage Current (Note 13) Iin - -
± 10 μA
Note 13. The SMUTE pin is not included. The SMUTE pin has internal pull-down resistor (typ.100kΩ).
[AK4420]
MS0683-E-06 2010/06
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SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V)
Parameter Symbol min Typ max Units
Master Clock Frequency
Duty Cycle
fCLK
dCLK
4.096
30
11.2896
36.864
70
MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
32
120
45
48
96
192
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 14)
LRCK Edge to BICK “↑” (Note 14)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
[AK4420]
MS0683-E-06 2010/06
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■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Figure 1. Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Figure 2. Serial Interface Timing
[AK4420]
MS0683-E-06 2010/06
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OPERATION OVERVIEW
■ System Clock
The external clocks required to operate the AK4420 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the internal master
clock is set to the appropriate frequency (Table 1).
The AK4420 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,
and the analog output is forced to 0V(typ). When MCLK and LRCK are input again, the AK4420 is powered up. After
power-up, the AK4420 is in the power-down mode until MCLK and LRCK are input.
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
32.0kHz 8.192 12.288
44.1kHz 11.2896 16.9344
48.0kHz 12.288 18.432
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - -
Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - - Quad
Table 1. System Clock Example
When MCLK= 256fs/384fs, the AK4420 supports sampling rate of 32kHz~96kHz (Table 1). However, when the
sampling rate is 32kHz~48kHz, DR and S/N will degrade as compared to when MCLK= 512fs/768fs. (Table 2)
MCLK DR,S/N
256fs/384fs 102dB
512fs/768fs 105dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■ Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial
data modes as shown in Table 3. In all modes the serial data is MSB-first, two’s complement format and it is latched on
the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin.
Mode DIF SDTI Format BICK Figure
0 L 24bit MSB justified ≥48fs Figure 3
1 H 24bit I2S ≥48fs Figure 4
Table 3. Audio Data Formats
[AK4420]
MS0683-E-06 2010/06
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LRCK
BICK
(
64fs
)
SDTI
0 22 1 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care 23
Lch Data Rch Data
23 30 222 24 23 30
22 1 0Don’t care
23 2223
Figure 3. Mode 0 Timing
LRCK
BICK
(
64fs
)
SDTI
0 3 1 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0Don’t care
23
Lch Data Rch Data
23 25 3224 23 25
22 1 0 Don’t care 23 23
Figure 4. Mode 1 Timing
■ Zero Detect Function
When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. The DZF
pin immediately returns to “L” if the input data for both channels are not zero.
[AK4420]
MS0683-E-06 2010/06
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■ Analog Output Block
The internal negative power supply generation circuit (Figure 5) provides a negative power supply for the internal 2Vrms
amplifier. It allows the AK4420 to output an audio signal centered at VSS (0V, typ) as shown in Figure 6. The negative
power generation circuit (Figure 5) needs 1.0uF capacitors (Ca, Cb) with low ESR (Equivalent Series Resistance). If this
capacitor is polarized, the positive polarity pin should be connected to the CP and VSS2 pins. This circuit operates by
clocks generated from MCLK. When MCLK stops, the AK4420 is placed in the reset mode automatically and the analog
outputs settle to VSS (0V, typ).
CVDD
Charge
Pump
CP CN VSS2 VEE
1uF
1uF
Negative Power
A
K4420
(+) Cb
Ca (+)
Figure 5. Negative Power Generation Circuit
A
OUTR
A
K4420
(AOUTL)
0V
2.12Vrms
Figure 6. Audio Signal Output
[AK4420]
MS0683-E-06 2010/06
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■ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE pin is set “H”, the output signal is attenuated to
-∞ in 1024 LRCK cycles. When the SMUTE pin is returned to “L”, the mute is cancelled and the output attenuation
gradually changes to 0dB in 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after starting
this operation, the attenuation is discontinued and it is returned to 0dB by the same cycle. Soft mute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin
A
ttenuation
DZF pin
1024/fs
0dB
-∞
A
OUT
1024/fs
8192/fs
GD GD
(1)
(2)
(3)
(4)
Notes:
(1) The time for input data be attenuation to -∞, is
Normal Speed Mode: 1024 LRCK cycles (1024/fs).
Double Speed Mode: 2048 LRCK cycles (2048/fs).
Quad Speed Mode : 4096 LRCK cycles (4096/fs).
(2) The analog output corresponding to a specific digital input has a group delay, GD.
(3) If soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level in the same cycle.
(4) When the input data for both channels are continuously zeros for 8192 LRCK cycles, the DZF pin is set to “H”. The
DZF pin immediately is set to “L” if the input data are not zero after going to DZF “H”.
Figure 7. Soft Mute and Zero Detect Function
[AK4420]
MS0683-E-06 2010/06
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■ System Reset
The AK4420 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.
The AK4420 is in power-down mode until LRCK are input.
Notes:
(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.
(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.
(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal
after Time A.
Time A = 1024/ (fs x 16): Normal speed mode
Time A = 1024/ (fs x 8) : Double speed mode
Time A = 1024/ (fs x 4) : Quadruple speed mode
(4) No audible click noise occurs under normal conditions.
(5) The DZF pin is “L” in the power-down mode.
(6) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power
supply voltage achieves 80% of VDD. If not, click noise may occur at a different time from this figure.
Figure 8. System Reset Diagram
D/A Out
(Analog)
MCLK
DZF
20 us
Low
Power Supply
(VDD, CVDD)
2, 3
LRCK
Digital
Circuit
Analog
Circuit
Charge Pump
Circuit
Charge Pump
Counter circuit
Time A
(1)
(2)
(3)
(5)
Power-up
Power-up
“0” data
D/A In
(
Di
g
ital
)
MUTE
(
D/A Out
)
(4)
(6)
Power down
Power down
Power-up Power down
[AK4420]
MS0683-E-06 2010/06
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■ Reset Function
When the MCLK or LRCK stops, the AK4420 is placed in reset mode and its analog outputs are set to VSS (0V, typ).
When the MCLK and LRCK are restarted, the AK4420 returns to normal operation mode. The BICK can be stopped
when MCLK or LRCK is stopped, but it must not be stopped when MCLK and LRCK are supplied.
Normal Operation
Internal
State Reset Normal Operation
GD
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(1)
VSS
(2)
MCLK Stop
(3) (3)
(4)
Clock In
MCLK, BICK, LRCK LRCK Stop
(4)
<Case1:MCLK Stop>
<Case2:LRCK Stop>
(5)
DZF (6)
DZF (6)
Notes:
(1) Digital data can be stopped. The click noise after MCLK and LRCK are input again can be reduced by inputting
the “0” data during this period.
(2) The analog output corresponding to a specific digital input has group delay (GD).
(3) No audible click noise occurs under normal conditions.
(4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(5) The AK4420 detects the stop of LRCK if LRCK stops for more than 2048/fs. When LRCK is stopped, the
AK4420 exits reset mode after LRCK is inputted..
(6) The DZF pin is set to “L” in the reset mode.
Figure 9. Reset Timing Example
[AK4420]
MS0683-E-06 2010/06
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SYSTEM DESIGN
Figure 10 shows the system connection diagram. An evaluation board (AKD4420) is available for fast evaluation as well
as suggestions for peripheral circuitry.
Note:
Use low ESR (Equivalent Series Resistance) capacitors. When using polarized capacitors, the positive polarity pin
should be connected to the CP and VSS2 pin.
VSS1 and VSS2 should be separated from digital system ground.
Digital input pins should not be allowed to float.
Figure 10. Typical Connection Diagram
Analog
5.0V
24bit Audio Data
1u (1)
64fs
Master Clock External Mute Circuits
Analog Ground
Digital Ground
+
Mode-
Setting
AK4420
DIF
SDTI
BICK
MCLK
SMUTE
CP
CN
LRCK
AOUTR
AOUTL
VDD
VSS1
DZF
CVDD
VSS2
VEE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+
+
fs
1u (1)
0.1u 10u
+
0.1u 10u
Lch Out
Rch Out
10Ω
[AK4420]
MS0683-E-06 2010/06
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1. Grounding and Power Supply Decoupling
VDD, CVDD and VSS are supplied from the analog supply and should be separated from the system digital supply.
Decoupling capacitors, especially 0.1μF ceramic capacitors for high frequency bypass, should be placed as near to VDD
and CVDD as possible. The differential voltage between VDD and VSS pins set the analog output range. The power-up
sequence between VDD and CVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VSS (ground) voltage. The output signal range is typically
2.12Vrms (typ @VDD=5V). The internal switched-capacitor filter (SCF) and continuous-time filter (CTF) attenuate the
noise generated by the delta-sigma modulator beyond the audio passband. Using single a 1st-order LPF (Figure 11) can
reduce noise beyond the audio passband. Figure 12 shows example in the case of 10kΩ, 100kΩ terminus.
The output voltage is a positive full scale for 7FFFFFH (@24bit data) and a negative full scale for 800000H (@24bit
data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is ±60mV or less.
AOUT
470
2.2nF
AK4420
2.12Vrms (typ)
Analog
Out
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 11. External 1st order LPF Circuit Example1
AOUT
820
1000pF
AK4420
Analog
Out
220
10kÆ1.92Vrms (typ)
100kÆ2.1Vrms (typ)
47μ
47k
Figure 12. External 1st order LPF Circuit Example2
[AK4420]
MS0683-E-06 2010/06
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PACKAGE
0-10°
Detail A
Seating Plane
0.10
0.17±0.05
0.22±0.1 0.65
*5.0±0.1 1.1 (max)
A
1 8
9 16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
[AK4420]
MS0683-E-06 2010/06
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MARKING
AKM
4420ET
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4420ET
4) Asahi Kasei Logo
AKM
4420VT
XXYYY
5) Pin #1 indication
6) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
7) Marketing Code : 4420VT
8) Asahi Kasei Logo
[AK4420]
MS0683-E-06 2010/06
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REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents
07/11/05 00 First Edition
07/12/04 01 13 Figure 8.
The description of the click noise was corrected.
Error
Correction
14 Figure 9.
The description of the click noise was corrected.
07/12/17 02
Error
Correction
14 “The BICK can be stopped when MCLK or LRCK is
stopped, but it must not be stopped when MCLK and LRCK
are supplied.” was deleted.
1 FEATURE(Ta)
AK4420VT was added.
2 Ordering Guide
AK4420VT was added
2 “Compatibility with AK4421 and AK4424” was added
4 ABSOLUTE MAXIMUM RATINGS
(Ambient Operating Temperature)
AK4420VT was added.
Spec
Addition
18 MARKING
AK4420VT was added.
6 Note13
pull-up -> pull down
08/04/01 03
Error
Correction 12 Normal Speed Mode:
1024 LRCK cycles (1020/fs) -> (1024/fs)
08/06/11 04
Error
Correction
1 FEATURES
“Digital de-emphasis” was deleted.
08/08/01 05
Error
Correction 6
DC CHARACTERISTICS
A row for the output voltage value was written as for input
High-Level Input Voltage → High-Level Output Voltage
Low-Level Input Voltage → Low-Level Output Voltage
VIH → VOH
VIL → VOL
A cross-reference to Note 13 was added.
10/06/23 06
Error
Correction 9 ■ System Clock
A description was changed.
Specification
Change 17 PACKAGE
A package drawing dimension was changed.
[AK4420]
MS0683-E-06 2010/06
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IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
