Virtex™ 2.5 V Field Programmable Gate Arrays
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DS003-2 (v2.6) July 19, 2001 www.xilinx.com Module 2 of 4
Product Specification 1-800-255-7778 11
with a comm on user interface regardless of their choice of
entry and verification tools. The XDM software simplifies the
selection of implementation options with pull-down menus
and on-line help.
Application programs ranging from schematic capture to
Placement and Routing (PAR) can be accessed through the
XDM so ftware. The program com mand se que nce is ge ner-
ated prior to execution, and stored for documentation.
Several advanced software f eatures facilitate Virtex design.
RPMs, for example, are schematic-based macros with rela-
tive location constraints to guide their placement. They help
ensure optimal implementation of common functions.
F or HDL design entry, the Xilinx FPGA Foundation develop-
ment system provides interfaces to the following synthesis
design environments.
•Synopsys (FPGA Compiler, FPGA Express)
•Exemplar (Spectrum)
•Synplicity (Synplify)
For schematic design entry, the Xilinx FPGA Foundation
and alliance development system provides interfaces to the
following schematic-capture design environments.
•Mentor Graphics V8 (Design Architect, QuickSim II)
•Viewlogic Systems (Viewdraw)
Third-party vendors support many other environments.
A standard interface-file specification, Electronic Design
Interchange Format (EDIF), simplifies file transfers into and
out of the development system.
Virtex FPGAs supported by a unified library of standard
functions. This library contains ov er 400 primitives and mac-
ros, ranging from 2-input AND gates to 16-bit accumulators,
and includes arithmetic functions, comparators, counters,
data registers, decoders, encoders, I/O functions, latches,
Boolean functions, multiplexers, shift registers, and barrel
shifters.
The “soft macro” portion of the library contains detailed
descriptions of common logic functions, but does not con-
tain any partitioning or placement information. The perfor-
mance of these macros depends, therefore, on the
partitioning and placement obtained during implementation.
RPMs, on the other hand, do contain predetermined par ti-
tioning and placement information that permits optimal
implementation of these functions. Users can create their
own library of soft macros or RPMs based on the macros
and primitives in the standard library.
The design environment supports hierarchical design entry,
with high-level schematics that comprise major functional
blocks, while lower-level schematics define the logic in
these blocks. These hierarchi ca l desi gn el em ents ar e au to-
matically combined by the implementation tools. Different
design entry tools can be combined within a hierarchical
design, thus allowing the most convenient entr y method to
be used for each portion of the design.
Design Implementation
The place-and-route tools (PAR) automatically provide the
implementation flow described in this section. The parti-
tioner takes the EDIF net list for the design and maps the
logic into the architectural resources of the FPGA (CLBs
and IOBs, for example). The placer then determines the
best loc ations for these blocks bas ed on their int erconnec-
tions and the de sired perfor mance. Finally, the router inter-
connects the blocks.
The PAR algorithms support fully automatic implementation
of most desig ns. For demanding app licatio ns, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optio nal ly s pecifi ed during the desi gn- e ntry proc es s. The
implementation of highly structured designs can benefit
greatly from basic floor planning.
The imp lementation so ftware in cor porates Timing Wizard®
timing-driv en placement and routing. Designers specify tim-
ing requirements along entire paths during design entry.
The timing path analysis routines in PAR then recognize
these user-specified requirements and accommodate them.
Timing r equirements a re entered on a schematic in a for m
directly relating to the system requirements, such as the tar-
geted clock frequency, or the maximum allowable delay
between two registers. In this way, the overall perfor mance
of the s yst em al ong e ntire sig nal p aths is auto mat ically tai-
lored to user-generated specifications. Specific timing inf or-
mation for individual nets is unnecessary.
Design Verification
In addition to conv entional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infi nitel y re programma ble, designs can be veri-
fied in rea l time wi thout the n eed for extensive sets of soft-
ware simulation vectors.
The dev elopment system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post -layout timing i nfor matio n from the
design database, and back-annotates this information into
the net list for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
TRACE® static timing analyzer.
For in-circuit debugging, the development system includes
a download and readback cable. This cable connects the
FPGA in the target system to a PC or workstation. After
downloading the design into the FPGA, the designer can
single-step the logic, readback the contents of the flip-flops,
and so observe the internal logic state. Simple modifica-
tions can be downloaded into the system in a matter of min-
utes.