February 1996
NDS9953A
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
________________________________________________________________________________
Absolute Maximum Ratings TA= 25°C unless otherwise noted
Symbol Parameter NDS9953A Units
VDSS Drain-Source Voltage -30 V
VGSS Gate-Source Voltage ± 20 V
IDDrain Current - Continuous (Note 1a) ± 2.9 A
- Pulsed ± 10
PDPower Dissipation for Dual Operation 2W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
NDS9953A.SAM
-2.9A, -30V. RDS(ON) = 0.13Ω @ VGS = -10V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as notebook computer power management
and other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
1
5
6
7
8
4
3
2
© 1997 Fairchild Semiconductor Corporation
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
IDSS Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -2 µA
TJ = 55°C -25 µA
IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.6 -2.8 V
TJ = 125°C -0.85 -1.25 -2.5
RDS(ON) Static Drain-Source On-Resistance VGS = -10 V, ID = -1.0 A 0.11 0.13 Ω
TJ = 125°C 0.15 0.21
VGS = -4.5 V, ID = -0.5 A 0.17 0.2
TJ = 125°C 0.24 0.32
ID(on) On-State Drain Current VGS = -10 V, VDS = -5 V -10 A
VGS = -4.5 V, VDS = -5 V -1.5
gFS Forward Transconductance VDS = -15 V, ID = -2.9 A 4S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
350 pF
Coss Output Capacitance 260 pF
Crss Reverse Transfer Capacitance 100 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on) Turn - On Delay Time VDD = -10 V, ID = -1 A,
VGEN = -10 V, RGEN = 6 Ω9 40 ns
trTurn - On Rise Time 21 40 ns
tD(off) Turn - Off Delay Time 21 90 ns
tfTurn - Off Fall Time 8 50 ns
QgTotal Gate Charge VDS = -10 V,
ID = -2.9 A, VGS = -10 V
10 25 nC
Qgs Gate-Source Charge 1.6 nC
Qgd Gate-Drain Charge 3.4 nC
NDS9953A.SAM
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current -1.2 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.25 A (Note 2)-0.8 -1.3 V
trr Reverse Recovery Time VGS = 0 V, IF = -1.25 A, dIF/dt = 100 A/µs 100 ns
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD(t)=TJ−TA
RθJA
(t)=TJ−TA
RθJC
+RθCA
(t)=ID
2(t)×RDS(ON)TJ
Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9953A.SAM
1a 1b 1c
NDS9953A.SAM
-5-4-3-2-10
-20
-15
-10
-5
0
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
V = -10V
GS
DS
D
-4.0
-6.0
-5.0
-4.5
-7.0
-3.5
-8.0
-3.0
-5.5
-50 -25 025 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = -10V
GS
I = -2.9A
D
R , NORMALIZED
DS(ON)
-50 -25 025 50 75 100 125 150
0.7
0.8
0.9
1
1.1
1.2
T , JUNCTION TEMPERATURE (°C)
GATE-SOURCE THRESHOLD VOLTAGE
I = -250µA
D
V = V
DS GS
J
V , NORMALIZED
th
-15-12-9-6-30
0.5
1
1.5
2
2.5
3
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
D
R , NORMALIZED
DS(on)
V = -3.5V
GS
-10
-6.0
-4.0
-8.0
-7.0
-5.0
-4.5
-5.5
-15-12-9-6-30
0.5
1
1.5
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
T = 125°C
J
25°C
-55°C
D
V = -10V
GS
R , NORMALIZED
DS(on)
Typical Electrical Characteristics
Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with
Temperature.
-6-5-4-3-2-1
-10
-8
-6
-4
-2
0
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
V = -10V
DS
GS
D
T = -55°C
J25°C 125°C
NDS9953A.SAM
-50 -25 025 50 75 100 125 150
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE BREAKDOWN VOLTAGE
I = -250µA
D
BV , NORMALIZED
DSS
J
0.2 0.4 0.6 0.8 11.2 1.4
0.001
0.01
0.1
0.5
1
5
10
-V , BODY DIODE FORWARD VOLTAGE (V)
-I , REVERSE DRAIN CURRENT (A)
T = 125°C
J25°C
-55°C
V = 0V
GS
SD
S
0 2 4 6 8 10 12
0
2
4
6
8
10
Q , GATE CHARGE (nC)
-V , GATE-SOURCE VOLTAGE (V)
g
GS
I = -2.9A
DV = -10V
DS -20V
-15V
0.1 0.2 0.5 1 2 5 10 30
50
100
200
300
500
800
1000
-V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
Figure 7. Breakdown Voltage Variation with
Temperature.
Figure 8. Body Diode Forward Voltage
Variation with Current and Temperature.
Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristic.
Typical Electrical Characteristics (continued)
-10-8-6-4-20
0
1
2
3
4
5
6
I , DRAIN CURRENT (A)
g , TRANSCONDUCTANCE (SIEMENS)
T = -55°C
J
25°C
125°C
V = -15V
DS
D
FS
Figure 11. Transconductance Variation with Drain
Current and Temperature.
NDS9953A.SAM
Typical Thermal Characteristics
00.2 0.4 0.6 0.8 1
0.5
1
1.5
2
2.5
2oz COPPER MOUNTING PAD AREA (in )
STEADY-STATE POWER DISSIPATION (W)
2
1c
1b
4.5"x5" FR-4 Board
T = 25 C
Still Air
Ao
Power for Single Operation
Total Power for Dual Operation
1a
Figure 12. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
00.1 0.2 0.3 0.4 0.5
1
2
3
4
5
2oz COPPER MOUNTING PAD AREA (in )
I , STEADY-STATE DRAIN CURRENT (A)
2
1c
1b
1a
4.5"x5" FR-4 Board
T = 25 C
Still Air
V = -10V
Ao
GS
D
Figure 13. Maximum Steady-State Drain
Current versus Copper Mounting Pad
Area.
0.1 0.2 0.5 1 2 5 10 30 50
0.01
0.03
0.1
0.3
1
3
10
30
- V , DRAIN-SOURCE VOLTAGE (V)
-I , DRAIN CURRENT (A)
DS
D
RDS(ON) LIMIT
1s
100ms
10s
DC
10ms
1ms
100us
V = -10V
SINGLE PULSE
R = See Note 1c
T = 25°C
GS
A
θJA
Figure 14. Maximum Safe Operating Area.
0.0001 0.001 0.01 0.1 110 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
Duty Cycle, D = t / t
12
R (t) = r(t) * R
R = See Note 1c
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2
Figure 15. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
TRADEMARKS
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST
FASTr™
GTO™
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
VCX™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench
QFET™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
Rev. E
