ADAU1978WBCPZ-RL - Analog Devices

Quad Analog-to-Digital Converter (ADC)

Data Sheet

ADAU1978

Rev. A

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FEATURES

Four 2 V rms differential inputs

On-chip phase-locked loop (PLL) for master clock

Low electromagnetic interference (EMI) design

109 dB analog-to-digital converter (ADC) dynamic range

Total harmonic distortion + noise (THD + N): −95 dB

Selectable digital high-pass filter

24-bit stereo ADC with 8 kHz to 192 kHz sample rates

Digital volume control with autoramp function

I2C/SPI controllable for flexibility

Software-controllable clickless mute

Software power-down

Right justified, left justified, I2S, and TDM modes

Master and slave operation modes

40-lead LFCSP package

Qualified for automotive applications

APPLICATIONS

Automotive audio systems

Active noise cancellation systems

GENERAL DESCRIPTION

The ADAU1978 incorporates four high performance, analog-to-

digital converters (ADCs) with 2 V rms capable ac-coupled inputs.

The ADCs use a multibit sigma-delta (Σ-Δ) architecture with

continuous time front end for low EMI. An I2C/serial peripheral

interface (SPI) control port is included that allows a microcontroller

to adjust volume and many other parameters. The ADAU1978

uses only a single 3.3 V supply. The part internally generates the

required digital DVDD supply. The low power architecture

reduces the power consumption. The ADAU1978 is available in

a 40-lead LFCSP package. The on-chip PLL can derive the master

clock from an external clock input or frame clock (sample rate

clock). When fed with the frame clock, it eliminates the need

for a separate high frequency master clock in the system.

Note that throughout this data sheet, multifunction pins, such

as SCL/CCLK, are referred to either by the entire pin name or

by a single function of the pin, for example, CCLK, when only

that function is relevant.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

AVDD2

REF

PRO GRAMMABLE G AIN

DECIMATOR/HPF

DC CALIBRATION

SERIAL AUDIO P ORT

VREF

MCLKIN

PLL_FILT

AVDD1

AVDD3

AVDD2

DGND

AGND3

AGND2

AGND1

AGND6

AGND5

AGND4

SA_MODE

PLL

AGND2

DVDD

IOVDD

LRCLK

BCLK

SDATAOUT1

SDATAOUT2

3.3V TO 1.8V

REGULATOR

ADAU1978

11292-001

SCL/CCLK

SDA/COUT

ADDR1/CIN

ADDR0/CLATCH

PD/RST

I2C/SPI

CONTROL

AGND1

AGND2

AGND3

AIN1P

AIN1N

AIN2P

AIN2N

AIN3P

AIN3N

AIN4P

AIN4N

ADC

AVDD1

AVDD3

ADAU1978 Data Sheet

Rev. A | Page 2 of 44

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Analog Performance Specifications ........................................... 3

Digital Input/Output Specifications........................................... 3

Power Supply Specifications........................................................ 4

Digital Filter Specifications ......................................................... 4

Timing Specifications .................................................................. 5

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 12

Overview ...................................................................................... 12

Power Supply and Voltage Reference ....................................... 12

Power-On Reset Sequence ........................................................ 12

PLL and Clock ............................................................................. 13

Analog Inputs .............................................................................. 14

ADC ............................................................................................. 16

ADC Summing Modes .............................................................. 16

Serial Audio Data Output Ports, Data Format ....................... 17

Control Ports ................................................................................... 21

I2C Mode ...................................................................................... 22

SPI Mode ..................................................................................... 25

Master Power and Soft Reset Register ..................................... 28

PLL Control Register ................................................................. 29

Block Power Control and Serial Port Control Register ......... 30

Serial Port Control Register 1 ................................................... 31

Serial Port Control Register 2 ................................................... 32

Channel 1 and Channel 2 Mapping for Output Serial Ports

Channel 3 and Channel 4 Mapping for Output Serial Ports

Serial Output Drive and Overtemperature Protection Control

Post ADC Gain Channel 1 Control Register .......................... 37

Post ADC Gain Channel 2 Control Register .......................... 38

Post ADC Gain Channel 3 Control Register .......................... 38

Post ADC Gain Channel 4 Control Register .......................... 39

High-Pass Filter and DC Offset Control Register and Master

Mute Register .............................................................................. 40

ADC Clipping Status Register .................................................. 41

Digital DC High-Pass Filter and Calibration Register .......... 42

Typical Application Circuit ........................................................... 43

Outline Dimensions ....................................................................... 44

Ordering Guide .......................................................................... 44

Automotive Products ................................................................. 44

REVISION HISTORY

1/14—Rev. 0 to Rev. A

Change to Features Section ............................................................. 1

Change to Dynamic Range (A-Weighted) Line Input

Parameter, Table 1 ............................................................................. 3

Change to Figure 9 ......................................................................... 10

Change to Figure 34 ....................................................................... 23

Changes to Figure 44 ...................................................................... 43

5/13—Revision 0: Initial Version

Data Sheet ADAU1978

Rev. A | Page 3 of 44

SPECIFICATIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

AVDDx/IOVDD = 3.3 V; DVDD (internally generated) = 1.8 V; TA = −40°C to +105°C, unless otherwise noted. Master clock = 12.288 MHz

(48 kHz fS, 256 × fS mode); input sample rate = 48 kHz; measurement bandwidth = 20 Hz to 20 kHz; word width = 24 bits; load capacitance

(digital output) = 20 pF; load current (digital output) = ±1 mA; digital input voltage high = 2.0 V; and digital input voltage low = 0.8 V.

ANALOG PERFORMANCE SPECIFICATIONS

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

LINE INPUT

Full-Scale AC Differential Input Voltage 2 V rms

Full-Scale Single-Ended Input Voltage 1 V rms

Input Common-Mode Voltage VIN, cm at AINxP/AINxN pins 1.5 V dc

ANALOG-TO-DIGITAL CONVERTERS

Differential Input Resistance Between AINxP and AINxN 28.6 kΩ

Single-Ended Input Resistance Between AINxP and AINxN 14.3 kΩ

ADC Resolution 24 Bits

Dynamic Range (A-Weighted) Line Input1 Input = 1 kHz, −60 dBFS (0 dBFS = 2 V rms input) 103 109 dB

Total Harmonic Distortion + Noise (THD + N)

Input = 1 kHz, −1 dBFS (0 dBFS = 2 V rms input)

−95

−88

Digital Gain Post ADC 0 60 dB

Gain Error −10 +10 %

Interchannel Gain Mismatch −0.25 +0.25 dB

Gain Drift 100 ppm/°C

Common-Mode Rejection Ratio (CMRR) 200 mV rms, 1 kHz 50 65 dB

200 mV rms, 20 kHz 56 dB

Power Supply Rejection Ratio (PSRR) 100 mV rms, 1 kHz on AVDD = 3.3 V 70 dB

Interchannel Isolation 100 dB

Interchannel Phase Deviation 0 Degrees

REFERENCE

Internal Reference Voltage VREF pin 1.47 1.50 1.54 V

Output Impedance 20 kΩ

ADC SERIAL PORT

Output Sample Rate 8 192 kHz

1 This is for a sampling frequency, fS, ranging from 44.1 kHz to 192 kHz.

DIGITAL INPUT/OUTPUT SPECIFICATIONS

Table 2.

Parameter Test Conditions/Comments Min Typ Max Unit

INPUT

High Level Input Voltage (VIH) 0.7 × IOVDD V

Low Level Input Voltage (VIL) 0.3 × IOVDD V

Input Leakage Current −10 +10 µA

Input Capacitance

OUTPUT

High Level Output Voltage (V

)

= 1 mA

IOVDD − 0.60

Low Level Output Voltage (VOL) IOL = 1 mA 0.4 V

ADAU1978 Data Sheet

Rev. A | Page 4 of 44

POWER SUPPLY SPECIFICATIONS

AVDD = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V, and fS = 48 kHz (master mode), unless otherwise noted.

Table 3.

Parameter Test Conditions/Comments Min Typ Max Unit

SUPPLY

DVDD On-chip low dropout (LDO) regulator 1.62 1.8 1.98 V

AVDDx AVDD 3.0 3.3 3.6 V

IOVDD IOVDD 1.62 3.3 3.6 V

IOVDD CURRENT Master clock = 256 × fS

Normal Operation fS = 48 kHz 450 µA

fS = 96 kHz 880 µA

fS = 192 kHz 1.75 mA

Power-Down

= 48 kHz to 192 kHz

µA

AVDDx CURRENT

Normal Operation 4-channel ADC, DVDD internal 14 mA

4-channel ADC, DVDD external 9.5 mA

Power-Down 270 µA

DVDD CURRENT

Normal Operation DVDD external 4.5 mA

Power-Down 65 µA

POWER DISSIPATION

Normal Operation Master clock = 256 fS, 48 kHz

Analog Supply DVDD internal 46.2 mW

DVDD external 31 mW

Digital Supply DVDD external 8.1 mW

Digital I/O Supply IOVDD = 3.3 V 1.49 mW

Power-Down, All Supplies

960

µW

DIGITAL FILTER SPECIFICATIONS

Table 4.

Parameter Mode Factor Min Typ Max Unit

ADC DECIMATION FILTER All modes, typical at fS = 48 kHz

Pass Band 0.4375 × fS 21 kHz

Pass-Band Ripple ±0.015 dB

Transition Band 0.5 × fS 24 kHz

Stop Band 0.5625 × fS 27 kHz

Stop-Band Attenuation 79 dB

Group Delay fS = 8 kHz to 96 kHz 22.9844/fS 479 µs

fS = 192 kHz 35 µs

HIGH-PASS FILTER

All modes, typical at 48 kHz

Cutoff Frequency At −3 dB point 0.9375 Hz

Phase Deviation At 20 Hz 10 Degrees

Settling Time 1 sec

ADC DIGITAL GAIN All modes 0 60 dB

Gain Step Size 0.375 dB

Data Sheet ADAU1978

Rev. A | Page 5 of 44

TIMING SPECIFICATIONS

Table 5.

Limit at

Parameter Min Max Unit Description

INPUT MASTER CLOCK (MCLK)

Duty Cycle 40 60 % MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS

fMCLKIN See Table 9 MHz MCLKIN frequency, PLL in MCLK mode

RESET

Reset Pulse 15 ns RST low

PLL

Lock Time 10 ms

I2C PORT See Figure 4

fSCL 400 kHz SCL frequency

tSCLH 0.6 µs SCL high

tSCLL 1.3 µs SCL low

tSCS 0.6 µs Setup time; relevant for repeated start condition

tSCH 0.6 µs Hold time; after this period of time, the first clock pulse is generated

tDS 100 ns Data setup time

tDH 0 Data hold time

tSCR 300 ns SCL rise time

tSCF 300 ns SCL fall time

SDR

300

SDA rise time

tSDF 300 ns SDA fall time

tBFT 1.3 µs Bus-free time; time between stop and start

tSUSTO 0.6 µs Setup time for stop condition

SPI PORT See Figure 3

fCCLK 10 MHz CCLK frequency

tCCPH 35 ns CCLK high

tCCPL 35 ns CCLK low

tCDS 10 ns CIN setup to CCLK rising

tCDH 10 ns CIN hold from CCLK rising

tCLS 10 ns CLATCH setup to CCLK rising

tCLH 40 ns CLATCH hold from CCLK rising

tCLPH 10 ns CLATCH high

tCOE 30 ns COUT enable from CLATCH falling

COD

COUT delay from CCLK falling

tCOTS 30 ns COUT tristate from CLATCH rising

ADC SERIAL PORT See Figure 2

ABH

BCLK high, slave mode

tABL 10 ns BCLK low, slave mode

tALS 10 ns LRCLK setup to BCLK rising, slave mode

tALH 5 ns LRCLK hold from BCLK rising, slave mode

tABDD 18 ns SDATAOUTx delay from BCLK falling

ADAU1978 Data Sheet

Rev. A | Page 6 of 44

Timing Diagrams

Figure 2. Serial Output Port Timing

Figure 3. SPI Port Timing

Figure 4. I2C Port Timing

BCLK

LRCLK

SDATAOUTx

LEFT JUSTIFIED

MODE

SDATAOUTx

RIGHT JUSTIFIED

MODE

LSB

SDATAOUTx

I2S MODE

MSB MSB – 1

MSB

8-BI T CLOCKS

(24-BIT DATA)

12-BI T CLOCKS

(20-BIT DATA)

14-BI T CLOCKS

(18-BIT DATA)

16-BI T CLOCKS

(16-BIT DATA)

tABL

tALS

tABDD

tABH

tABDD

tALH

11292-002

CLATCH

CCLK

CIN

COUT

CLS

CDS

CDH

COD

CCPH

CCPL

CLH

CLPH

COE

COTS

11292-003

tSCH

tSCLH

tSCR

tSCLL tSCF

SDA

SCL

tSCH

tSCS

tDH

tSDF

tSDR tDS

STOP START

tSUSTO

tBFT

11292-004

Data Sheet ADAU1978

Rev. A | Page 7 of 44

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog (AVDDx) Supply −0.3 V to +3.6 V

Digital Supply

DVDD −0.3 V to +1.98 V

IOVDD −0.3 V to +3.63 V

Input Current (Except Supply Pins) ±20 mA

Analog Input Voltage (Signal Pins) –0.3 V to +3.6 V

Digital Input Voltage (Signal Pins) −0.3 V to +3.6 V

Operating Temperature Range (Ambient)

−40°C to +105°C

Junction Temperature Range −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA represents junction-to-ambient thermal resistance, and

θJC represents the junction-to-case thermal resistance. All

characteristics are for a standard JEDEC board per JESD51.

Table 7. Thermal Resistance

Package Type θJA θJC Unit

40-Lead LFCSP 32.8 1.93 °C/W

ESD CAUTION

ADAU1978 Data Sheet

Rev. A | Page 8 of 44

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 5. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type1 Description

1 AGND1 P Analog Ground.

2 VREF O

Voltage Reference. Decouple VREF to AGND with a 10 μF capacitor in parallel with a 100 nF

capacitor.

3 PLL_FILT O PLL Loop Filter. Return PLL_FILT to AVDD using recommended loop filter components.

4 AVDD2 P Analog Power Supply. Connect AVDD2 to an analog 3.3 V supply.

5 AGND2 P Analog Ground.

6 PD/RST I Power-Down/Reset (Active Low).

7 MCLKIN I Master Clock Input.

8, 23 to 27, 30 NC No Connect. Do not connect to these pins. Leave the NC pins open.

9 SA_MODE I

Standalone Mode. Connect SA_MODE to IOVDD using 10 kΩ pull-up resistor for standalone

mode.

10 DVDD O 1.8 V Digital Power Supply Output. Decouple to DGND with 100 nF and 10 μF capacitors.

11 DGND P Digital Ground.

12 IOVDD P Digital I/O Power Supply. Connect IOVDD to a supply from 1.8 V to 3.3 V.

13 SDATAOUT1 O ADC Serial Data Output Pair 1 (ADC L1 and ADC R1).

14 SDATAOUT2 O ADC Serial Data Output Pair 2 (ADC L2 and ADC R2).

15 LRCLK I/O Frame Clock for ADC Serial Port.

16 BCLK I/O Bit Clock for ADC Serial Port.

17 SDA/COUT I/O Serial Data Out (I2C)/Control Data Output (SPI).

18 SCL/CCLK I Serial Clock Input (I2C)/Control Clock Input (SPI).

19 ADDR0/

CLATCH

I Chip Address Bit 0 Setting (I2C)/Chip Select Input for Control Data (SPI).

20 ADDR1/CIN I Chip Address Bit 1 Setting (I2C)/Control Data Input (SPI).

21 AGND3 P Analog Ground.

22 AGND4 P Analog Ground.

28 AGND5 P Analog Ground.

29 AGND6 P Analog Ground.

31 AVDD3 P Analog Power Supply. Connect AVDD3 to an analog 3.3 V supply.

11292-005

1AGND1 2

VREF 3

PLL_FILT 4

AVDD2 5

AGND2

MCLKIN 8

NC 9

SA_MODE 10DVDD

23 NC

24 NC

25 NC

26 NC

27 NC

28 AGND5

29 AGND6

30 NC

22 AGND4

21 AGND3

DGND 12

IOVDD 13

SDATAOUT1

LRCLK

SDA/COUT 16

BCLK

SCL/CCLK

ADDR1/CIN

SDATAOUT2

33 AIN1P

34 AIN2N

35 AIN2P

36AIN3N

37 AIN3P

38 AIN4N

39 AIN4P

40 AVDD1

32 AIN1N

31 AVDD3

TOP VIE W

(Not to Scale)

ADAU1978

PD/RST

ADDR0/CLATCH

NOTES

1. NC = NO CONNECT . DO NOT CONNECT TO THI S PIN.

2. THE EXPOSED PAD MUST BE CONNECTED TO THE

GROUND PLANE O N THE P RINT E D CI RCU I T BOA RD (PCB).

Data Sheet ADAU1978

Rev. A | Page 9 of 44

Pin No. Mnemonic Type1 Description

32 AIN1N I Analog Input Channel 1 Inverting Input.

33 AIN1P I Analog Input Channel 1 Noninverting Input.

34 AIN2N I Analog Input Channel 2 Inverting Input.

35 AIN2P I Analog Input Channel 2 Noninverting Input.

36 AIN3N I Analog Input Channel 3 Inverting Input.

37 AIN3P I Analog Input Channel 3 Noninverting Input.

38 AIN4N I Analog Input Channel 4 Inverting Input.

39 AIN4P I Analog Input Channel 4 Noninverting Input.

40 AVDD1 P Analog Power Supply. Connect AVDD1 to an analog 3.3 V supply.

Exposed Pad. The exposed pad must be connected to the ground plane on the printed circuit

board (PCB).

1 P = power, O = output, I = input, I/O = input/output.

ADAU1978 Data Sheet

Rev. A | Page 10 of 44

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 6. Fast Fourier Transform, 2 mV Differential Input at fS = 48 kHz

Figure 7. Fast Fourier Transform, −1 dBFS Differential Input

Figure 8. THD + N vs. Input Amplitude

Figure 9. CMRR Differential Input, Referenced to 200 mV Differential Input

Figure 10. Fast Fourier Transform, No Input

Figure 11. ADC Pass-Band Ripple at fS = 48 kHz

20 204 6 810 12 14 16 18

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

FRE QUENCY ( kHz )

AMPLITUDE (dBFS)

11292-006

1010.1

FRE QUENCY ( kHz )

AMPLITUDE (dBFS)

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

11292-007

02.01.81.61.41.21.00.80.60.40.2 INPUT AMPLITUDE ( V rms)

THD + N ( dBF S )

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

11292-008

–100

–95

–90

–85

–80

–75

–70

–65

–60

–55

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

100 1k

CMRR (dB)

FRE QUENCY ( Hz ) 10k

11292-009

20k

20 2046810 12 14 16 18

–160

–150

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

FRE QUENCY ( kHz )

AMPLITUDE (dBFS)

11292-010

0.10

0.08

0.06

0.04

0.02

–0.10

–0.08

–0.06

–0.04

–0.02

018000160001400012000100008000600040002000

MAG NITUDE ( dB)

FRE QUENCY ( Hz )

11292-011

Data Sheet ADAU1978

Rev. A | Page 11 of 44

Figure 12. ADC Filter Stop-Band Response at fS = 48 kHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100 0400005000 10000 15000 20000 25000 30000 35000

MAG NITUDE ( dB)

FRE QUENCY ( Hz )

11292-012

ADAU1978 Data Sheet

Rev. A | Page 12 of 44

THEORY OF OPERATION

OVERVIEW

The ADAU1978 incorporates four high performance ADCs and

a phase-locked loop circuit for generating the necessary on-chip

clock signals.

POWER SUPPLY AND VOLTAGE REFERENCE

The ADAU1978 requires a single 3.3 V power supply. Separate

power supply input pins are provided for the analog and boost

converter. Decouple these pins to AGND with 100 nF ceramic

chip capacitors placed as close as possible to the pins to minimize

noise pickup. A bulk aluminum electrolytic capacitor of at least

10 μF must be provided on the same PCB as the ADC. It is

important that the analog supply be as clean as possible for

best performance.

The supply voltage for the digital core (DVDD) is generated

using an internal low dropout regulator. The typical DVDD

output is 1.8 V and must be decoupled using a 100 nF ceramic

capacitor and a 10 µF capacitor. Place the 100 nF ceramic

capacitor as close as possible to the DVDD pin.

The voltage reference for the analog blocks is generated

internally and output at the VREF pin (Pin 2). The typical

voltage at the pin is 1.5 V with an AVDDx of 3.3 V.

All digital inputs are compatible with TTL and CMOS levels.

All outputs are driven from the IOVDD supply. The IOVDD

can be in the 1.8 V to 3.3 V range. The IOVDD pin must be

decoupled with a 100 nF capacitor placed as close to the

IOVDD pin as possible.

The ADC internal voltage reference is output from the VREF pin

and must be decoupled using a 100 nF ceramic capacitor in

parallel with a 10 µF capacitor. The VREF pin has limited current

capability. The voltage reference is used as a reference to the

ADC; therefore, it is recommended not to draw current from

this pin for external circuits. When using this reference, use a

noninverting amplifier buffer to provide a reference to other

circuits in the application.

In reset mode, the VREF pin is disabled to save power and is

enabled only when the RST pin is pulled high.

POWER-ON RESET SEQUENCE

The ADAU1978 requires that a single 3.3 V power supply be

provided externally at the AVDDx pin. The part internally

generates DVDD (1.8 V), which is used for the digital core of

the ADC. The DVDD supply output pin (Pin 10) is provided

to connect the decoupling capacitors to DGND. The typical

recommended values for the decoupling capacitors are 100 nF

in parallel with 10 µF. During a reset, the DVDD regulator is

disabled to reduce power consumption. After the PD/RST pin

(Pin 6) is pulled high, the part enables the DVDD regulator.

However, the internal ADC and digital core reset is controlled by

the internal POR signal (power-on reset) circuit, which monitors

the DVDD level. Therefore, the device does not come out of a

reset until DVDD reaches 1.2 V and the POR signal is released.

The DVDD settling time depends on the charge-up time for the

external capacitors and on the AVDDx ramp-up time.

The internal power-on reset circuit is provided with hysteresis to

ensure that a reset of the part is not initiated by an instantaneous

glitch on DVDD. The typical trip points are 1.2 V with PD/RST

high and 0.6 V (±20%) with PD/RST low. This ensures that

the core is not reset until the DVDD level falls below the 0.6 V

trip point.

As soon as the PD/RST pin is pulled high, the internal regulator

starts charging up CEXT on the DVDD pin. The DVDD charge-up

time is based on the output resistance of the regulator and the

external decoupling capacitor. The time constant can be calcu-

lated as

tC = ROUT × CEXT

where ROUT = 20 Ω typical.

For example, if CEXT is 10 µF, tC is 200 µs and is the time that it

takes to reach the DVDD voltage, within 63.6%.

The power-on reset circuit releases an internal reset of the core

when DVDD reaches 1.2 V (see Figure 13). Therefore, it is

recommended to wait for at least the tC period to elapse before

sending I2C or SPI control signals.

Figure 13. Power-On Reset Timing

When applying a hardware reset to the part by pulling the

PD/RST pin (Pin 6) low and then high, there are certain time

restrictions. During the PD/RST low pulse period, the DVDD

starts discharging. The discharge time constant is decided on by

the internal resistance of the regulator and CEXT. The time

required for DVDD to fall from 1.8 V to 0.48 V (0.6 V − 20%)

can be estimated using the following equation:

tD = 1.32 × RINT × CEXT

where RINT = 64 kΩ typical. (RINT can vary due to process by ±20%.)

For example, if CEXT is 10 µF, tD is 0.845 sec.

Depending on CEXT, tD may vary and, in turn, affect the mini-

mum hold period for the PD/RST pulse. The PD/RST pulse

1.2V 0.48V

POR

DVDD (1.8V)

PD/RST

AVDDx

tRESET

11292-013

Data Sheet ADAU1978

Rev. A | Page 13 of 44

must be held low for the tD time period to initialize the core

properly.

The required PD/RST low pulse period can be reduced by

adding a resistor across CEXT. The new tD value can then be

calculated as

tD = 1.32 × REQ × CEXT

where REQ = 64 kΩ || REXT.

The resistor ensures that DVDD not only discharges quickly during

a reset or an AVDDx power loss but also resets the internal blocks

correctly. Note that some power loss in this resistor is to be

expected because the resistor constantly draws current from

DVDD. The typical value for CEXT is 10 µF and for REXT is 3 kΩ.

This results in a time constant of

tD = 1.32 × REQ × CEXT = 37.8 ms

where REQ = 2.866 kΩ (64 kΩ || 3 kΩ).

Using this equation at a set CEXT value, the REXT can be calculated

for a desired PD/RST pulse period.

There is also a software reset bit (S_RST, Bit 7 of Register 0x00)

available that can be used to reset the part, but note that during an

AVDDx power loss, the software reset may not ensure proper

initialization because DVDD may not be stable.

Figure 14. DVDD Regulator Output Connections

PLL AND CLOCK

The ADAU1978 has a built-in analog PLL to provide a jitter-free

master clock to the internal ADC. The PLL must be programmed

for the appropriate input clock frequency. The PLL_CONTROL

The CLK_S bit (Bit 4) of Register 0x01 is used for setting the

clock source for the PLL. The clock source can be either the

MCLKIN pin or the LRCLK pin (slave mode). In LRCLK mode,

the PLL can support sample rates between 32 kHz and 192 kHz.

In MCLK input mode, the MCS bits (Bits[2:0] of Register 0x01)

must be set to the desired input clock frequency for the MCLKIN

pin. Table 9 shows the input master clock frequency required

for the most common sample rates and the MCS bit settings.

The PLL_LOCK bit (Bit 7) of Register 0x01 indicates the lock

status of the PLL. It is recommended that after initial power-up

the PLL lock status be read to ensure that the PLL outputs the

correct frequency before unmuting the audio outputs.

Table 9. Required Input Master Clock Frequency for

Common Sample Rates

MCS

(Bits[2:0]) fS (kHz)

Frequency

Multiplication Ratio

MCLKIN

Frequency (MHz)

000 32 128 × fS 4.096

001 32 256 × fS 8.192

010 32 384 × fS 12.288

011 32 512 × fS 16.384

100

768 × f

24.576

000 44.1 128 × fS 5.6448

001 44.1 256 × fS 11.2896

010 44.1 384 × fS 16.9344

011 44.1 512 × fS 22.5792

100 44.1 768 × fS 33.8688

000 48 128 × fS 6.144

001 48 256 × fS 12.288

010 48 384 × fS 18.432

011 48 512 × fS 24.576

100 48 768 × fS 36.864

000

64 × f

6.144

001 96 128 × fS 12.288

010 96 192 × fS 18.432

011 96 256 × fS 24.576

100 96 384 × fS 36.864

000 192 32 × fS 6.144

001 192 64 × fS 12.288

010 192 96 × fS 18.432

011 192 128 × fS 24.576

100 192 192 × fS 36.864

The PLL can accept the audio frame clock (sample rate clock)

as the input, but the serial port must be configured as a slave,

and the frame clock must be fed to the part from the master.

It is strongly recommended that the PLL be disabled, repro-

grammed with the new setting, and then reenabled. A lock bit

is provided that can be polled via the I2C to check whether the

PLL has acquired lock.

The PLL requires an external filter, which is connected at the

PLL_FILT pin (Pin 3). The recommended PLL filter circuit for

MCLK or LRCLK mode is shown in Figure 15. Using NPO

capacitors is recommended for temperature stability. Place the

filter components close to the device for best performance.

Figure 15. PLL Filter

3.3V TO 1.8V

REGULATOR

DVDD

ADAU1978

IOVDD

+1.8V OR +3.3V

0.1µF

EXT

10µF

ML CC X 7R

EXT

3kΩ

AVDD1 AVDD3 AVDD2

+3.3V

TO INTERNAL

BLOCKS

11292-114

AVDDx

PLL_FILT

LRCL K M ODE

39nF

4.87kΩ

2.2nF

AVDDx

PLL_FILT

MCLK M ODE

5.6nF

1kΩ

390pF

11292-014

ADAU1978 Data Sheet

Rev. A | Page 14 of 44

ANALOG INPUTS

The ADAU1978 has four differential analog inputs. The ADCs

can accommodate both dc- and ac-coupled input signals.

The block diagram shown in Figure 16 represents the typical

input circuit.

In most audio applications, the dc content of the signal is removed

by using a coupling capacitor. However, the ADAU1978 consists

of a unique input structure that allows ac coupling of the input

signals. The typical input resistance is approximately 14 kΩ

from each input to AGND.

The high-pass filter has a 1.4 Hz, 6 dB per octave cutoff at a

48 kHz sample rate. The cutoff frequency scales directly with

the sample frequency. However, care is required in dc-coupled

applications to ensure that the common-mode dc voltage does

not exceed the specified limit. The input required for the full-

scale ADC output (0 dBFS) is typically 2 V rms differential.

Figure 16. Analog Input Block

VREF

AINxP

AINxN

VID = V INPUT DIFFERENTIAL

VICM+ = VCM AT AINxP

VICM– = VCM AT AINxN

11292-015

Data Sheet ADAU1978

Rev. A | Page 15 of 44

Line Inputs

This section describes some of the possible ways to connect the

line level inputs of the ADAU1978.

Line Input Balanced or Differential Input DC-Coupled Case

For example, for an input signal of 2 V rms differential with

approximately 1.5 V common-mode dc, the signal at each input

pin has a 1 V rms or 2.8 V p-p signal swing. With common-mode

dc of 1.5 V, the signal can swing between (1.5 V + 1.414 V) =

2.914 V to (1.5 V − 1.414 V) = 0.086 V at each input. Therefore,

this is approximately 5.6 V p-p differential across AINxP and

AINxN and measures close to 0 dBFS (ac only with a dc high-

pass filter) at the ADC output (see Figure 17).

Line Input Balanced or Differential Input AC-Coupled Case

For connecting the ADAU1978 to a head unit amplifier output,

ac coupling is recommended. In this case, the AINxP/AINxN

pins are at a common-mode level of 1.5 V. The attenuator can

be used to reduce the input level if it is more than 2 V rms.

The C1 and C2 values can be found for the required low

frequency cutoff using the following equation:

C1 or C2 = 1/(2 × π × fC × Input Resistance)

where the Input Resistance of the ADAU1978 is 14.3 kΩ typical.

Refer to Figure 18 for information about connecting the line

level inputs to the ADAU1978.

Line Input Unbalanced or Single-Ended, Pseudo Differential

AC-Coupled Case

For a single-ended application, reduce the signal swing by half

because only one input is used for the signal with the other con-

nected to 0 V. Doing this reduces the input signal capability to

1 V rms in the single-ended application and measures approxi-

mately −6.16 dBFS (ac only with a dc high-pass filter) at the

ADC output.

See Figure 19 for additional information. The value of the C1/C2 is

similar to the balanced ac-coupled case previously mentioned in

the Line Input Balanced or Differential Input AC-Coupled Case

section.

Figure 17. Connecting the Line Level Inputs—Differential DC-Coupled Case

Figure 18. Connecting the Line Level Inputs—Differential AC-Coupled Case

Figure 19. Connecting the Line Level Inputs—Pseudo Differential AC-Coupled Case

AINxP

AINxN

VDIFF = 2V rms AC

VCM = 1.5V DC

TYPICAL AUDIO POWER

AMPLIFIER OUTPUT

11292-016

OPT ION A: DIFF ERENTIAL DC-COUPL ED

AINxP

C2 AINxN

11292-017

TYPICAL AUDIO POWER

AMPLIFIER OUTPUT

OPT ION B: DIFF ERENTIAL AC-COUPL ED

ATTENUATOR

VDIFF = 2V rms

11292-018

AINxP

C2 AINxN

= 1V rms AC

TYPICAL AUDIO POWER

AMPLIFIER OUTPUT

OP TION C: PSEUDO DIFFE RENTIAL AC-COUPLED

ADAU1978 Data Sheet

Rev. A | Page 16 of 44

ADC

The ADAU1978 contains four sigma-delta (Σ-Δ) ADC channels

configured as two stereo pairs with configurable differential/

single-ended inputs. The ADC can operate at a nominal sample

rate of 32 kHz up to 192 kHz. The ADCs include on-board

digital antialiasing filters with 79 dB stop-band attenuation and

linear phase response. Digital outputs are supplied through two

serial data output pins (one for each stereo pair) and a common

frame clock (LRCLK) and bit clock (BCLK). Alternatively, one

of the TDM modes can be used to support up to 16 channels on

a single TDM data line.

With smaller amplitude input signals, a 10-bit programmable

digital gain compensation for an individual channel is provided

to scale up the output word to full scale. Take care to avoid

overcompensation (large gain compensation), which leads to

clipping and THD degradation in the ADC.

The ADCs also have a dc offset calibration algorithm to null the

systematic dc offset of the ADC. This feature is useful for dc

measurement applications.

ADC SUMMING MODES

The four ADCs can be grouped into either a single stereo ADC

or a single mono ADC to increase the SNR for the application.

Two options are available: one option for summing two channels

of the ADC and another option for summing all four channels

of the ADC. Summing is performed in the digital block.

2-Channel Summing Mode

When the SUM_MODE bits (Bits[7:6] of Register 0x0E) are set

to 01, the Channel 1 and Channel 2 ADC data are combined

and output from the SDATAOUT1 pin. Similarly, the Channel 3

and Channel 4 ADC data are combined and output from the

SDATAOUT2 pin. As a result, the SNR improves by 3 dB. For this

mode, both Channel 1 and Channel 2 must be connected to the

same input signal source. Similarly, Channel 3 and Channel 4

must be connected to the same input signal source.

Figure 20. 2-Channel Summing Mode Connection Diagram

4-Channel Summing Mode

When the SUM_MODE Bits (Bits[7:6] of Register 0x0E) are set

to 10, the Channel 1 through Channel 4 ADC data are combined

and output from the SDATAOUT1 pin. As a result, the SNR

improves by 6 dB. For this mode, all four channels must be

connected to the same input signal source.

Figure 21. 4-Channel Summing Mode Connection Diagram

11292-019

OP TION B: DIFF ERENTIAL AC-COUP LED

DIFF

= 2V rms

AIN1P

AIN1N

AIN2P

AIN2N

TYPICAL STEREO

OUTPUT

AIN3P

AIN3N

AIN4P

AIN4N

11292-020

OP TION B: DIFF ERENTIAL AC-COUP LED

DIFF

= 2V rms

AIN1P

AIN1N

AIN2P

AIN2N

TYPICAL STEREO

OUTPUT

AIN3P

AIN3N

AIN4P

AIN4N

Data Sheet ADAU1978

Rev. A | Page 17 of 44

SERIAL AUDIO DATA OUTPUT PORTS, DATA

FORMAT

The serial audio port comprises four pins: BCLK, LRCLK,

SDATAOUT1, and SDATAOUT2. The ADAU1978 ADC outputs

are available on the SDATAOUT1 and SDATAOUT2 pins in

serial format. The BCLK and LRCLK pins serve as the bit clock

and frame clock, respectively. The port can be operated as master

or slave and can be set either in stereo mode (2-channel mode)

or in TDM multichannel mode. The supported popular audio

formats are I2S, left justified (LJ), and right justified (RJ).

Stereo Mode

In 2-channel or stereo mode, the SDATAOUT1 outputs ADC

data for Channel 1 and Channel 2, and the SDATOUT2 outputs

ADC data for Channel 3 and Channel 4. Figure 22 through

Figure 24 show the supported audio formats.

Figure 22. I2S Audio Format

Figure 23. Left Justified Audio Format

Figure 24. Right Justified Audio Format

BCLK

LRCLK

SDATAOUT1

S MODE)

SDATAOUT2

S MODE)

NOTES

1. SAI = 0.

2. SDATA_FMT = 00 (I

S).

CHANNEL 1 CHANNEL 2

8 TO 3 2 BCLKs 8 TO 3 2 BCL Ks

CHANNEL 3 CHANNEL 4

11292-024

BCLK

LRCLK

SDATAOUT1

(LJ MODE)

SDATAOUT2

(LJ MODE)

CHANNEL 1 CHANNEL 2

CHANNEL 3 CHANNEL 4

11292-025

NOTES

1. SDATA_FMT = 01 (LJ).

BCLK

LRCLK

SDATAOUT1

(RJ MO DE)

SDATAOUT2

(RJ MO DE)

CHANNEL 1 CHANNEL 2

CHANNEL 3 CHANNEL 4

11292-026

NOTES

1. SDATA_FMT = 10 (RJ, 24- BIT) .

ADAU1978 Data Sheet

Rev. A | Page 18 of 44

TDM Mode

for the TDM mode. The TDM slot width, data width, and

channel assignment, as well as the pin used to output the data,

are programmable.

By default, serial data is output on the SDATAOUT1 pin;

however, the SDATA_SEL bit (Bit 7 of Register 0x06) can be

used to change the setting so that serial data is output from the

SDATAOUT2 pin.

The TDM mode supports two, four, eight, or 16 channels. The

ADAU1978 outputs four channels of data in the assigned slots

(Figure 27 shows the TDM mode slot assignments). During the

unused slots, the output pin becomes high-Z so that the same

data line can be shared with other devices on the TDM bus.

The TDM port can be operated as either a master or a slave.

In master mode, the BCLK and LRCLK are output from the

ADAU1978, whereas in slave mode, the BCLK and LRCLK pins

are set to receive the clock from the master in the system.

Both the nonpulse and pulse modes are supported. In nonpulse

mode, the LRCLK signal is typically 50% of the duty cycle, whereas

in pulse mode, the LRCLK signal must be at least one BCLK wide

(see Figure 25 and Figure 26).

Figure 25. TDM Nonpulse Mode Audio Format

Figure 26. TDM Pulse Mode Audio Format

BCLK

LRCLK

SDATA I

SDATA LJ

CHANNEL 1

CHANNEL 2 CHANNEL N

11292-027

32/24/ 16 BCLKs

8 TO 3 2 BCLKs

8 TO 3 2 BCLKs 8 TO 3 2 BCLKs 8 TO 3 2 BCLKs

8 TO 3 2 BCLKs 8 T O 32 BCL Ks

32/24/ 16 BCLKs 32/24/ 16 BCLKs

SDATA I

SCHANNEL 1 CHANNEL 2 CHANNEL N

24 OR 16 BCL Ks 2 4 OR 16 BCLKs 24 O R 16 BCLKs

NOTES

1. SAI = 0 0 1 (2 CHANNEL S), 01 0 (4 CHANNELS ) , 01 1 ( 8 CHANNEL S), 1 00 (16 CHANNELS ) .

2. SDATA_FMT = 00 (I

S), 01 ( LJ) , 10 ( RJ, 24- BIT) , 11 (RJ, 16-BI T) .

3. BCLKE DGE = 0 .

4. LR_MO DE = 0.

5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 ( 16 BCLKs).

BCLK

LRCLK

SDATA I

SDATA LJ

CHANNEL 1

CHANNEL 2 CHANNEL N

11292-028

32/24/ 16 BCLKs

8 TO 3 2 BCLKs

8 TO 3 2 BCLKs 8 TO 3 2 BCLKs 8 TO 3 2 BCLKs

8 TO 3 2 BCLKs 8 T O 32 BCL Ks

32/24/ 16 BCLKs 32/24/ 16 BCLKs

SDATA I

SCHANNEL 1 CHANNEL 2 CHANNEL N

24 OR 16 BCL Ks 2 4 OR 16 BCLKs 24 OR 1 6 BCLKs

NOTES

1. SAI = 0 0 1 (2 CHANNEL S), 01 0 (4 CHANNELS ) , 01 1 ( 8 CHANNEL S), 1 00 (16 CHANNELS )

2. SDATA_FMT = 00 (I

S), 01 ( LJ) , 10 ( RJ, 24- BIT) , 11 (RJ, 16-BI T)

3. BCLKE DGE = 0

4. LR_ MO DE = 1

5. SLOT_WIDTH = 00 (32 BCLKs), 01 (24 BCLKs), 10 ( 16 BCLKs)

Data Sheet ADAU1978

Rev. A | Page 19 of 44

Figure 27. TDM Mode Slot Assignment

Table 10. Bit Clock Frequency TDM Mode

BCLK Frequency

Mode 16-Bit Clocks Per Slot 24-Bit Clocks Per Slot 32-Bit Clocks Per Slot

TDM2 32 × fS 48 × fS 64 × fS

TDM4 64 × fS 96 × fS 128 × fS

TDM8 128 × fS 192 × fS 256 × fS

TDM16 256 × fS 384 × fS 512 × fS

The bit clock frequency depends on the sample rate, the slot

width, and the number of bit clocks per slot. Table 10 can be

used to calculate the BCLK frequency.

The sample rate (fS) can range from 8 kHz up to 192 kHz.

However, in master mode, the maximum bit clock frequency

(BCLK) is 24.576 MHz. For example, for a sample rate of

192 kHz, 128 × fS is the maximum possible BCLK frequency.

Therefore, only 128-bit clock cycles are available per TDM

frame. There are two options in this case: either operate with a

32-bit data width in TDM4 or operate with a 16-bit data width

in TDM8. In slave mode, this limitation does not exist because

the bit clock and frame clock are fed to the ADAU1978. Var ious

combinations of BCLK frequencies and modes are available, but

take care to choose the combination that is most suitable for the

application.

NUMBER OF BCLK CYCLES = (NUMBER O F BCLKs /SLOT) × NUM BER OF SLOT S

SLOT2SLOT1

SLOT1 SLOT2 SLOT3 SLOT4

SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 SLOT8

SLOT1 SLOT2 SLOT3 SLOT4 SLOT5 SLOT6 SLOT7 SLOT8 SLOT9 SLOT10 SLOT11 SLOT12 SLOT13 SLOT14 SLOT15 SLOT16

LRCLK

BCLK

SDATAOUTx—TDM2

SDATAOUTx—TDM4

SDATAOUTx—TDM8

SDATAOUTx—TDM16

DATA WIDTH

16/24 BITS

SLOT WIDTH

16/24/ 32 BITS

HIGH-Z HIGH-Z

11292-029

ADAU1978 Data Sheet

Rev. A | Page 20 of 44

Connection Options

Figure 28 through Figure 32 show the available options for

connecting the serial audio port in I2S or TDM mode. In

TDM mode, it is recommended to include the pull-down

resistor on the data signal to prevent the line from floating

when the SDATAOUTx pin of the ADAU1978 becomes high-Z

during an inactive period. The resistor value should be such

that no more than 2 mA is drawn from the SDATAOUTx pin.

Although the resistor value is typically in the 10 kΩ to 47 kΩ

range, the appropriate resistor value depends on the devices

on the data bus.

Figure 28. Serial Port Connection Option 1—I2S/Left Justified/Right Justified

Modes, ADAU1978 Master

Figure 29. Serial Port Connection Option 2—I2S/Left Justified/Right Justified

Modes, ADAU1978 Slave

Figure 30. Serial Port Connection Option 3—TDM Mode, ADAU1978 Master

Figure 31. Serial Port Connection Option 4—TDM Mode, Second ADC Master

Figure 32. Serial Port Connection Option 5—TDM Mode, DSP Master

DSP

SLAVEMASTER

ADAU1978

BCLK

LRCLK

SDATAOUT1

SDATAOUT2

11292-030

DSP

MASTERSLAVE

ADAU1978

BCLK

LRCLK

SDATAOUT1

SDATAOUT2

11292-033

DSP

SLAVEMASTER

ADAU1978

BCLK

LRCLK

SDATAOUTx

SLAVE

ADAU1978

SI M ILIAR ADC

BCLK

LRCLK

SDATAOUTx

11292-031

DSP

SLAVESLAVE

ADAU1978

BCLK

LRCLK

SDATAOUTx

MASTER

ADAU1978

SI M ILIAR ADC

BCLK

LRCLK

SDATAOUTx

11292-034

DSP

MASTERSLAVE

ADAU1978

BCLK

LRCLK

SDATAOUTx

SLAVE

ADAU1978

SI M ILIAR ADC

BCLK

LRCLK

SDATAOUTx

11292-032

Data Sheet ADAU1978

Rev. A | Page 21 of 44

CONTROL PORTS

The ADAU1978 control port allows two modes of operation,

either 2-wire I2C mode or 4-wire SPI mode, that are used for

setting the internal registers of the part. Both the I2C and SPI

modes allow read and write capability of the registers. All the

registers are eight bits wide. The registers start at Address 0x00

and end at Address 0x1A.

The control port in both I2C and SPI modes is slave only and,

therefore, requires the master in the system to operate. The

registers can be accessed with or without the master clock to

the part. However, to operate the PLL, serial audio ports, and

boost converter, the master clock is necessary.

By default, the ADAU1978 operates in I2C mode, but the part can

be put into SPI mode by pulling the CLATCH pin low three times.

The control port pins are multifunctional, depending on the

mode in which the part is operating. Table 11 describes the

control port pin functions in both modes.

Table 11. Control Port Pin Functions

I2C Mode SPI Mode

Pin No. Mnemonic Pin Function Pin Type Pin Function Pin Type

17 SDA/COUT SDA data I/O COUT output data O

SCL/CCLK

SCL clock

CCLK input clock

19 ADDR0/CLATCH I2C Device Address Bit 0 I CLATCH input I

20 ADDR1/CIN I2C Device Address Bit 1 I CIN input data I

ADAU1978 Data Sheet

Rev. A | Page 22 of 44

I2C MODE

The ADAU1978 supports a 2-wire serial (I2C-compatible) bus

protocol. Two pins, serial data (SDA) and serial clock (SCL), are

used to communicate with the system I2C master controller. In

I2C mode, the ADAU1978 is always a slave on the bus, meaning

that it cannot initiate a data transfer. Each slave device on the

I2C bus is recognized by a unique device address. The device

address and R/W byte for the ADAU1978 are shown in Table 12.

The address resides in the first seven bits of the I2C write. Bit 7

and Bit 6 of the I2C address for the ADAU1978 are set by the

levels on the ADDR1 and ADDR0 pins. The LSB of the first I2C

byte (the R/W bit) from the master identifies whether it is a read

or write operation. Logic Level 1 in the LSB (Bit 0) corresponds

to a read operation, and Logic Level 0 corresponds to a write

operation.

Table 12. I2C First Byte Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ADDR1 ADDR0 1 0 0 0 1 R/W

The first seven bits of the I2C chip address for the ADAU1978

are xx10001. Bit 7 and Bit 6 of the address byte can be set using

the ADDR1 and ADDR0 pins to set the chip address to the

desired value.

The 7-bit I2C device address can be set to one of four of the

following possible options using the ADDR1 and ADDR0 pins:

• I2C Device Address 0010001 (0x11)

• I2C Device Address 0110001 (0x31)

• I2C Device Address 1010001 (0x51)

• I2C Device Address 1110001 (0x71)

In I2C mode, both the SDA and SCL pins require that an

appropriate pull-up resistor be connected to IOVDD. Ensure

that the voltage on these signal lines does not exceed the voltage

on the IOVDD pin. Figure 44 shows a typical connection

diagram for the I2C mode.

The value of the pull-up resistor for the SDA or SCL pin can be

calculated as follows.

Minimum RPULL UP = (IOVDD − VIL)/ISINK

where:

IOVDD is the I/O supply voltage, typically ranging from 1.8 V

up to 3.3 V.

VIL is the maximum voltage at Logic Level 0 (that is, 0.4 V, as

per the I2C specifications).

ISINK is the current sink capability of the I/O pin.

The SDA pin can sink 2 mA of current; therefore, the minimum

value of RPULL UP for an IOVDD of 3.3 V is 1.5 kΩ.

Depending on the capacitance of the board, the speed of the bus

can be restricted to meet the rise time and fall time specifications.

For fast mode with a bit rate time of around 1 Mbps, the rise

time must be less than 550 ns. Use the following equation to

determine whether the rise time specification can be met:

t = 0.8473 × RPULL UP × CBOARD

where CBOARD must be less than 236 pF to meet the 300 ns rise

time requirement.

For the SCL pin, the calculations depend on the current sink

capability of the I2C master used in the system.

Addressing

Initially, each device on the I2C bus is in an idle state and monitors

the SDA and SCL lines for a start condition and the proper address.

The I2C master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while

SCL remains high. This indicates that an address/data stream

follows. All devices on the bus respond to the start condition

and acquire the next eight bits from the master (the 7-bit address

plus the R/W bit) MSB first. The master sends the 7-bit device

address with the R/W bit to all the slaves on the bus. The device

with the matching address responds by pulling the data line

(SDA) low during the ninth clock pulse. This ninth bit is known

as an acknowledge bit. All other devices withdraw from the bus

at this point and return to the idle condition.

The R/W bit determines the direction of the data. A Logic 0 on the

LSB of the first byte means that the master is to write information

to the slave, whereas a Logic 1 means that the master is to read

information from the slave after writing the address and repeating

the start address. A data transfer takes place until a master initiates

a stop condition. A stop condition occurs when SDA transitions

from low to high while SCL is held high.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence

during normal read and write operations, the ADAU1978

immediately jumps to the idle condition.

Figure 33 and Figure 34 use the following abbreviations:

ACK = acknowledge

No ACK = no acknowledge

Data Sheet ADAU1978

Rev. A | Page 23 of 44

Figure 33. I2C Write to ADAU1978, Single Byte

Figure 34. I2C Read from ADAU1978, Single Byte

012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

ADDR1 ADDR0 1 0 0 0 1

START STOP

SCL

SDA

FIRST BYTE (DEVI CE ADDRESS) SECO ND BYTE ( RE GI ST ER ADDRESS) THI RD BYTE ( DAT A)

R/W

11292-035

ACK

ADAU1978 ACK

ADAU1978

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

ADDR1 ADDR0 1 0 0 0 1

SCL

SDA

THI RD BYTE ( DE VICE ADDRESS) DATA BYTE FROM ADAU1 9 78

R/W

11292-036

01234567 8 910 11 12 13 14 15 16 17 18

ADDR1 ADDR0 1000 1

START

SCL

SDA

FIRST BYTE (DEVI CE ADDRESS) SECOND BY TE (REGI STE R ADDRESS)

R/W

NO ACK STOP

ACK

ADAU1978

ACK

ADAU1978 ACK

ADAU1978

REPEAT START

ADAU1978 Data Sheet

Rev. A | Page 24 of 44

I2C Read and Write Operations

Figure 35 shows the format of a single-word I2C write

operation. Every ninth clock pulse, the ADAU1978 issues an

acknowledge by pulling SDA low.

Figure 36 shows the format of a burst mode write sequence. This

figure shows an example of a write to sequential single-byte

registers. The ADAU1978 increments its address register after

every byte because the requested address corresponds to a

Figure 37 shows the format of a single-word I2C read operation.

Note that the first R/W bit is 0, indicating a write operation.

This is because the address still needs to be written to set up the

internal address. After the ADAU1978 acknowledges the receipt

of the address, the master must issue a repeated start command

followed by the chip address byte with the R/W bit set to 1

(read). This causes the ADAU1978 SDA to reverse and begin

driving data back to the master. The master then responds every

ninth pulse with an acknowledge pulse to the ADAU1978.

Figure 38 shows the format of a burst mode read sequence. This

figure shows an example of a read from sequential single-byte

registers. The ADAU1978 increments its address registers after

every byte because the ADAU1978 uses an 8-bit register address.

Figure 35 to Figure 38 use the following abbreviations:

S = start bit

P = stop bit

AM = acknowledge by master

AS = acknowledge by slave

Figure 35. Single-Word I2C Write Format

Figure 36. Burst Mode I2C Write Format

Figure 37. Single-Word I2C Read Format

Figure 38. Burst Mode I2C Read Format

SCHIPADDRESS,

R/W = 0 AS DATA BYT EAS PREGISTER ADDRESS

8 BITS

11292-037

SCHIP

ADDRESS,

R/W = 0

AS AS ASREGISTER

ADDRESS

8 BIT S

DATA

BYTE 1 DATA

BYTE 2 DATA

BYTE 3 DATA

BYTE 4

AS AS AS P...

CHIP

ADDRESS,

R/W = 0

11292-038

DATA

BYTE 1

SCHIP

ADDRESS,

R/W = 0

AS AS PREGISTER

ADDRESS

8 BITS

CHIP

ADDRESS,

R/W = 1

AS S

11292-039

DATA

BYTE 1

SCHIP

ADDRESS,

R/W = 0

AMREGISTER

ADDRESS

8 BIT S

SAS AS AS DATA

BYTE 2 AM ... P

CHIP

ADDRESS,

R/W = 1

11292-040

Data Sheet ADAU1978

Rev. A | Page 25 of 44

SPI MODE

By default, the ADAU1978 is in I2C mode. To invoke SPI control

mode, pull CLATCH low three times. This can be done by perform-

ing three dummy writes to the SPI port (the ADAU1978 does not

acknowledge these three writes, see Figure 39). Beginning with the

fourth SPI write, data can be written to or read from the device.

The ADAU1978 can be taken out of SPI mode only by a full

reset initiated by power cycling the device.

The SPI port uses a 4-wire interface, consisting of the CLATCH,

CCLK, CIN, and COUT signals, and it is always a slave port.

The CLATCH signal goes low at the beginning of a transaction

and high at the end of a transaction. The CCLK signal latches

COUT on a low-to-high transition. COUT data is shifted out of

the ADAU1978 on the falling edge of CCLK and is clocked into

a receiving device, such as a microcontroller, on the CCLK

rising edge. The CIN signal carries the serial input data, and the

COUT signal carries the serial output data. The COUT signal

remains tristated until a read operation is requested. This allows

direct connection to other SPI-compatible peripheral COUT ports

for sharing the same system controller port. All SPI transactions

have the same basic generic control word format, as shown in

Table 15. A timing diagram is shown in Figure 3. Write all data

MSB first.

Chip Address R/W

The LSB of the first byte of an SPI transaction is a R/W bit. This bit

determines whether the communication is a read (Logic Level 1)

or a write (Logic Level 0). This format is shown in Table 13.

Table 13. SPI Address and R/W Byte Format

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0 0 0 0 0 0 0 R/W

The 8-bit address word is decoded to a location in one of the

registers. This address is the location of the appropriate register.

Data Bytes

The number of data bytes varies according to the register being

accessed. During a burst mode write, an initial register address is

written followed by a continuous sequence of data for consecutive

A sample timing diagram for a single-word SPI write operation

to a register is shown in Figure 40. A sample timing diagram of

a single-word SPI read operation is shown in Figure 41. The

COUT pin goes from being high-Z to being driven at the

beginning of Byte 3. In this example, Byte 0 to Byte 1 contain

the device address, the R/W bit, and the register address to be

read. Subsequent bytes carry the data from the device.

Standalone Mode

The ADAU1978 can also operate in standalone mode. However,

in standalone mode, the boost converter, microphone bias, and

diagnostics blocks are powered down. To set the part in standalone

mode, pull the SA_MODE pin to IOVDD. In this mode, some

pins change functionality to provide more flexibility (see Table 14

for more information).

Table 14. Pin Functionality in Standalone Mode

Pin Function1 Setting Description

ADDR0

S SAI format

1 TDM modes, determined by the

SDATAOUT2 pin

ADDR1

Master mode SAI

1 Slave mode SAI

SDA 0 MCLK = 256 × fS, PLL on

1 MCLK = 384 × fS, PLL on

SCL 0 48 kHz sample rate

96 kHz sample rate

SDATAOUT2 0 TDM4—LRCLK pulse

1 TDM8—LRCLK pulse

1 Pin functionality, not full pin names, is listed. See Table 11 for additional

information.

Table 15. Generic Control Word Format

Byte 0 Byte 1 Byte 2 Byte 31

Device Address[6:0], R/W Register Address[7:0] Data[7:0] Data[7:0]

1 Continues to end of data.

ADAU1978 Data Sheet

Rev. A | Page 26 of 44

Figure 39. SPI Mode Initial Sequence

Figure 40. SPI Write to ADAU1978 Clocking (Single-Word Write Mode)

Figure 41. SPI Read from ADAU1978 Clocking (Single-Word Read Mode)

Figure 42. SPI Write to ADAU1978 (Multiple Bytes)

Figure 43. SPI Read from ADAU1978 (Multiple Bytes)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

CLATCH

CCLK

CIN

11292-041

0 1 2 3 45 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

CLATCH

CCLK

CIN

11292-042

DEVI CE ADDRE S S ( 7 BIT S ) R/W DAT A BY TE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

CLATCH

CCLK

CIN

COUT

11292-043

REG IST E R ADDRE S S BY TE

DEVICE ADDRES S ( 7 BITS )

R/W DATA BYT E

DATA BY TE F ROM ADAU1978

ADDRESS

BYTE

DATA BY TE1 DATA BYTE2DEVICE

ADDRESS

BYTE

DATA BY TE n – 1 DATA BY TE n

CLATCH

CCLK

CIN

11292-044

DEVICE

ADDRESS

BYTE

ADDRESS

BYTE

DATA BY TE2 DATA BYTE 3

DATA BY TE1 DATA BY TE n – 1 DATA BYTE n

CLATCH

CCLK

CIN

COUT

11292-045

Data Sheet ADAU1978

Rev. A | Page 27 of 44

Table 16. REGMAP_ADAU1978 Register Summary

Reg

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x00

M_POWER

[7:0]

S_RST

RESERVED

PWUP

0x00

0x01

PLL_CONTROL

[7:0]

PLL_LOCK

PLL_MUTE

RESERVED

CLK_S

RESERVED

MCS

0x41

0x02

RESERVED

[7:0]

RESERVED

Reserved

0x03

RESERVED

[7:0]

RESERVED

Reserved

0x04

BLOCK_POWER_SAI

[7:0]

LR_POL

BCLKEDGE

LDO_EN

VREF_EN

ADC_EN4

ADC_EN3

ADC_EN2

ADC_EN1

0x3F

0x05

SAI_CTRL0

[7:0]

SDATA_FMT

SAI

0x02

0x06

SAI_CTRL1

[7:0]

SDATA_SEL

SLOT_WIDTH

DATA_WIDTH

LR_MODE

SAI_MSB

BCLKRATE

SAI_MS

0x00

0x07

SAI_CMAP12

[7:0]

CMAP_C2

CMAP_C1

0x10

0x08

SAI_CMAP34

[7:0]

CMAP_C4

CMAP_C3

0x32

0x09

SAI_OVERTEMP

[7:0]

SAI_DRV_C4

SAI_DRV_C3

SAI_DRV_C2

SAI_DRV_C1

DRV_HIZ

RESERVED

0xF0

0x0A

POSTADC_GAIN1

[7:0]

PADC_GAIN1

0xA0

0x0B

POSTADC_GAIN2

[7:0]

PADC_GAIN2

0xA0

0x0C

POSTADC_GAIN3

[7:0]

PADC_GAIN3

0xA0

0x0D

POSTADC_GAIN4

[7:0]

PADC_GAIN4

0xA0

0x0E

MISC_CONTROL

[7:0]

SUM_MODE

RESERVED

MMUTE

RESERVED

DC_CAL

0x02

0x0F

RESERVED

[7:0]

RESERVED

0xFF

0x10

RESERVED

[7:0]

RESERVED

0x0F

0x11

RESERVED

[7:0]

RESERVED

0x00

0x12

RESERVED

[7:0]

RESERVED

0x00

0x13

RESERVED

[7:0]

RESERVED

0x00

0x14

RESERVED

[7:0]

RESERVED

0x00

0x15

RESERVED

[7:0]

RESERVED

0x20

0x16

RESERVED

[7:0]

RESERVED

0x00

0x17

RESERVED

[7:0]

RESERVED

Reserved

0x18

RESERVED

[7:0]

RESERVED

Reserved

0x19

ASDC_CLIP

[7:0]

RESERVED

ADC_CLIP4

ADC_CLIP3

ADC_CLIP2

ADC_CLIP1

0x00

0x1A

DC_HPF_CAL

[7:0]

DC_SUB_C4

DC_SUB_C3

DC_SUB_C2

DC_SUB_C1

DC_HPF_C4

DC_HPF_C3

DC_HPF_C2

DC_HPF_C1

0x00

ADAU1978 Data Sheet

Rev. A | Page 28 of 44

MASTER POWER AND SOFT RESET REGISTER

Address: 0x00, Reset: 0x00, Name: M_POWER

The power management control register is used for enabling the boost regulator, microphone bias, PLL, band gap reference, ADC, and

LDO regulator.

Table 17. Bit Descriptions for M_POWER

Bits Bit Name Settings Description Reset Access

7 S_RST Software Reset. The software reset resets all internal circuitry and all control registers to

their respective default states. It is not necessary to reset the ADAU1978 during a power-

up or power-down cycle.

0x0 RW

0 Normal Operation.

1 Software Reset.

[6:1]

RESERVED

Reserved.

0x00

0 PWUP Master Power-Up Control. The master power-up control fully powers up or powers down

the ADAU1978. This must be set to 1 to power up the ADAU1978. Individual blocks can

be powered down via their respective power control registers.

0x0 RW

0 Full Power-Down.

1 Master Power-Up.

Data Sheet ADAU1978

Rev. A | Page 29 of 44

PLL CONTROL REGISTER

Address: 0x01, Reset: 0x41, Name: PLL_CONTROL

Table 18. Bit Descriptions for PLL_CONTROL

Bits Bit Name Settings Description Reset Access

7 PLL_LOCK PLL Lock Status. PLL lock status bit. When set to 1, the PLL is locked. 0x0 R

0 PLL Not Locked.

1 PLL Locked.

6 PLL_MUTE PLL Unlock Automute. When set to 1, it mutes the ADC output if PLL becomes unlocked. 0x1 RW

0 No Automatic Mute on PLL Unlock.

1 Automatic Mute with PLL Unlock.

5 RESERVED Reserved. 0x0 RW

4 CLK_S PLL Clock Source Select. Selecting input clock source for PLL. 0x0 RW

MCLK Used for PLL Input.

1 LRCLK Used for PLL Input; Only Supported for Sample Rates in the range of 32 kHz to 192 kHz.

3 RESERVED Reserved. 0x0 RW

[2:0] MCS Master Clock Select. MCS bits determine the frequency multiplication ratio of the PLL. It

must be set based on the input MCLK frequency and sample rate.

0x1 RW

001 256 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).

010 384 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).

011 512 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).

100 768 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).

000 128 × fS MCLK for 32 kHz up to 48 kHz (see the PLL and Clock section for other sample rates).

101 Reserved.

110

Reserved.

111 Reserved.

ADAU1978 Data Sheet

Rev. A | Page 30 of 44

BLOCK POWER CONTROL AND SERIAL PORT CONTROL REGISTER

Address: 0x04, Reset: 0x3F, Name: BLOCK_POWER_SAI

Table 19. Bit Descriptions for BLOCK_POWER_SAI

Bits Bit Name Settings Description Reset Access

7 LR_POL Sets LRCLK Polarity 0x0 RW

0 LRCLK Low then High

1 LRCLK High then Low

6 BCLKEDGE Sets the Bit Clock Edge on Which Data Changes 0x0 RW

0 Data Changes on Falling Edge

1 Data Changes on Rising Edge

5 LDO_EN LDO Regulator Enable 0x1 RW

0 LDO Powered Down

1 LDO Enabled

4 VREF_EN Voltage Reference Enable 0x1 RW

0 Voltage Reference Powered Down

1 Voltage Reference Enabled

3 ADC_EN4 ADC Channel 4 Enable 0x1 RW

0 ADC Channel Powered Down

1 ADC Channel Enabled

2 ADC_EN3 ADC Channel 3 Enable 0x1 RW

0 ADC Channel Powered Down

1 ADC Channel Enabled

1 ADC_EN2 ADC Channel 2 Enable 0x1 RW

0 ADC Channel Powered Down

1 ADC Channel Enabled

0 ADC_EN1 ADC Channel 1 Enable 0x1 RW

0 ADC Channel Powered Down

1 ADC Channel Enabled

Data Sheet ADAU1978

Rev. A | Page 31 of 44

SERIAL PORT CONTROL REGISTER 1

Address: 0x05, Reset: 0x02, Name: SAI_CTRL0

Table 20. Bit Descriptions for SAI_CTRL0

Bits Bit Name Settings Description Reset Access

[7:6] SDATA_FMT Serial Data Format 0x0 RW

00 I2S Data Delayed from Edge of LRCLK by 1 BCLK

01 Left Justified

10 Right Justified, 24-Bit Data

11 Right Justified, 16-Bit Data

[5:3] SAI Serial Port Mode 0x0 RW

000 Stereo (I2S, LJ, RJ)

001 TDM2

010

TDM4

011 TDM8

100 TDM16

[2:0] FS Sampling Rate 0x2 RW

000 8 kHz to 12 kHz

001 16 kHz to 24 kHz

010 32 kHz to 48 kHz

011 64 kHz to 96 kHz

100

128 kHz to 192 kHz

ADAU1978 Data Sheet

Rev. A | Page 32 of 44

SERIAL PORT CONTROL REGISTER 2

Address: 0x06, Reset: 0x00, Name: SAI_CTRL1

Table 21. Bit Descriptions for SAI_CTRL1

Bits Bit Name Settings Description Reset Access

7 SDATA_SEL SDATAOUTx Pin Selection in TDM4 or Greater Modes 0x0 RW

0 SDATAOUT1 used for output

1 SDATAOUT2 used for output

[6:5] SLOT_WIDTH Number of BCLKs per Slot in TDM Mode 0x0 RW

00 32 BCLKs per TDM slot

01 24 BCLKs per TDM slot

10 16 BCLKs per TDM slot

11 Reserved

DATA_WIDTH

Output Data Bit Width

0x0

0 24-bit data

1 16-bit data

LR_MODE

Sets LRCLK Mode

0x0

0 50% duty cycle clock

1 Pulse—LRCLK is a single BCLK cycle wide pulse

2 SAI_MSB Sets Data to be Input/Output Either MSB or LSB First 0x0 RW

0 MSB first data

1 LSB first data

1 BCLKRATE Sets the Number of Bit Clock Cycles per Data Channel Generated When in

Master Mode

0x0 RW

0 32 BCLKs/channel

1 16 BCLKs/channel

0 SAI_MS Sets the Serial Port into Master or Slave Mode 0x0 RW

0 LRCLK/BCLK slave

1 LRCLK/BCLK master

Data Sheet ADAU1978

Rev. A | Page 33 of 44

CHANNEL 1 AND CHANNEL 2 MAPPING FOR OUTPUT SERIAL PORTS REGISTER

Address: 0x07, Reset: 0x10, Name: SAI_CMAP12

Table 22. Bit Descriptions for SAI_CMAP12

Bits Bit Name Settings Description Reset Access

[7:4] CMAP_C2 ADC Channel 2 Output Mapping 0x1 RW

0000 Slot 1 for Channel

0001 Slot 2 for Channel

0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)

0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)

0100

Slot 5 for Channel (TDM8+ only)

0101 Slot 6 for Channel (TDM8+ only)

0110 Slot 7 for Channel (TDM8+ only)

0111 Slot 8 for Channel (TDM8+ only)

1000 Slot 9 for Channel (TDM16 only)

1001 Slot 10 for Channel (TDM16 only)

1010 Slot 11 for Channel (TDM16 only)

1011 Slot 12 for Channel (TDM16 only)

1100 Slot 13 for Channel (TDM16 only)

1101 Slot 14 for Channel (TDM16 only)

1110 Slot 15 for Channel (TDM16 only)

1111

Slot 16 for Channel (TDM16 only)

ADAU1978 Data Sheet

Rev. A | Page 34 of 44

Bits Bit Name Settings Description Reset Access

[3:0] CMAP_C1 ADC Channel 1 Output Mapping. If CMAP is set to a slot that does not

exist for a given serial mode, that channel is not driven. For example, if

CMAP is set to Slot 9 and the serial format is I2S, that channel is not driven.

If more than one channel is set to the same slot, only the lowest channel

number is driven; other channels are not driven.

0x0 RW

0000 Slot 1 for Channel

0001 Slot 2 for Channel

0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)

0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)

0100 Slot 5 for Channel (TDM8+ only)

0101

Slot 6 for Channel (TDM8+ only)

0110 Slot 7 for Channel (TDM8+ only)

0111 Slot 8 for Channel (TDM8+ only)

1000 Slot 9 for Channel (TDM16 only)

1001 Slot 10 for Channel (TDM16 only)

1010 Slot 11 for Channel (TDM16 only)

1011 Slot 12 for Channel (TDM16 only)

1100 Slot 13 for Channel (TDM16 only)

1101 Slot 14 for Channel (TDM16 only)

1110 Slot 15 for Channel (TDM16 only)

1111 Slot 16 for Channel (TDM16 only)

Data Sheet ADAU1978

Rev. A | Page 35 of 44

CHANNEL 3 AND CHANNEL 4 MAPPING FOR OUTPUT SERIAL PORTS REGISTER

Address: 0x08, Reset: 0x32, Name: SAI_CMAP34

Table 23. Bit Descriptions for SAI_CMAP34

Bits Bit Name Settings Description Reset Access

[7:4] CMAP_C4 ADC Channel 4 Output Mapping 0x3 RW

0000 Slot 1 for Channel

0001 Slot 2 for Channel

0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)

0011 Slot 4 for Channel (on SDATAOUT2 in stereo modes)

0100

Slot 5 for Channel (TDM8+ only)

0101 Slot 6 for Channel (TDM8+ only)

0110 Slot 7 for Channel (TDM8+ only)

0111 Slot 8 for Channel (TDM8+ only)

1000 Slot 9 for Channel (TDM16 only)

1001 Slot 10 for Channel (TDM16 only)

1010 Slot 11 for Channel (TDM16 only)

1011 Slot 12 for Channel (TDM16 only)

1100 Slot 13 for Channel (TDM16 only)

1101 Slot 14 for Channel (TDM16 only)

1110 Slot 15 for Channel (TDM16 only)

1111

Slot 16 for Channel (TDM16 only)

ADAU1978 Data Sheet

Rev. A | Page 36 of 44

Bits Bit Name Settings Description Reset Access

[3:0] CMAP_C3 ADC Channel 3 Output Mapping 0x2 RW

0000 Slot 1 for Channel

0001 Slot 2 for Channel

0010 Slot 3 for Channel (on SDATAOUT2 in stereo modes)

0011

Slot 4 for Channel (on SDATAOUT2 in stereo modes)

0100 Slot 5 for Channel (TDM8+ only)

0101 Slot 6 for Channel (TDM8+ only)

0110 Slot 7 for Channel (TDM8+ only)

0111 Slot 8 for Channel (TDM8+ only)

1000 Slot 9 for Channel (TDM16 only)

1001

Slot 10 for Channel (TDM16 only)

1010 Slot 11 for Channel (TDM16 only)

1011 Slot 12 for Channel (TDM16 only)

1100 Slot 13 for Channel (TDM16 only)

1101 Slot 14 for Channel (TDM16 only)

1110 Slot 15 for Channel (TDM16 only)

1111 Slot 16 for Channel (TDM16 only)

SERIAL OUTPUT DRIVE CONTROL AND OVERTEMPERATURE PROTECTION STATUS REGISTER

Address: 0x09, Reset: 0xF0, Name: SAI_OVERTEMP

Table 24. Bit Descriptions for SAI_OVERTEMP

Bits Bit Name Settings Description Reset Access

7 SAI_DRV_C4 Channel 4 Serial Output Drive Enable. 0x1 RW

0 Channel Not Driven on Serial Output Port.

1 Channel Driven on Serial Output Port. Slot determined by CMAP_4.

Data Sheet ADAU1978

Rev. A | Page 37 of 44

Bits Bit Name Settings Description Reset Access

6 SAI_DRV_C3 Channel 3 Serial Output Drive Enable. 0x1 RW

0 Channel Not Driven on Serial Output Port.

1 Channel Driven on Serial Output Port. Slot determined by CMAP_3.

5 SAI_DRV_C2 Channel 2 Serial Output Drive Enable. 0x1 RW

0 Channel Not Driven on Serial Output Port.

1 Channel Driven on Serial Output Port. Slot determined by CMAP_2.

4 SAI_DRV_C1 Channel 1 Serial Output Drive Enable. 0x1 RW

0 Channel Not Driven on Serial Output Port.

1 Channel Driven on Serial Output Port. Slot determined by CMAP_1.

3 DRV_HIZ Select whether to tristate unused SAI channels or actively drive these data slots. 0x0 RW

0 Unused outputs driven low.

1 Unused outputs High-Z.

[2:1] RESERVED Reserved 0x0 R

Overtemperature Status.

0x0

0 Normal Operation.

1 Overtemperature Fault.

POST ADC GAIN CHANNEL 1 CONTROL REGISTER

Address: 0x0A, Reset: 0xA0, Name: POSTADC_GAIN1

Table 25. Bit Descriptions for POSTADC_GAIN1

Bits Bit Name Settings Description Reset Access

[7:0] PADC_GAIN1 Channel 1 Post ADC Gain 0xA0 RW

00000000 +60 dB Gain

00000001 +59.625 dB Gain

00000010

+59.25 dB Gain

... ...

10011111 +0.375 dB Gain

10100000 0 dB Gain

10100001 −0.375 dB Gain

... ...

11111110 −35.625 dB Gain

11111111 Mute

ADAU1978 Data Sheet

Rev. A | Page 38 of 44

POST ADC GAIN CHANNEL 2 CONTROL REGISTER

Address: 0x0B, Reset: 0xA0, Name: POSTADC_GAIN2

Table 26. Bit Descriptions for POSTADC_GAIN2

Bits Bit Name Settings Description Reset Access

[7:0]

PADC_GAIN2

Channel 2 Post ADC Gain

0xA0

00000000

+60 dB Gain

00000001 +59.625 dB Gain

00000010

+59.25 dB Gain

...

10011111

+0.375 dB Gain

10100000

0 dB Gain

10100001 −0.375 dB Gain

...

11111110

−35.625 dB Gain

11111111

Mute

POST ADC GAIN CHANNEL 3 CONTROL REGISTER

Address: 0x0C, Reset: 0xA0, Name: POSTADC_GAIN3

Table 27. Bit Descriptions for POSTADC_GAIN3

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

PADC_GAIN3

Channel 3 Post ADC Gain

0xA0

00000000 +60 dB Gain

00000001

+59.625 dB Gain

00000010

+59.25 dB Gain

...

10011111

+0.375 dB Gain

10100000 0 dB Gain

10100001

−0.375 dB Gain

...

11111110

−35.625 dB Gain

11111111

Mute

Data Sheet ADAU1978

Rev. A | Page 39 of 44

POST ADC GAIN CHANNEL 4 CONTROL REGISTER

Address: 0x0D, Reset: 0xA0, Name: POSTADC_GAIN4

Table 28. Bit Descriptions for POSTADC_GAIN4

Bits Bit Name Settings Description Reset Access

[7:0] PADC_GAIN4 Channel 4 Post ADC Gain 0xA0 RW

00000000 +60 dB Gain

00000001 +59.625 dB Gain

00000010 +59.25 dB Gain

...

10011111 +0.375 dB Gain

10100000 0 dB Gain

10100001 −0.375 dB Gain

... ...

11111110 −35.625 dB Gain

11111111

Mute

ADAU1978 Data Sheet

Rev. A | Page 40 of 44

HIGH-PASS FILTER AND DC OFFSET CONTROL REGISTER AND MASTER MUTE REGISTER

Address: 0x0E, Reset: 0x02, Name: MISC_CONTROL

Table 29. Bit Descriptions for MISC_CONTROL

Bits Bit Name Settings Description Reset Access

[7:6] SUM_MODE Channel Summing Mode Control for Higher SNR 0x0 RW

00 Normal 4-Channel Operation

01 2-Channel Summing Operation (See the ADC Summing Modes Section)

10 1-Channel Summing Operation (See the ADC Summing Modes Section)

11 Reserved

5 RESERVED Reserved 0x0 RW

4 MMUTE Master Mute 0x0 RW

Normal Operation

1 All Channels Muted

[3:1] RESERVED Reserved 0x0 RW

0 DC_CAL DC Calibration Enable 0x0 RW

0 Normal Operation

1 Perform DC Calibration

Data Sheet ADAU1978

Rev. A | Page 41 of 44

ADC CLIPPING STATUS REGISTER

Address: 0x19, Reset: 0x00, Name: ASDC_CLIP

Table 30. Bit Descriptions for ASDC_CLIP

Bits Bit Name Settings Description Reset Access

[7:4] RESERVED Reserved 0x0 RW

3 ADC_CLIP4 ADC Channel 4 Clip Status 0x0 R

0 Normal Operation

1 ADC Channel Clipping

2 ADC_CLIP3 ADC Channel 3 Clip Status 0x0 R

0 Normal Operation

1 ADC Channel Clipping

1 ADC_CLIP2 ADC Channel 2 Clip Status 0x0 R

0 Normal Operation

1 ADC Channel Clipping

0 ADC_CLIP1 ADC Channel 1 Clip Status 0x0 R

0 Normal Operation

1 ADC Channel Clipping

ADAU1978 Data Sheet

Rev. A | Page 42 of 44

DIGITAL DC HIGH-PASS FILTER AND CALIBRATION REGISTER

Address: 0x1A, Reset: 0x00, Name: DC_HPF_CAL

Table 31. Bit Descriptions for DC_HPF_CAL

Bits Bit Name Settings Description Reset Access

DC_SUB_C4

Channel 4 DC Subtraction from Calibration

0x0

0 No DC Subtraction

1 DC Value from DC Calibration Is Subtracted

DC_SUB_C3

Channel 3 DC Subtraction from Calibration

0x0

0 No DC Subtraction

1 DC Value from DC Calibration Is Subtracted

DC_SUB_C2

Channel 2 DC Subtraction from Calibration

0x0

0 No DC Subtraction

1 DC Value from DC Calibration Is Subtracted

4 DC_SUB_C1 Channel 1 DC Subtraction from Calibration 0x0 RW

0 No DC Subtraction

1 DC Value from DC Calibration Is Subtracted

3 DC_HPF_C4 Channel 4 DC High-Pass Filter Enable 0x0 RW

0 HPF Off

1 HPF On

2 DC_HPF_C3 Channel 3 DC High-Pass Filter Enable 0x0 RW

0 HPF Off

1 HPF On

1 DC_HPF_C2 Channel 2 DC High-Pass Filter Enable 0x0 RW

0 HPF Off

1 HPF On

0 DC_HPF_C1 Channel 1 DC High-Pass Filter Enable 0x0 RW

0 HPF Off

1 HPF On

Data Sheet ADAU1978

Rev. A | Page 43 of 44

TYPICAL APPLICATION CIRCUIT

Figure 44. Typical Application Circuit, Four Inputs, I2C and I2S Mode

11292-046

R17

C20

C21

4.87kΩ

2200pF

39nF

PLL INPUT OPTI O N

LRCLK MCLK

1kΩ

390pF

5600pF

NOTES

1. R9 , R10 = TYPICAL 2 KOHM.

2. R1 1 T HROUG H R1 4 USED FOR SET TING T HE DEVICE IN I

C MODE.

3. R1 6 = TYPICAL 4 7 KOHM .

4. PLL LO OP FILTER:

I2C/SPI

CONTROL

LINE1

C18

10µF C19

0.1µF

C20 C21

R17

+3 .3V (AVDD2)

10µF

ML CC X7R

C12

0.1µF

+3.3V

C13

0.1µF

C14

0.1µF

C15

0.1µF

R10

R11

R12

R16

0.1µF

C16

10µF

ML CC X7R

AIN1P

AVDD1

AVDD3

AVDD2

DVDD

IOVDD

LRCLK

BCLK

SDATAOUT1 TO DSP

IOVDD

SDATAOUT2

SCL/CCLK

SDA/COUT

ADDR1/CIN

ADDR0/CLATCH

PD/RST

+1. 8V OR + 3. 3V

AGND1 AGND3

AVDD2

AVDD1

PROGRAM MABLE GAI N

DECIMATOR/HPF

DC CALI BRATIO N

SERI AL AUDIO P ORT

AVDD3

ADC

3.3V TO 1. 8V

REGULATOR

ADC

AGND2 AGND2

AGND1

AGND2

AGND3

AGND4

AGND5

AGND6

DGND

VREF

MCLKIN

PLL_FILT

SA_MODE

R13 R14

AIN1N

AIN2P

AIN2N

AIN3P

AIN3N

AIN4P

AIN4N

LINE2

LINE3

LINE4

MICRO-

CONTROLLER

ADAU1978

REF PLL

MAX INPUT 2 V rms

DIFFERENTIAL

*FO R MO RE INFORMAT IO N ABOUT CALCUL ATING T HE VAL UE

FO R REXT, SEE T HE PO W ER-O N RESET SEQ UENCE SECTI ON.

REXT*

ADAU1978 Data Sheet

Rev. A | Page 44 of 44

OUTLINE DIMENSIONS

Figure 45. 40-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

6 mm × 6 mm Body, Very Very Thin Quad

(CP-40-14)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option

ADAU1978WBCPZ –40°C to +105°C 40-Lead LFCSP_WQ CP-40-14

ADAU1978WBCPZ-RL –40°C to +105°C 40-Lead LFCSP, 13” Tape and Reel CP-40-14

EVAL-ADAU1978Z Evaluation Board

1 Z = RoHS Compliant Part.

2 W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The ADAU1978WBCPZ models are available with controlled manufacturing to support the quality and reliability requirements of

automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore,

designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for

use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and

to obtain the specific Automotive Reliability reports for these models.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

0.50

BSC

BOTTOM VIEW

TOP VI EW

PI N 1

INDICATOR

EXPOSED

PAD

PI N 1

INDICATOR

SEATING

PLANE

0.05 M AX

0.02 NOM

0.20 RE F

COPLANARITY

0.08

0.30

0.25

0.18

6.10

6.00 S Q

5.90

0.80

0.75

0.70

FOR PRO P E R CONNECT ION OF

THE EXPOSED PAD, REFER TO

THE P IN CONFIGURATION AND

FUNCTION DESCRIPT IONS

SECTION OF THIS DATA SHEET.

0.45

0.40

0.35

0.25 M IN

4.05

3.90 S Q

3.75

COM P LIANT TO JEDEC S TANDARDS MO-220-WJJD.

05-06-2011-A

registered trademarks are the property of their respective owners.

D11292-0-1/14(A)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Analog Devices Inc.:

ADAU1978WBCPZ ADAU1978WBCPZ-RL EVAL-ADAU1978Z