DCQPACKAGE
SOT223
(TOPVIEW)
DBVPACKAGE
SOT23
(TOPVIEW)
IN
GND
EN NR/FB
OUT
1
2
34
5
1
IN
OUT
GND
NR/FB
EN
TABISGND
6
IN
N/C
N/C
EN
8
7
6
5
OUT
N/C
NR/FB
GND
1
2
3
4
DRB PACKAGE
3mmx 3mmSON
(TOP VIEW)
2 3 54
TPS736xx
GNDEN NR
IN OUT
VIN VOUT
Optional Optional
Optional
ON
OFF
TypicalApplicationCircuitforFixed-VoltageVersions
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
Cap-Free, NMOS, 400mA Low-Dropout Regulator
with Reverse Current Protection
1FEATURES DESCRIPTION
2• Stable with No Output Capacitor or Any Value
or Type of Capacitor The TPS736xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
• Input Voltage Range of 1.7V to 5.5V pass element in a voltage-follower configuration. This
• Ultra-Low Dropout Voltage: 75mV typ topology is stable using output capacitors with low
• Excellent Load Transient Response—with or ESR, and even allows operation without a capacitor.
without Optional Output Capacitor It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
• New NMOS Topology Delivers Low Reverse over all values of output current.
Leakage Current
• Low Noise: 30mVRMS typ (10Hz to 100kHz) The TPS736xx uses an advanced BiCMOS process
to yield high precision while delivering very low
• 0.5% Initial Accuracy dropout voltages and low ground pin current. Current
• 1% Overall Accuracy Over Line, Load, and consumption, when not enabled, is under 1mA and
Temperature ideal for portable applications. The extremely low
• Less Than 1mA max IQin Shutdown Mode output noise (30mVRMS with 0.1mF CNR) is ideal for
powering VCOs. These devices are protected by
• Thermal Shutdown and Specified Min/Max thermal shutdown and foldback current limit.
Current Limit Protection space
• Available in Multiple Output Voltage Versions
– Fixed Outputs of 1.20V to 5.0V
– Adjustable Output from 1.20V to 5.5V
– Custom Outputs Available
APPLICATIONS
• Portable/Battery-Powered Equipment
• Post-Regulation for Switching Supplies
• Noise-Sensitive Circuitry such as VCOs
• Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
space
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
PRODUCT VOUT (2)
TPS736xx yy yz XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Zis package quantity.
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet
or see the TI website at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory
EEPROM programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PARAMETER TPS736xx UNIT
VIN range –0.3 to 6.0 V
VEN range –0.3 to 6.0 V
VOUT range –0.3 to 5.5 V
VNR, VFB range –0.3 to 6.0 V
Peak output current Internally limited
Output short-circuit duration Indefinite
Continuous total power dissipation See Thermal Information Table
Junction temperature range, TJ–55 to +150 °C
Storage temperature range –65 to +150 °C
ESD rating, HBM 2 kV
ESD rating, CDM 500 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
THERMAL INFORMATION TPS736xx(3)
THERMAL METRIC(1)(2) DRB DCQ DBV UNITS
8 PINS 6 PINS 5 PINS
qJA Junction-to-ambient thermal resistance(4) 47.8 70.4 180
qJCtop Junction-to-case (top) thermal resistance(5) 83 70 64
qJB Junction-to-board thermal resistance(6) N/A N/A 35 °C/W
yJT Junction-to-top characterization parameter(7) 2.1 6.8 N/A
yJB Junction-to-board characterization parameter(8) 17.8 30.1 N/A
qJCbot Junction-to-case (bottom) thermal resistance(9) 12.1 6.3 N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
.ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
.iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
.iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1mF, unless otherwise noted. Typical values are at TJ= +25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range(1) (2) 1.7 5.5 V
VFB Internal reference (TPS73601) TJ= +25°C 1.198 1.20 1.210 V
Output voltage range VFB 5.5 – VDO V
(TPS73601)(3)
VOUT Nominal TJ= +25°C –0.5 +0.5
Accuracy(1) %
over VIN, IOUT, VOUT + 0.5V ≤VIN ≤5.5V;
(4) –1.0 ±0.5 +1.0
and T 10mA ≤IOUT ≤400mA
ΔVOUT%/ΔVIN Line regulation(1) VO(nom) + 0.5V ≤VIN ≤5.5V 0.01 %/V
1mA ≤IOUT ≤400mA 0.002
ΔVOUT%/ΔIOUT Load regulation %/mA
10mA ≤IOUT ≤400mA 0.0005
Dropout voltage(5)
VDO IOUT = 400mA 75 200 mV
(VIN = VOUT(nom) – 0.1V)
ZO(DO) Output impedance in dropout 1.7V ≤VIN ≤VOUT + VDO 0.25 Ω
VOUT = 0.9 × VOUT(nom) 400 650 800 mA
ICL Output current limit 3.6V ≤VIN ≤4.2V, 0°C ≤TJ≤+70°C 500 800 mA
ISC Short-circuit current VOUT = 0V 450 mA
IREV Reverse leakage current(6) (–IIN) VEN ≤0.5V, 0V ≤VIN ≤VOUT 0.1 10 mA
IOUT = 10mA (IQ) 400 550
IGND GND pin current mA
IOUT = 400mA 800 1000
VEN ≤0.5V, VOUT ≤VIN ≤5.5,
ISHDN Shutdown current (IGND) 0.02 1 mA
–40°C ≤TJ≤+100°C
IFB FB pin current (TPS73601) 0.1 0.3 mA
f = 100Hz, IOUT = 400mA 58
Power-supply rejection ratio
PSRR dB
(ripple rejection) f = 10KHz, IOUT = 400mA 37
COUT = 10mF, No CNR 27 × VOUT
Output noise voltage
VNmVRMS
BW = 10Hz – 100KHz COUT = 10mF, CNR = 0.01mF 8.5 × VOUT
VOUT = 3V, RL= 30ΩCOUT = 1mF,
tSTR Startup time 600 ms
CNR = 0.01mF
VEN(HI) EN pin high (enabled) 1.7 VIN V
VEN(LO) EN pin low (shutdown) 0 0.5 V
IEN(HI) EN pin current (enabled) VEN = 5.5V 0.02 0.1 mA
Shutdown, temperature increasing +160
TSD Thermal shutdown temperature °C
Reset, temperature decreasing +140
TJOperating junction temperature –40 +125 °C
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤1.6V, the output will lock to VIN and may result in a damaging over-voltage level on the output. To
avoid this situation, disable the device before powering down the VIN.
(3) TPS73601 is tested at VOUT = 2.5V.
(4) Tolerance of external resistors not included in this specification.
(5) VDO is not measured for fixed output versions with VOUT(nom) < 1.8V.
(6) Fixed-voltage versions only; refer to Applications section for more information.
4Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
Servo
Error
Amp
Ref
27kΩ
8kΩ
Current
Limit
Thermal
Protection
Bandgap
NR
OUT
R1
R2
EN
GND
IN
R1+ R2= 80kΩ
4MHz
Charge Pump
VO
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
R1
Short
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
R2
Open
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
NOTE: VOUT = (R1 + R2)/R2 × 1 .204;
R1R2 ≅ 1 9kΩ f or best
accuracy.
Servo
Error
Amp
Ref
Current
Limit
Thermal
Protection
Bandgap
OUT
FB
R1
R2
EN
GND
IN
80kΩ
8kΩ
27kΩ
4MHz
Charge Pump
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Fixed Voltage Version
Figure 2. Adjustable Voltage Version
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
TABISGND
DCQPACKAGE
SOT223
(TOPVIEW)
5
IN
OUT
GND
NR/FB
EN
DBVPACKAGE
SOT23
(TOPVIEW)
IN
GND
EN 3 NR/FB
OUT1
2
5
4
IN
N/C
N/C
EN
8
7
6
5
OUT
N/C
NR/FB
GND
1
2
3
4
DRBPACKAGE
3mmx3mmSON
(TOPVIEW)
43
6
21
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
PIN CONFIGURATIONS
PIN DESCRIPTIONS
SOT23 SOT223 3x3 SON
(DBV) (DCQ) (DRB)
NAME PIN NO. PIN NO. PIN NO. DESCRIPTION
IN 1 1 8 Input supply
GND 2 3, 6 4, Pad Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
EN 3 5 5 regulator into shutdown mode. Refer to the Shutdown section under Applications
Information for more details. EN can be connected to IN if not used.
Fixed voltage versions only—connecting an external capacitor to this pin bypasses
NR 4 4 3 noise generated by the internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier,
FB 4 4 3 and is used to set the output voltage of the device.
OUT 5 2 1 Output of the Regulator. There are no output capacitor requirements for stability.
6Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
0.5
0.4
0.3
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
Change in VOUT (%)
0 50 100 150 300 350200 250 400
IOUT (mA)
Referred to IOUT = 10mA
−40_C
+125_C
+25_C
0.20
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
Change in VOUT (%)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VIN −VOUT (V)
+125_C+25_C
−40_C
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
100
80
60
40
20
0
VDO (mV)
0 50 100 150 200 400250 300 350
IOUT (mA)
+125_C
+25_C
−40_C
TPS73625DBV
100
80
60
40
20
0
VDO (mV)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS73625DBV
IOUT = 400mA
30
25
20
15
10
5
0
Percent of Units (%)
−1.0
−0.9
−0.8
−0.7
−0.6
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
VOUT Error (%)
IOUT = 10mA
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS
For all voltage versions, at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted.
LOAD REGULATION LINE REGULATION
Figure 3. Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE
Figure 5. Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM OUTPUT VOLTAGE DRIFT HISTOGRAM
Figure 7. Figure 8.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
1000
900
800
700
600
500
400
300
200
100
0
IGND (µA)
0 100 200 300 400
IOUT (mA)
VIN = 5.5V
VIN = 4V
VIN = 2V
1000
900
800
700
600
500
400
300
200
100
0
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
IOUT = 400mA
VIN = 5.5V
VIN = 3V
VIN = 2V
ICL
800
700
600
500
400
300
200
100
0
OutputCurrent(mA)
ISC
-0.5 0 1.0 1.5 2.0 2.5 3.0 3.5
OutputVoltage(V)
0.5
TPS73633
1
0.1
0.01
IGND (µA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
VENABLE = 0.5V
VIN = VO+ 0.5V
800
750
700
650
600
550
500
450
400
Current Limit (mA)
1.5 2.5 3.0 3.5 4.0 4.5 5.02.0 5.5
VIN (V)
800
750
700
650
600
550
500
450
400
Current Limit (mA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted. GROUND PIN CURRENT vs OUTPUT CURRENT GROUND PIN CURRENT vs TEMPERATURE
Figure 9. Figure 10.
GROUND PIN CURRENT in SHUTDOWN CURRENT LIMIT vs VOUT
vs TEMPERATURE (FOLDBACK)
Figure 11. Figure 12.
CURRENT LIMIT vs VIN CURRENT LIMIT vs TEMPERATURE
Figure 13. Figure 14.
8Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
40
35
30
25
20
15
10
5
0
PSRR(dB)
0.2
V V (V)-
IN OUT
Frequency=10kHz
C =10 F
V =2.5V
I =100mA
OUT
OUT
OUT
m
0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10k10
90
80
70
60
50
40
30
20
10
0
Ripple Rejection (dB)
100 1k 100k 1M 10M
Frequency (Hz)
IOUT = 1mA
COUT = 1µF
IOUT = Any
COUT = 0µF
VIN = VOUT + 1V
IOUT = 1mA
COUT = Any
IOUT = 1mA
COUT = 10µF
IOUT = 100mA
COUT = Any
IOUT = 100mA
COUT = 10µF
IO=100mA
CO=1µF
1
0.1
0.01
eN(µV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
COUT = 1µF
COUT = 0µF
COUT = 10µF
IOUT = 150mA
1
0.1
0.01
eN(µV/√Hz)
10 100 1k 10k 100k
Frequency (Hz)
IOUT = 150mA
COUT = 1µF
COUT = 0µF
COUT = 10µF
60
50
40
30
20
10
0
VN(RMS)
COUT (µF)
0.1 1 10
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
CNR = 0.01µF
10Hz < Frequency < 100kHz
140
120
100
80
60
40
20
0
VN(RMS)
CNR (F)
1p 10p 100p 1n 10n
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
COUT = 0µF
10Hz < Frequency < 100kHz
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted. PSRR (RIPPLE REJECTION) vs FREQUENCY PSRR (RIPPLE REJECTION) vs VIN – VOUT
Figure 15. Figure 16.
NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY
CNR = 0mF CNR = 0.01mF
Figure 17. Figure 18.
RMS NOISE VOLTAGE vs COUT RMS NOISE VOLTAGE vs CNR
Figure 19. Figure 20.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
10µs/div
100mV/tick
50mV/tick
20mV/tick
50mA/tick
VIN = 3.8V COUT = 0µF
COUT = 1µF
COUT = 10µF
10mA
400mA
VOUT
VOUT
VOUT
IOUT
10µs/div
50mV/div
50mV/div
1V/div
VOUT
VOUT
VIN
IOUT = 400mA
5.5V
4.5V
dVIN
dt = 0.5V/µs
COUT = 0µF
COUT = 100µF
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
100µs/div
1V/div
1V/div
RL= 20Ω
COUT = 10µF
2V
0V
RL= 1kΩ
COUT = 0µF
RL= 20Ω
COUT = 1µF
VOUT
VEN
6
5
4
3
2
1
0
−1
−2
Volts
50ms/div
VIN
VOUT
10
1
0.1
0.01
IENABLE (nA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted. TPS73633 TPS73633
LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 21. Figure 22.
TPS73633 TPS73633
TURN-ON RESPONSE TURN-OFF RESPONSE
Figure 23. Figure 24.
TPS73633
POWER UP / POWER DOWN IENABLE vs TEMPERATURE
Figure 25. Figure 26.
10 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
60
55
50
45
40
35
30
25
20
VN(rms)
CFB (F)
10p 100p 1n 10n
VOUT = 2.5V
COUT = 0µF
R1= 39.2kΩ
10Hz < Frequency < 100kHz
160
140
120
100
80
60
40
20
0
IFB (nA)
−50 −25 0 25 50 75 100 125
Temperature (_C)
25µs/div
200mV/div
200mV/div
VOUT
VOUT
IOUT
400mA
10mA
COUT = 0µF
CFB = 10nF
R1= 39.2kΩ
COUT = 10µF
5µs/div
100mV/div
100mV/div
VOUT
VOUT
VIN
4.5V
3.5V
COUT = 0µF
VOUT = 2.5V
CFB = 10nF
COUT = 10µF
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ= +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted. TPS73601 TPS73601
RMS NOISE VOLTAGE vs CFB IFB vs TEMPERATURE
Figure 27. Figure 28.
TPS73601 TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION LINE TRANSIENT, ADJUSTABLE VERSION
Figure 29. Figure 30.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
TPS736xx
GNDEN
ON
OFF
NR
IN OUT
VIN VOUT
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalbypass
capacitortoreduce
outputnoise.
TPS73601
GNDEN FB
IN OUT
VIN VOUT
VOUT = x1.204
(R1+ R2)
R2
R1CFB
R2
Optionalinputcapacitor.
Mayimprovesource
impedance,noise,orPSRR.
Optionaloutputcapacitor.
Mayimproveloadtransient,
noise,orPSRR.
Optionalcapacitor
reducesoutputnoise
andimproves
transientresponse.
OFF ON
VN+32mVRMS (R1)R2)
R2+32mVRMS VOUT
VREF
VN(mVRMS)+27ǒmVRMS
VǓ VOUT(V)
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
APPLICATION INFORMATION
For best accuracy, make the parallel combination of
The TPS736xx belongs to a family of new generation R1and R2approximately equal to 19kΩ. This 19kΩ,
LDO regulators that use an NMOS pass transistor to in addition to the internal 8kΩresistor, presents the
achieve ultra-low-dropout performance, reverse same impedance to the error amp as the 27kΩ
current blockage, and freedom from output capacitor bandgap reference output. This impedance helps
constraints. These features, combined with low noise compensate for leakages into the error amp
and an enable input, make the TPS736xx ideal for terminals.
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an INPUT AND OUTPUT CAPACITOR
adjustable output version. All versions have thermal REQUIREMENTS
and over-current protection, including foldback
current limit. Although an input capacitor is not required for
stability, it is good analog design practice to connect
Figure 31 shows the basic circuit connections for the a 0.1mF to 1mF low ESR capacitor across the input
fixed voltage models. Figure 32 gives the connections supply near the regulator. This counteracts reactive
for the adjustable output version (TPS73601). input sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
The TPS736xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nΩF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
Figure 31. Typical Application Circuit for applications, the sum of capacitor ESR and trace
Fixed-Voltage Versions resistance will meet this requirement.
OUTPUT NOISE
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS736xx and
it generates approximately 32mVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
(1)
Figure 32. Typical Application Circuit for Since the value of VREF is 1.2V, this relationship
Adjustable-Voltage Version reduces to:
R1and R2can be calculated for any output voltage
using the formula shown in Figure 32. Sample (2)
resistor values for common output voltages are
shown in Figure 2.for the case of no CNR.
12 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
VN(mVRMS)+8.5ǒmVRMS
VǓ VOUT(V)
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
An internal 27kΩresistor in series with the noise ENABLE PIN AND SHUTDOWN
reduction pin (NR) forms a low-pass filter for the The enable pin (EN) is active high and is compatible
voltage reference when an external noise reduction with standard TTL-CMOS levels. A VEN below 0.5V
capacitor, CNR, is connected from NR to ground. For (max) turns the regulator off and drops the GND pin
CNR = 10nF, the total noise in the 10Hz to 100kHz current to approximately 10nA. When EN is used to
bandwidth is reduced by a factor of ~3.2, giving the shutdown the regulator, all charge is removed from
approximate relationship: the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
(3) When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
for CNR = 10nF. discharged using this configuration, and the pass
This noise reduction effect is shown as RMS Noise transistor may be left on (enhanced) for a significant
Voltage vs CNR in the Typical Characteristics section. time after VIN has been removed. This scenario can
result in reverse current flow (if the IN pin is low
The TPS73601 adjustable version does not have the impedance) and faster ramp times upon power-up. In
NR pin available. However, connecting a feedback addition, for VIN ramp times slower than a few
capacitor, CFB, from the output to the feedback pin milliseconds, the output may overshoot upon
(FB) reduces output noise and improves load power-up.
transient performance. Note that current limit foldback can prevent device
The TPS736xx uses an internal charge pump to start-up under some conditions. See the Internal
develop an internal supply voltage sufficient to drive Current Limit section for more information.
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250mV of switching noise at DROPOUT VOLTAGE
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most The TPS736xx uses an NMOS pass transistor to
values of IOUT and COUT.achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
BOARD LAYOUT RECOMMENDATION TO device is in its linear region of operation and the
IMPROVE PSRR AND NOISE PERFORMANCE input-to-output resistance is the RDS-ON of the NMOS
pass element.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that For large step changes in load current, the TPS736xx
the board be designed with separate ground planes requires a larger voltage drop from VIN to VOUT to
for VIN and VOUT, with each ground plane connected avoid degraded transient response. The boundary of
only at the GND pin of the device. In addition, the this transient dropout region is approximately twice
ground connection for the bypass capacitor should the dc dropout. Values of VIN – VOUT above this line
connect directly to the GND pin of the device. ensure normal transient response.
Operating in the transient dropout region can cause
INTERNAL CURRENT LIMIT an increase in recovery time. The time required to
recover from a load transient is a function of the
The TPS736xx internal current limit helps protect the magnitude of the change in load current rate, the rate
regulator during fault conditions. Foldback current of change in load current, and the available
limit helps to protect the regulator from damage headroom (VIN to VOUT voltage drop). Under
during output short-circuit conditions by reducing worst-case conditions [full-scale instantaneous load
current limit when VOUT drops below 0.5V. See change with (VIN – VOUT) close to dc dropout levels],
Figure 12 in the Typical Characteristics section. the TPS736xx can take a couple of hundred
Note from Figure 12 that approximately –0.2V of VOUT microseconds to return to the specified regulation
results in a current limit of 0mA. Therefore, if OUT is accuracy.
forced below –0.2V before EN goes high, the device
may not start up. In applications that work with both a
positive and negative voltage supply, the TPS736xx
should be enabled first.
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
(Fixed Voltage Version)
dVńdt +VOUT
COUT 80kWøRLOAD
(Adjustable Voltage Version)
dVńdt +VOUT
COUT 80kWø(R1)R2)øRLOAD
TPS736xx
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
www.ti.com
TRANSIENT RESPONSE After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
The low open-loop output impedance provided by the that reverse current is specified as the current flowing
NMOS pass element in a voltage follower out of the IN pin due to voltage applied on the OUT
configuration allows operation without an output pin. There will be additional current flowing into the
capacitor for many applications. As with any OUT pin due to the 80kΩinternal resistor divider to
regulator, the addition of a capacitor (nominal value ground (see Figure 1 and Figure 2).
1mF) from the OUT pin to ground will reduce
undershoot magnitude but increase its duration. In For the TPS73601, reverse current may flow when
the adjustable version, the addition of a capacitor, VFB is more than 1.0V above VIN.
CFB, from the OUT pin to the FB pin will also improve
the transient response. THERMAL PROTECTION
The TPS736xx does not have active pull-down when Thermal protection disables the output when the
the output is over-voltage. This allows applications junction temperature rises to approximately +160°C,
that connect higher voltage sources, such as allowing the device to cool. When the junction
alternate power supplies, to the output. This also temperature cools to approximately +140°C, the
results in an output overshoot of several percent if output circuitry is again enabled. Depending on power
load current quickly drops to zero when a capacitor is dissipation, thermal resistance, and ambient
connected to the output. The duration of overshoot temperature, the thermal protection circuit may cycle
can be reduced by adding a load resistor. The on and off. This limits the dissipation of the regulator,
overshoot decays at a rate determined by output protecting it from damage due to overheating.
capacitor COUT and the internal/external load Any tendency to activate the thermal protection circuit
resistance. The rate of decay is given by: indicates excessive power dissipation or an
inadequate heat sink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including heat sink), increase the ambient
(4) temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your application. This produces a
worst-case junction temperature of +125°C at the
(5) highest expected ambient temperature and
worst-case load.
REVERSE CURRENT The internal protection circuitry of the TPS736xx has
The NMOS pass element of the TPS736xx provides been designed to protect against overload conditions.
inherent protection against current flow from the It was not intended to replace proper heat sinking.
output of the regulator to the input when the gate of Continuously running the TPS736xx into thermal
the pass device is pulled low. To ensure that all shutdown degrades device reliability.
charge is removed from the gate of the pass element,
the EN pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
14 Submit Documentation Feedback Copyright © 2003–2010, Texas Instruments Incorporated
PD+(VIN *VOUT) IOUT
TPS736xx
www.ti.com
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010
POWER DISSIPATION space
(6)
The ability to remove heat from the die is different for
each package type, presenting different Power dissipation can be minimized by using the
considerations in the PCB layout. The PCB area lowest possible input voltage necessary to assure the
around the device that is free of other components required output voltage.
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards PACKAGE MOUNTING
are shown in the Thermal Information table. Using
heavier copper will increase the effectiveness in Solder pad footprint recommendations for the
removing heat from the device. The addition of plated TPS736xx are presented in Application Bulletin
through-holes to heat-dissipating layers will also Solder Pad Recommendations for Surface-Mount
improve the heat-sink effectiveness. Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
space REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision S (August, 2009) to Revision T Page
• Replaced Dissipation Ratings Table with Thermal Information Table .................................................................................. 3
Changes from Revision R (May, 2008) to Revision S Page
• Changed Figure 12 ............................................................................................................................................................... 8
• Added paragraph about recommended start-up sequence to Internal Current Limit section ............................................. 13
• Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section ................................ 13
Copyright © 2003–2010, Texas Instruments Incorporated Submit Documentation Feedback 15
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS73601DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73601DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73601DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73601DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73601DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73601DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73601DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73601DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73601DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73601DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS736125DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS736125DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS736125DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS736125DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73615DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73615DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73615DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS73615DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73615DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73615DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73615DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73615DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73615DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73615DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73616DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73616DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73618DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73618DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73618DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73618DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73619DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73619DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73619DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS73619DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73625DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73625DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73625DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73625DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU SN Level-2-260C-1 YEAR
TPS73630DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73630DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73630DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73630DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73632DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73632DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73632DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS73632DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73633DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73633DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73633DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73633DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DRBR ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DRBRG4 ACTIVE SON DRB 8 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DRBT ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73633DRBTG4 ACTIVE SON DRB 8 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS73643DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73643DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73643DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS73643DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 5
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73601, TPS73615, TPS73618, TPS73625, TPS73630, TPS73632, TPS73633 :
•Automotive: TPS73601-Q1
•Enhanced Product: TPS73601-EP, TPS73615-EP, TPS73618-EP, TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73601DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73601DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73601DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS73601DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS73601DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73601DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS736125DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS736125DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73615DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73615DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73615DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS73615DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73615DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73616DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73616DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73618DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73618DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73618DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS73619DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS73619DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
TPS73625DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73625DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73625DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS73630DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73630DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73630DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS73632DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73632DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73633DBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73633DBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS73633DCQR SOT-223 DCQ 6 2500 330.0 12.4 6.8 7.3 1.88 8.0 12.0 Q3
TPS73633DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73633DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS73643DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS73643DBVT SOT-23 DBV 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
*All dimensions are nominal
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS73601DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73601DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73601DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS73601DRBR SON DRB 8 3000 370.0 355.0 55.0
TPS73601DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73601DRBT SON DRB 8 250 220.0 205.0 50.0
TPS736125DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS736125DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73615DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73615DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73615DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS73615DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73615DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73616DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73616DBVT SOT-23 DBV 5 250 203.0 203.0 35.0
TPS73618DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73618DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73618DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS73619DRBR SON DRB 8 3000 370.0 355.0 55.0
TPS73619DRBT SON DRB 8 250 220.0 205.0 50.0
TPS73625DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73625DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73625DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS73630DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73630DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73630DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS73632DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73632DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73633DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TPS73633DBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TPS73633DCQR SOT-223 DCQ 6 2500 358.0 335.0 35.0
TPS73633DRBR SON DRB 8 3000 367.0 367.0 35.0
TPS73633DRBT SON DRB 8 250 210.0 185.0 35.0
TPS73643DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS73643DBVT SOT-23 DBV 5 250 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated