Rev. B 03/14
9
LYT4221-4228/4321-4328
www.powerint.com
Maximum Input Capacitance
To achieve high power factor, the capacitance used in both the
EMI filter and for decoupling the rectified AC (bulk capacitor)
must be limited in value. The maximum value is a function of
the output power of the design and reduces as the output
power reduces. For the majority of designs limit the total
capacitance to less than 220 nF with a bulk capacitor value of
100 nF. Film capacitors are recommended compared to
ceramic types as they minimize audible noise with operating
with leading edge phase dimmers. Start with a value of 10 nF
for the capacitance in the EMI filter and increase in value until
there is sufficient EMI margin.
REFERENCE Pin Resistance Value Selection
The LYTSwitch-4 high-line family contains phase dimming
devices, LYT4321-4328, and non-dimming devices, LYT4221-
4228. Both the non-dimmable devices and dimmable devices
use 24.9 kW ±1% REFERENCE pin resistor for best output
current tolerance (over AC input voltage changes).
VOLTAGE MONITOR Pin Resistance Network Selection
For widest AC phase angle dimming range with LYT4321-4328,
use a 4 MW resistor connected to the line voltage peak detector
circuit. Make sure that the resistor’s voltage rating is sufficient
for the peak line voltage. If necessary use multiple series
connected resistors.
Primary Clamp and Output Reflected Voltage VOR
A primary clamp is necessary to limit the peak drain to source
voltage. A Zener clamp requires the fewest components and
board space and gives the highest efficiency. RCD clamps are
also acceptable however the peak drain voltage should be care-
fully verified during start-up and output short-circuits as the
clamping voltage varies with significantly with the peak drain
current.
For the highest efficiency, the clamping voltage should be
selected to be at least 1.5 times the output reflected voltage,
VOR, as this keeps the leakage spike conduction time short.
When using a Zener clamp in a universal input or high-line only
application, a VOR of less than 135 V is recommended to allow
for the absolute tolerances and temperature variations of the
Zener. This will ensure efficient operation of the clamp circuit
and will also keep the maximum drain voltage below the rated
breakdown voltage of the FET. An RCD (or RCDZ) clamp
provides tighter clamp voltage tolerance than a Zener clamp.
The RCD clamp is more cost-effective than the Zener clamp but
requires more careful design to ensure that the maximum drain
voltage does not exceed the power FET breakdown voltage.
These VOR limits are based on the BVDSS rating of the internal
FET, a VOR of 90 V to 120 V is typical for most designs, giving
the best PFC and regulation performance.
Series Drain Diode
An ultrafast or Schottky diode in series with the drain is
necessary to prevent reverse current flowing through the device.
The voltage rating must exceed the output reflected voltage,
VOR. The current rating should exceed two times the average
primary current and have a peak rating equal to the maximum
drain current of the selected LYTSwitch-4 high-line device.
Line Voltage Peak Detector Circuit
LYTSwitch-4 high-line devices use the peak line voltage to
regulate the power delivery to the output. A capacitor value of
1 µF to 4.7 µF is recommended to minimize line ripple and give
the highest power factor (>0.9), smaller values are acceptable
but result in lower PF and higher line current distortion.
Operation with Phase Controlled Dimmers
Dimmer switches control incandescent lamp brightness by not
conducting (blanking) for a portion of the AC voltage sine wave.
This reduces the RMS voltage applied to the lamp thus reducing
the brightness. This is called natural dimming and the LYTSwitch-4
high-line LYT4321-4328 devices when configured for dimming
utilize natural dimming by reducing the LED current as the RMS
line voltage decreases. By this nature, line regulation performance
is purposely decreased to increase the dimming range and
more closely mimic the operation of an incandescent lamp.
Leading Edge Phase Controlled Dimmers
The requirement to provide flicker-free output dimming with low-
cost, TRIAC-based, leading edge phase dimmers introduces a
number of trade-offs in the design.
Due to the much lower power consumed by LED based lighting
the current drawn by the overall lamp is below the holding
current of the TRIAC within the dimmer. This causes undesirable
behaviors such as limited dimming range and/or flickering. The
relatively large impedance the LED lamp presents to the line
allows significant ringing to occur due to the inrush current
charging the input capacitance when the TRIAC turns on. This
too can cause similar undesirable behavior as the ringing may
cause the TRIAC current to fall to zero and turn off.
To overcome these issues two circuits, the active damper and
passive bleeder, are incorporated. The drawback of these
circuits is increased dissipation and therefore reduced efficiency
of the supply so for non-dimming applications these components
can simply be omitted.
Figure 10(a) shows the line voltage and current at the input of a
leading edge TRIAC dimmer with Figure 10(b) showing the
resultant rectified bus voltage. In this example, the TRIAC
conducts at 90 degrees.
Figure 11 shows undesired rectified bus voltage and current
with the TRIAC turning off prematurely and restarting.
If the TRIAC is turning off before the end of the half-cycle
erratically or alternate half AC cycles have different conduction
angles then flicker will be observed in the LED light due to
variations in the output current. This can be solved by including
a bleeder and damper circuit.
Dimmers will behave differently based on manufacturer and
power rating, for example a 300 W dimmer requires less
dampening and requires less power loss in the bleeder than a
600 W or 1000 W dimmer due to different drive circuits and
TRIAC holding current specifications. Line voltage also has a
significant impact as at high-line for a given output power the