Features e High speed ta, = ns CMOS for optimum speed/power @ Low active power T770 mW e Low standby power 165 mW @ Automatic power-down when deselected @ TIL-compatible inputs and outputs Easy memory expansion with CEj, CY7C109 Functional Description The CY7C109 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE}), an active HIGH chip enable (CE2), an active LOW output enable (OB), and three-state drivers. This device has an au- tomatic power-down feature that reduces power consumption by more than 75% when deselected. Writing to the device is accomplished by taking chip enable one (CE}) and write en- 128K x 8 Static RAM into the location specified on the address pins (Ag through Aj6}. Reading from the device is accomplished by taking chip enable one (CE,) and out- put enable (OE) LOW while forcing write enable (WE) and chip enable two (CE) HIGH. Under these conditions, the con- tents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (1/Og through 1/07) are placed in a high-impedance state when the device is deselected (CE, HIGH or CE; LOW), the outputs are disabled (OE HIGH), or during a write operation (CE, LOW, CE, HIGH, and WE LOW). CE;, and OE options able (WE) inputs LOW and chip enable two (CE)) input HIGH. Data onthe eight The CY7C109 is available in standard VYOpins (/Oothrough/O7)}isthenwritten 400-mil-wide DIPs and SOJs. Logic Block Diagram Pin Configurations DIP/SOJ Top View INPUT BUFFER 512x256 x 8 ARRAY ROW DECODER cE, COLUMN GEy DECODER WE rrrentee Citta cot SENSE AMPS VOo VO, VO. Vs VO, VOs VO VO Selection Guide ime (ns Maximum ay ating Current (mA Maximum Current (mA Cypress Semiconductor Corporation Commercial 7C109-15 155 3901 North First Street @ San Jose 7C10925 7C10935 135 125 CA 95134 @ 408-943-2600 July 1990 Revised April 1996CY7C109 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Current into Outputs (LOW) ................00000- 20mA not tested.) Static Discharge Voltage ......0.. 0.0 .s sess sees >2001V Storage Temperature ............0000055 -65Cto 150C (per MIL-STD-883, Method 3015) Ambient Temperature with Latch-Up Current 2.0.0... .. 00. cece eee eee ees >200 mA Power Applied ............c cee eee eee es 55C to +125C . Supply Voltage on Vcc to Relative GNDU) .. -0.5V to +7.0V Operating Range DC Voltage Applied to Outputs Ambient 0 in High Z Statel!] ................... -0.5V to Vcc +0.5V Range Temperature Vee DC Input Voltagel!) .... 0... -0.5V to Vcc +0.5V Commercial 0C to +70C 3V + 10% Electrical Characteristics Over the Operating Rangel?) 7C109-15 7C10920 7C109-25 7C10935 Pa- rame- ter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou |Output HIGH | Vec=Min.,Ioq=-40mA] 24 24 2.4 24 Vv Voltage VoL | Output LOW | Vcc = Min., IoL = 8.0 mA 0.4 0.4 0.4 0.4 Vv Voltage Vin_ (| Input HIGH 22 | Vcc 22 | Vcc 2.2 | Voc 22 | Vec Vv Voltage +03 +03 +03 +03 VIL Input LOW Volt- -03/ 08 |-03] 08 |-03] 08 |-03 ] 08 Vv age! lx Input Load Cur- | GND < V, < Vcc -1 +1 -1 +1 -1 +1 -1 +1 pA rent loz Output Leakage | GND < V] < Vcc, -5 +5 -5 +5 -5 +5 -5 +5 pA Current Output Disabled los Output Short Vcc = Max. Vout = GND 300 300 -300 -300 | mA Circuit Cur- rentl4] Icc Vcc Operating | Voc = Max. Com'l 155 140 135 125 | mA Supply Current | Ioyur = 0 mA, f = fax = Ltre Ispi | AutomaticCE | Max. Voc, CE, > Vyyq | Com! 40 30 30 25 | mA Power-Down or CE) < VIL, Current VIN = Vin or TIL Inputs) | Vin < Vin f = fMax Isp2 | Automatic CE = | Max. Voc, Com! 10 10 10 10 mA Power-Down CE) = Vcc 03V, Current or CE) < 0.34, CMOS Inputs | Vin = Vcc 0.39, or Vin < 0.39, f=0 Capacitancel5] Parameter Description Test Conditions Max. Unit Cin Input Capacitance Ta = 25C, f = 1 MHz, 9 pF 7 Veco = 5.0V Cout Output Capacitance 9 pF Notes: 1. Viz (min.} = 2.0V for pulse durations of less than 20 ns. 4, Not more than one output should be shorted at one time. Duration of 2. Ty is the instant on case temperature. the short circuit should not exceed 30 seconds. 3. See the last page of this specification for Group A subgroup testing 5, Tested initially and after any design or process changes that may affect information. these parameters.CY7C109 AC Test Loads and Waveforms R1 4808 R1 4802 ALL INPUT PULSES Lh ___w 5V 3.0V 90% 90% OUTPUT ( OUTPUT ; I $ Re T $ R2 GND so" 30 rT J 2552 rT {2558 LL INCLUDING = = INCLUDING = = <3ns <3ns JIG AND JIG AND SCOPE (a) SCOPE (b) 109-3 109-4 Equivalent to: THEVENIN EQUIVALENT OUTPUT o ag 1.73V Switching Characteristics). Over the Operating Range 7C109-15 7C10920 7C10925 7C10935 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Min. | Unit READ CYCLE tre Read Cycle Time 15 20 25 35 ns tad Address to Data Valid 15 20 25 35 ns toHA Data Hold from Address Change 3 3 5 5 ns tace CE) LOW to Data Valid, CE HIGH to Data 15 20 25 35 ns a tpoE OE LOW to Data Valid 7 8 10 15 ns tLZOE OE LOW to Low Z 0 0 0 0 ns tHZOE OE HIGH to High Zl 5] 7 8 10 15 | ns tLzcE CE, LOW to Low Z, CE, HIGH to Low ZJ | 3 3 5 5 ns tHzcE CE, HIGH to High Z, CE, LOW to High ZI:3] 7 8 10 15 | ns teu CE LOW to Power-Up, CE2 HIGH to Power- | 0 0 0 0 ns Pp tpp CEy HIGH to Power-Down, CE; LOW to Pow- 15 20 25 35 ns er-Down WRITE CYCLE!! two Write Cycle Time 15 20 25 35 ns tscp CE LOW to Write End, CE, HIGH to Write | 12 15 20 25 ns n taw Address Set-Up to Write End 12 15 20 25 ns tHa Address Hold from Write End 0 0 0 0 ns tsa, Address Set-Up to Write Start 0 0 0 0 ns tpwE WE Pulse Width 12 15 20 25 ns tsp Data Set-Up to Write End 8 10 15 20 ns typ Data Hold from Write End 0 0 0 0 ns ttzwe | WE HIGH to Low Z) 3 3 5 5 nis tuzwE WE LOW to High zl? 3] 7 8 10 15 | ns Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing ref- erence levels of 1.5V, input pulse levels of Oto 3.0V, and output loading of the specified In _/Ioy and 30-pF load capacitance. tHzo08. tyzce. and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage. At any given temperature and voltage condition. tyzcp is less than tuzce. tyzor is less than tLzok. and tyzwep is less than th zwefor any given device. 9, The internal write time of the memory is defined by the overlap of CE, LOW. CE, HIGH, and WE LOW. CE, and WE must be LOW and CE, HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.CY7C109 =e : Oe PE hy ee eS S CoiRPR ES Switching Waveforms Read Cycle No, 1[19 11] tro ADDRESS * a tan h tou, * DATA OUT PREVIOUS DATA VALID KXXX DATA VALID 109-5 Read Cycle No. 2 (OE Controlled)[1. 12] ADDRESS CE, CE, tpoe HIGH IMPEDANCE tLz0E HIGH IMPEDANCE DATA OUT DATA VALID t LZCE tp Veco tpu SUPPLY 50% 50% Se CURRENT 188 Write Cycle No. 1 (CE, or CE; Controllea)l"3. 14] twe ADDRESS CE, CE, tpwe We _ tsp tup DATA VO DATA VALID 109-7 Notes: 10. Device is continuously selected. OE, CE, = Vy. CE: = Vin. 13. Data I/O is high impedance if OE = Vyy. 11. WE is HIGH for read cycle. 14. If CE; goes HIGH or CE goes LOW simultaneously with WE going 12. Address valid priorto or coincidentwith CE, transition LOW and CE) HIGH, the output remains in a high-impedance state. transition HIGH.ees CYPRESS Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE HIGH During Write): 14] a twe ADDRESS * tsce = OSs LL CY7C109 SS Le [* tsce * taw = tha * tsa - * tpwe = WE N iv NAN 7 oY e at tsp etien} typ 7 DATAI/O K DATAin VALID > Mt tHZ0E 09-8 Write Cycle No. 3 (WE Controlled, OE LOW)IN TAG. 14] a twe | ADDRESS * * tsce ~ CE, MAS LZ * x CE, Y MME QQ SN a tsce * aa: tow aE tH _ pt tsa tpwe > fT WE N 7 nt tsp apee] tip orravo KESEEK KOK owava | +X tuzwe [* > tLzwe >} Note: 15. During this period the 1/Os are in the output state and input signals should not be applied. 109-9CY7C109 Truth Table CE, | CE2 | OE | WE | 1/09 - I/O; Mode Power H x | X | X | HighZ Power-Down Standby (Isp) x L {|X |] X | HighZ Power-Down Standby (Isp) L | H | L | A ] Data Out Read Active (Icc} L H | X | L | DatalIn Write Active (Icc} L H | H | H | HighZ Selected, Outputs Disabled | Active (Icc} Ordering Information Speed Package Package Type Operating (ns) Ordering Code Name Range 15 CY7C10915PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109-15VC V33 32-Lead (400-Mil) Molded SOJ 20 CY7C10920PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C10920VC V33 32-Lead (400-Mil) Molded SOJ 25 CY7C10925PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109-25VC V33 32-Lead (400-Mil) Molded SO] 35 CY7C10935PC P43 32-Lead (400-Mil) Molded DIP | Commercial CY7C109-35VC V33 32-Lead (400-Mil) Molded SOJ Document #: 38-00140-GCY7C109 ae = mys Pe a wines ee aT PRESS Package Diagrams 32-Lead (400-Mil) Molded DIP P43 PI Loa no on on at DIMENSIONS IM INCHES MIlM, MAS, }) ) iSsr Trerspr Tree?) | 0.040 o.070 1580 - Ds Lec) ' SEATING PLANE = aes - T - oelo May, AA Biss 4 a 0.015 MIN, o.oie J 3 MIM, Te. nes i noe | nats 32-Lead (400-Mil) Molded SOJ V33 DIMENSIONS IM INCHE? MIM. DETAIL A Mas. PIN 1 1D ExTEPMAL LEAD DETIGN Doooooonooonoononmd - z . A re 435) Ly 4 a5 445 ANS DOUOUUOOUUDOUUDUDOOD DOD t { - ! Les os Tas af f j aC A Te. 25 MIM, Gypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ina Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or otherrights. Cypress Semicon- ductor does not authorize its products for use as critical components in life support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in lite support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.